JP2001051874A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer which can optionally specify trace conditions including a stored information amount. SOLUTION: The microcomputer 1A has a CPU 2 which executes instructions according to the decoding results of the instruction by an instruction decode 24. The CPU regards the decoding result of a trace information acquisition instruction as non-operation in actual chip mode and makes a trace control circuit 8A perform trace operation in evaluation mode according to the decoding result of the trace information acquisition instruction. The trace control circuit holds in a trace memory 9 the state in the microcomputer specified with the decoding result of the trace information acquisition instruction in timing specified with the decoding result of the mentioned instruction as well. The internal state to be trace and the tracing timing are both specified with the decoding result of the trace information acquisition instruction, thus trace conditions can optionally be specified including a stored information amount.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microcomputer, and more particularly to a technique for acquiring trace information for software debugging or system debugging of a microcomputer application system.

[0002]

2. Description of the Related Art In software debugging or system debugging of a microcomputer application system, a real-time trace function is used in which a program execution state of a microcomputer is sequentially sampled in synchronization with a bus cycle and stored in a trace buffer. In order to realize this, the microcomputer for evaluation has a debugging function of outputting the state of the internal address bus and the data bus to the outside from a debugging interface connected to a debugging device such as an emulator. A debugging device such as an emulator stores bus information output from the debugging interface of the evaluation microcomputer in a trace buffer for each bus cycle. Using the bus information stored in the trace buffer, system debugging and program debugging are performed while tracking the instruction execution state by the microcomputer.

An example of a document describing the trace function is an LSI handbook (November 3, 1984).
(0th day, published by Ohm Co., Ltd.).

[0004]

However, the conventional tracing function can specify tracing conditions, but does not have a function to arbitrarily specify the amount of accumulated information. Therefore, when information is supplied beyond the capacity of the trace buffer. However, there is a problem that old information is lost by the amount of information supplied beyond. As a result, there is a case where necessary information cannot be obtained even if a large-capacity trace buffer is used. Therefore, the present inventors have studied to make it possible to arbitrarily specify the trace condition including the amount of accumulated information. Further, in such a case, it is clear that the method cannot be applied to debugging of a system using a real-time OS (operating system) unless consideration is given to obtaining trace information so as not to hinder the real-time performance of the debugging process. Became.

[0005] It is an object of the present invention to provide a microcomputer capable of arbitrarily specifying a trace condition including the amount of stored information.

Another object of the present invention is to provide a microcomputer which enables acquisition of trace information so as not to hinder the real-time property of a debugging process.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

The microcomputer according to the first aspect of the present invention is a microcomputer having a so-called operation mode of an actual chip and an operation mode of an evaluation chip, which also has an evaluation function. This microcomputer (1A)
It has a CPU (2) for executing an instruction in accordance with the result of decoding the instruction by the instruction decoder (24), and an external bus interface circuit (7) which can be interfaced with the outside. The CPU, in a first operation mode such as a real chip mode, the non-operation of the decoding result of a specific debugging instruction such as a trace information acquisition instruction,
In a second operation mode such as an evaluation chip mode, a specific debug operation such as a trace operation is performed according to a result of decoding the specific debug instruction.
A) is executed. The debug control circuit holds the internal state of the microcomputer specified by the decoding result of the specific debugging instruction in the trace memory (9) at the timing specified by the decoding result of the specific debugging instruction. I do. The information stored in the trace memory can be output to the outside of the microcomputer.

According to the above, since both the internal state to be traced and the trace timing specified by the signal or the signal line are specified by the decoding result of the specific debug instruction, the accumulated information amount of the trace information is specified. The trace condition can be arbitrarily specified, including

Further, the microcomputer decodes the specific debug instruction in both the real chip mode and the evaluation mode, and in the first operation mode such as the real chip mode, the microcomputer decodes the specific debug instruction. Is processed as a non-operation. As a result, firstly, trace information can be acquired so as not to hinder the real-time property of the debugging process. That is, even in the actual chip mode, a substantially useless execution cycle of the debug instruction is inserted, and although the processing contents are different, the execution cycle is also inserted in the evaluation mode. Second, the trace points of both the internal state to be traced and the trace timing can be specified at the stage of assembly or compilation, and there is no need to set trace conditions of the trace circuit again at the time of evaluation. Therefore, it is possible to omit the logic means for setting the trace conditions from the emulator.

The microcomputer according to the second aspect of the present invention is a microcomputer dedicated to evaluation, such as a so-called evaluation chip. The microcomputer (1B) includes a CPU (2) for executing an instruction in accordance with a result of decoding the instruction by the instruction decoder (24), an external bus interface circuit (7) capable of interfacing with the outside, and an internal state of the microcomputer. Interface circuit (1
0). The CPU causes the debug control circuit (8B) to execute a specific debug operation such as a trace operation in accordance with a result of decoding a specific debug instruction such as a trace information acquisition instruction. The debug control circuit outputs the internal state of the microcomputer specified by the decoding of the specific debugging instruction to the outside from the evaluation interface circuit at the timing specified by the decoding of the specific debugging instruction. Is performed.

According to the microcomputer (1B), similarly to the above, it is possible to arbitrarily specify trace conditions including the amount of accumulated information of the trace information, to acquire the trace information so as not to hinder the real-time performance of the debugging process, Logic means for setting conditions can be omitted from the emulator.

The microcomputer (1A) serving both as the actual chip and the evaluation chip according to the first aspect, and the microcomputer (1B) dedicated to the evaluation chip according to the second aspect.
A microcomputer (1C) according to a third aspect having only a real chip function of executing a user program evaluated by a CPU (2) that executes an instruction in accordance with a result of decoding an instruction by an instruction decoder (24), and an external device And an external bus interface circuit (7) capable of interfacing. The CPU processes, as a non-operation, a decoding result of a specific debug instruction that causes a debugging microcomputer corresponding to the microcomputer to control a debugging operation.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [1] Microcomputer Combined with Actual Chip / Evaluation Chip FIG. 1 shows a first microcomputer 1A according to the present invention.
Is shown. Microcomputer 1A shown in FIG.
Is a microcomputer having a so-called actual chip and an operation mode of an evaluation chip, which also has an evaluation function.

Although not particularly limited, the microcomputer 1A is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The CPU (Central Processing Unit) 2 includes an instruction control unit 20, an instruction decoder 24, and an operation unit 21, which are representatively shown.

The instruction control unit 20 is connected to the instruction cache memory 3 via an instruction cache bus ICBUS, controls fetching and prefetching of an instruction to be executed, and executes an instruction execution sequence due to interruption or exception processing. To change the instruction address. CP
The instruction address to be executed by U2 is held by the program counter (PC) 22. The instruction to be executed by the CPU 2 is loaded into the instruction register (IR) 23. In the example of FIG. 1, an operation program of the CPU 2 is stored in a program memory (not shown) provided outside the microcomputer 1A. The instruction cache memory 3 holds some frequently executed programs among the programs held by the program memory. IRQi is an external interrupt request signal typically shown.

The instruction loaded in the instruction register 23 is decoded by the instruction decoder 24. The instruction decoder 24 generates various control signals inside the CPU 2 according to the decoding result.

The operation unit 21 includes a data cache bus DC
Connected to the data cache memory 4 via the BUS,
It has an arithmetic unit, a general-purpose register, and the like, and performs operations such as operand access and operand operation according to the decoding result of the instruction decoder 24. Necessary operands are obtained via the data cache memory 4 or as immediate data.

The instruction cache memory 3 and the data cache memory 4 are connected to a bus controller 5 via an internal bus IBUS. The bus controller 5 is connected to a peripheral circuit 6, an external bus interface circuit 7, and a trace memory 9 via a peripheral bus PBUS. The instruction cache memory 3 and the data cache memory 4
Gives a bus controller 5 an access address from the CPU 2 at that time when a cache miss occurs. The bus controller 5 controls an access cycle for fetching the data related to the cache miss according to the type of the access target circuit. If the access target is external, the bus cycle of the peripheral bus PBUS and the external bus cycle are controlled, and if the access target is the peripheral circuit 6, the peripheral bus cycle is controlled.

The operation mode of the microcomputer 1 is determined by the state of the mode signal MD at power-on reset. The mode control circuit 11 outputs the mode signal M
If D is a logical value "1", the microcomputer 1 sets the real chip mode (first operation mode). If the mode signal MD is a logical value "0", the microcomputer 1
Is set to the evaluation chip mode (second operation mode).
A general difference between the operation modes is an address map of the CPU 2 and the like. For example, in the real chip mode, some address areas accessible only in the privilege mode can be used for evaluation in the user mode.

Next, the trace function of the microcomputer 1A will be described. CPU2 includes in its instruction set:
A trace information acquisition instruction is included as a specific debug instruction. As shown in FIG. 3, the trace information acquisition instruction has a field A for specifying an operation code, a field B for specifying a signal position to be traced, and a field C for specifying a timing to be traced.

The trace information acquisition instruction is regarded as a non-operation instruction in the real chip mode. That is, the mode control circuit 11 sets the control signal 12 to the logical value “1” in the real chip mode, and sets the control signal 12 to the logical value “0” in the evaluation chip mode. The instruction decoder 24 receives the control signal 12. When the instruction decoder 24 recognizes the trace information acquisition instruction by decoding the operation code, if the control signal 12 has the logical value "1", the instruction decoder 24 replaces the decoding result with the decoding result of the non-operation code. Therefore, even if the trace information acquisition instruction is embedded in the operation program, the substantial processing by the instruction is not performed in the actual chip mode, and the trace information acquisition operation described later is skipped.

In the evaluation chip mode, the instruction decoder 2
4 decodes the trace information acquisition instruction, and causes the trace control circuit 8A to execute the trace by the control signal 25 according to the result of the decoding. That is, the trace control circuit 8A
Converts the signal at the signal position designated in the field B (the state inside the microcomputer) into the field C
At the timing designated by, the operation of holding the data in the trace memory 9 is performed. According to the example of FIG. 1, the signal position specified in the field B is information (instruction address, instruction information and control information) on the instruction cache bus ICBUS, and information (data address, data) on the data cache bus DCBUS. Information and control information), the value of the program counter PC, information (address, data information, instruction information and control information) on the internal bus IBUS, the peripheral bus P
It means any of information (address, data information, command information and control information) on the BUS. The timing specified by the field C is a timing at which the trace is started from the instruction execution cycle after the trace information acquisition instruction as a starting point, and ends in what cycle. Thus, for example, a trace operation such as tracing information on the instruction cache bus IBUS to the trace memory 9 for eight cycles after three cycles after decoding of the trace information acquisition instruction can be performed.

The trace memory 9 is, for example, assigned to a part of the address area accessible only in the privileged mode in the real chip mode, as described above.
Therefore, the trace operation does not compress the address space in the real chip mode. When the stored information in the trace memory is read out after the execution of the user program is finished, the CPU 2 can execute the system program or the debug support program in the privileged mode to access the trace memory 9.

According to the microcomputer 1A,
Both the internal state to be traced such as the bus state such as ICBUS, DCBUS, IBUS, and PBUS or the latch state of a specific circuit such as the program counter 22, and the trace timing such as the trace period are the trace information. Since the trace condition is specified by the decoding result of the acquisition instruction, the trace condition including the amount of trace information stored in the trace memory 9 can be arbitrarily specified. Therefore, if the storage capacity of the trace memory 9 is small,
Since the trace conditions can be specified at the instruction level in response, there is almost no loss of desired trace information.

The trace information acquisition instruction is decoded in both the real chip mode and the evaluation mode. In the real chip mode, the trace information acquisition instruction is processed as a non-operation. This makes it possible to acquire trace information so as not to hinder the real-time performance of the debugging process.
That is, even in the actual chip mode, a substantially useless execution cycle of the trace information acquisition instruction is inserted, and although the processing content is different, the execution cycle is also inserted in the evaluation mode. Furthermore, the trace points of both the internal state to be traced and the trace timing can be specified at the stage of assembly or compilation, and there is no need to set the trace conditions of the trace circuit again at the time of evaluation. Therefore, it is possible to omit the logic means for setting the trace conditions from the emulator.

[2] Evaluation Chip Dedicated Microcomputer FIG. 2 shows an example in which the trace mechanism based on the trace information acquisition instruction is applied to an evaluation chip dedicated microcomputer. The difference from FIG. 1 is that the trace control circuit 8B
And the point that an evaluation interface circuit 10 is provided in place of the trace memory 9. That is, the evaluation interface circuit 10 outputs the internal state of the microcomputer 1B to the outside for evaluation. The CPU 2
The instruction decoder 24 causes the trace control circuit 8B to execute a trace information acquisition operation in accordance with the result of decoding the trace information acquisition instruction. Since the microcomputer 1B is dedicated to the evaluation chip, the control signal 12 is fixed to a logical value "0" by pull-down, and control for making the trace operation non-operation is unnecessary. The trace control circuit 8B selects the signal at the signal position specified in the field B at the timing specified in the field C in accordance with the control signal 25 which is the interpretation of the trace information acquisition instruction, as in FIG. Then, an operation of outputting the evaluation interface circuit 10 to the outside is performed.

According to the microcomputer 1B of FIG. 2, similarly to FIG. 1, it is possible to arbitrarily specify the trace conditions including the amount of accumulated trace information, and acquire the trace information so as not to hinder the real-time performance of the debugging process. Thus, it is possible to omit the logic means for setting the trace conditions from the emulator.

[3] Microcomputer dedicated to real chip FIG. 3 shows an example of a microcomputer 1C dedicated to real chip. The difference from FIG. 1 is that the trace control circuit 8A for tracing and the trace memory 9 are deleted. The CPU 2 is the same as that of FIG. 1, and its instruction set includes the trace information acquisition instruction. However, since the microcomputer 1C is dedicated to the real chip, the control signal 12 is fixed to a logical value "1" by pull-up, and the trace operation is always set to non-operation even if the trace information acquisition instruction is fetched. It is supposed to.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, a trace memory may be provided inside a structure dedicated to the evaluation chip. Reading from the trace memory can be performed via the evaluation interface circuit.

The CPU may execute instructions in a multi-stage pipeline. Further, the CPU may employ a real-time OS. The connection between the CPU and the internal bus may not be performed via the cache memory. The cache memory may be a unified cache memory in which instructions and data are mixed. The microcomputer incorporates various peripheral circuits such as a timer counter and a serial interface, and may further include a bus master such as a direct memory access controller and an accelerator unit such as a floating point unit.

[0034]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since both the internal state to be traced and the trace timing are specified by the decoding result of the specific debug instruction, the trace condition including the accumulated information amount of the trace information can be arbitrarily specified.

In either case of the real chip mode or the evaluation mode, the specific debug instruction is decoded, and in the first operation mode such as the real chip mode, the specific debug instruction is processed as a non-operation. Therefore, the trace information can be acquired so as not to hinder the real-time property of the debugging process.

Moreover, the trace points can be specified at the stage of assembly or compilation, so that it is not necessary to set the trace conditions of the trace circuit again at the time of evaluation, and it is possible to omit the logic means for setting the trace conditions from the emulator. Become.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microcomputer for both a real chip and an evaluation chip according to an example of the present invention.

FIG. 2 is a block diagram of a microcomputer dedicated to an evaluation chip according to another example of the present invention.

FIG. 3 is a block diagram of a real-chip dedicated microcomputer according to yet another example of the present invention.

FIG. 4 is a format diagram showing an example of a trace information income instruction.

[Explanation of symbols]

Reference Signs List 1A Microcomputer for both real chip and evaluation chip 1B Microcomputer for evaluation chip 1C Microcomputer for real chip 2 CPU 3 Instruction cache memory 4 Data cache memory 5 Bus controller 7 External bus interface circuit 8A, 8B Trace control circuit 9 Trace Memory 10 Evaluation interface circuit 11 Mode control circuit 20 Instruction control unit 21 Operation unit 22 Program counter 23 Instruction register 24 Instruction decoder

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shinjiro Yamada 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5B033 BA02 BE07 FA24 5B042 GA13 HH30 KK06 LA11 MA08 MA20 MC03 MC09

Claims (5)

[Claims] 1. A CPU for executing an instruction in accordance with a result of decoding of an instruction by an instruction decoder, and an external bus interface circuit capable of interfacing with an external device, wherein the CPU has a specific debugging function in a first operation mode. The result of decoding the instruction is non-operational and the second
Causing the debug control circuit to execute a specific debug operation in accordance with the result of decoding the specific debug instruction in the operation mode, wherein the state of the microcomputer specified by the result of decoding the specific debug instruction is In the trace memory at the timing specified by the decoding result of the specific debug instruction. The information stored in the trace memory is configured to be output to the outside. And a microcomputer. 2. The first operation mode is a real chip mode in which an evaluation regarding a microcomputer is not performed.
2. The system according to claim 1, wherein the second operation mode is an evaluation mode for performing an evaluation on the microcomputer.
The microcomputer as described. 3. A CPU for executing an instruction according to a result of decoding of an instruction by an instruction decoder, an external bus interface circuit capable of interfacing with an external device, and an evaluation device capable of outputting an internal state of the microcomputer to an external device for evaluation. An interface circuit, wherein the CPU causes a debug control circuit to execute a specific debug operation in accordance with a result of decoding the specific debug instruction, and the debug control circuit is specified by the result of decoding the specific debug instruction. A microcomputer which outputs the internal state of the microcomputer to the outside from the evaluation interface circuit at a timing designated by the decoding result of the specific debug instruction. 4. A microcomputer comprising: a CPU for executing an instruction in accordance with a result of decoding of an instruction by an instruction decoder; and an external bus interface circuit capable of interfacing with the outside, wherein the CPU corresponds to the microcomputer. A microcomputer which processes a decoding result of a specific debugging instruction which causes a debugging microcomputer to control a debugging operation as a non-operation. 5. The microcomputer according to claim 1, wherein the specific debug instruction is a trace information acquisition instruction.