JP2001044776A - Variable gain amplifier and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a variable gain amplifier to be in operation even at a low voltage. SOLUTION: This variable gain amplifier is provided with attenuator circuits 31-33 in cascade connection with respect to an input signal, amplifiers 41-43 to which each output signal of the attenuator circuits 31-33 is supplied, resistors R61, R62 connected in common to output terminals of the amplifiers 41-43, and a constant current source 60 in common to the amplifiers 41-43. Transistors(TRs) Q13-Q33 are provided respectively in series with current lines between the amplifiers 41-43 and the constant current source 60. Selectively on/off- controlling the TRs Q13-Q33 according to a control signal can obtain output signals from the resistors R61, R62 whose level is controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a variable gain amplifier and a receiver using the same.

[0002]

2. Description of the Related Art As digital audio broadcasting, DAB (digital audio broadcasting according to the Eureka 147 standard) is adopted in Europe, and ISDB-T is proposed in Japan.

[0003] ISDB-T has a transmission bandwidth of 432 kHz (in the case of narrow-band ISDB-T). Modulation method: OFDM multiplexing method: By adopting MPEG2, digital audio data and digital data of a plurality of channels can be simultaneously transmitted. Broadcast.

[0004] The frequency band used for broadcasting is 88 MHz to 108 MHz and 170 MHz in the narrow band ISDB-T.
~ 222 MHz is planned.

[0005]

The AM receiver is provided with an AGC circuit, which controls the level of the AM detection output so as to be constant irrespective of the received electric field strength. That is, a variable gain amplifier is provided in a signal line of a high frequency signal or an intermediate frequency signal, and the gain of the variable gain amplifier is A
Feedback control is performed by a DC voltage (AGC voltage) included in the M detection output.

As a variable gain amplifier, for example, there is a circuit as shown in FIG. That is, the output signal of the signal source A10 is sequentially supplied to the attenuator circuits A11 to A13,
From the attenuator circuits A11 to A13, signals whose levels are sequentially reduced are output. The output signal is supplied to the differential amplifiers A21 to A23, respectively, and the output signal of the signal source A10 is supplied to the differential amplifier A20. Further, the differential amplifiers A20 to A23 share common load resistors Ra, R
Connected to b.

The following operation is performed according to the magnitude relationship between the control voltage VCTL and the bias voltages Va, Vb, Vc.

(1) When VCTL <Va Since the transistor Qa is turned on and the transistor Qb is turned off, the constant current source Qg is connected to the differential amplifier A20, and only the differential amplifier A20 becomes effective. Operate. Therefore, the output signal of the signal source A10 is taken out to the resistors Ra and Rb through the differential amplifier A20.

(2) When Va <VCTL <Va + Vb The transistor Qa is turned off, the transistor Qb is turned on, the transistor Qc is turned on, and the transistor Qd is turned off. As a result, the differential amplifier A21 only operates effectively. Therefore, the attenuator circuit A
The output signal of 11 is passed through a differential amplifier A21 to a resistor Ra,
Rb.

(3) When Va + Vb <VCTL <Va + Vb + Vc Since the transistor Qe is turned on and only the differential amplifier A22 operates effectively, the output signal of the attenuator circuit A12 is connected to the resistor through the differential amplifier A22. It is taken out to Ra and Rb.

(4) When VCTL> Va + Vb + Vc Since the transistor Qf is turned on and only the differential amplifier A23 operates effectively, the output signal of the attenuator circuit A13 is supplied to the resistors Ra and Rb through the differential amplifier A23. Is taken out.

Therefore, the circuit shown in FIG.
It operates as a variable gain amplifier whose gain changes in four stages depending on L.

Further, the transistors Qa to Qf
Is also operated in the active region, so that the transistor Q
The collector currents of a, Qc, Qe and Qf are controlled by the control voltage VCT.
For example, when L is changed as shown in FIG. 7, the gain can be changed continuously.

That is, for example, when VCTL = Va, the output current of the constant current source Qg is determined by the transistors Qa and Qc.
The differential amplifiers A20 and A21 operate effectively. Therefore,
The output signal of the signal source A10 is taken out through the differential amplifier A20, and the output signal of the attenuator circuit A11 is output from the differential amplifier A20.
At this time, the output current of the differential amplifier A20 and the output current of the differential amplifier A21 are added in the resistors Ra and Rb.

However, at this time, the differential amplifiers A20, A21
Is the current obtained by shunting the output current of the constant current source Qg, and is smaller than when the transistors Qa and Qc are completely turned on. Therefore, the gain of the differential amplifiers A20 and A21 is as follows. It is smaller than when it is completely on.

Therefore, when VCTL = Va, the variable gain amplifier has a gain when only the differential amplifier A20 is effectively operating and a gain when only the differential amplifier A21 is effectively operating. Gain between the two. And
If the control voltage VCTL moves away from the reference voltage Va, the ratio when the output current of the constant current source Qg is shunted to the transistors Qa and Qc changes in accordance with the control voltage VCTL. It changes from the gain when VCTL = Va.

Accordingly, the variable gain amplifier has a continuous gain ranging from the maximum gain determined by the differential amplifier A20 to the minimum gain determined by the attenuator circuits A11 to A13 and the differential amplifier A23 in accordance with the control voltage VCTL. Will change.

Thus, although the circuit of FIG. 6 operates as a variable gain amplifier, the transistors Qa to Q
When f operates in the active region, about 0.5 V is required as the collector-emitter voltage. Further, between the collectors and the emitters of the transistors Qa to Qf, the power supply is stacked in three stages. Also, the differential amplifier A20
The transistors A23 to A23 require about 0.7 V as their base-emitter voltage.

Therefore, this variable gain amplifier requires an operating voltage of at least collector-emitter voltage × 3 + base-emitter voltage = 0.5 V × 3 + 0.7 V = 2.2 V as a whole. Not suitable for conversion.

Further, when the variable gain amplifier is used in the AGC circuit of the digital audio broadcasting receiver as described above, the variable gain amplifier is also required to have low distortion. That is, in DAB and ISDB-T, one broadcast wave is composed of a plurality of carrier signals. For example,
In the case of the narrow band ISDB-T, the broadcast wave is composed of 109 carrier signals distributed every 4 kHz in the mode 1 and distributed every 1 kHz in the mode 2.
It consists of 433 carrier signals.

Therefore, in a digital audio broadcasting receiver, if the linearity of the variable gain amplifier is poor, the received signal and the intermediate frequency signal passing through the variable gain amplifier will be distorted, and the distortion component will be reduced to the original carrier. Sometimes indistinguishable from a signal. Therefore, it is required that the variable gain amplifier used in the AGC circuit of the digital audio broadcasting receiver has less distortion.

The present invention seeks to solve the above problems.

[0023]

According to the present invention, for example, a plurality of attenuator circuits cascade-connected to an input signal, a plurality of amplifiers to which respective output signals of the plurality of attenuator circuits are respectively supplied, An extraction circuit commonly connected to the output terminals of the plurality of amplifiers, an operating current source common to the plurality of amplifiers, a current line between the plurality of amplifiers, and a current line between the operating current sources, respectively. Having a plurality of switch elements provided in series, and selectively controlling on / off of the plurality of switch elements according to a control signal to obtain a level-controlled output signal from the take-out circuit. It is a gain amplifier. Therefore, the plurality of amplifiers selectively and effectively operate according to the control signal, and the output signal of the attenuator circuit is extracted to the extraction circuit through the effectively operating amplifier.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [ISDB-T Receiver] ISDB
The -T receiver is configured, for example, as shown in FIG. FIG. 1 shows a case of a receiver for a narrow band ISDB-T, which is a case where a direct conversion system is configured.

That is, a broadcast wave of the narrow band ISDB-T is received by the antenna 11, and this received signal is supplied to an antenna tuning circuit 12 of an electronic tuning system, and a reception signal S12 of a target frequency is taken out. S12 is AG
It is supplied to mixer circuits 15A and 15B through a variable gain amplifier 13 for C and an inter-stage tuning circuit 14 of an electronic tuning system.

Further, an oscillation signal having a frequency twice as high as the carrier frequency (center frequency) of the reception signal S12 is formed in the PLL 21, and this oscillation signal is supplied to the frequency dividing circuit 22 and equal to the carrier frequency of the reception signal S12. Further, the frequency is divided into two signals whose phases are different from each other by 90 °, and the divided signal is supplied to the mixer circuits 15A and 15B as a local oscillation signal.

Thus, in the mixer circuits 15A and 15B, the received signal S12 is frequency-converted into baseband signals S15A and S15B whose phases are different from each other by 90 °, ie, I-axis and Q-axis baseband signals S15A and S15B.

At this time, from the PLL 21, the V
A part of the control voltage supplied to the variable capacitance diode of CO (not shown) is extracted, and this control voltage is supplied to the tuning circuit 1.
2 and 14 are supplied as tuning voltages, and tuning to the received signal S12 is realized.

The signals S15A and S15B from the mixer circuits 15A and 15B are supplied to the low-pass filters 16A and 16A, respectively.
B → AGC variable gain amplifiers 17A, 17B → Supplied to demodulation circuit 19 through signal lines of low-pass filters 18A, 18B. Although not shown, the demodulation circuit 19 performs complex Fourier transform, frequency deinterleaving, time deinterleaving, and digital decoding of a target channel among a plurality of channels in correspondence with a modulation process at the time of ISDB-T transmission. It performs demodulation processing such as audio data selection, error correction and data decompression.

Therefore, from the demodulation circuit 19, audio signals L and R of a target program out of a plurality of programs (channels) are extracted.

At this time, the low-pass filter 18
Signals S15A and S15B from A and 18B are supplied to an AGC detection circuit 25 to form an AGC voltage V25.
The C voltage V25 is supplied to the variable gain amplifiers 17A and 17B as a gain control signal.

Further, the signals S15A and S15B from the mixer circuits 15A and 15B are supplied to the AGC detection circuit 23 to form a delayed AGC voltage V23. The AGC voltage V23 is supplied to the addition circuit 24 and the AGC voltage V25. Is supplied to the adding circuit 24. Then, an addition voltage V24 of the AGC voltages V23 and V25 is taken out from the addition circuit 24,
This voltage V24 is supplied to the variable gain amplifier 13 as a gain control signal.

Therefore, AGC is performed on the reception signal S12 from the tuning circuit 12 by the AGC voltage V24, and the low-pass filter 16 is controlled by the AGC voltage V25.
AGC is performed on the baseband signals S15A and S15B from A and 16B. At this time, since the AGC voltage V24 is an added voltage of the delayed AGC voltage V23 and the AGC voltage V25, the AGC range for the reception signal S12 can be expanded.

The receiver is provided with tuning circuits 12, 1
4. PLL 21 VCO resonance circuit and demodulation circuit 19
Except for the above, a one-chip IC can be realized.

[Variable Gain Amplifier] Variable Gain Amplifier 13
Is cascaded, for example, as shown in FIG.
Stage attenuator circuits 31 to 33, and differential amplifiers 40 to 33 for selectively extracting input signals and output signals of respective stages.
43 and cascode amplifiers 51-54.

That is, in the variable gain amplifier 13 of FIG. 2, a series circuit of resistors R01 to R03 is connected to a secondary coil L12 of a tuning coil (not shown) of the tuning circuit 12,
From the tuning circuit 12, the received signal S12 is extracted in a balanced manner. At this time, the output impedance of the tuning circuit 12 is, for example, 50Ω.

The attenuator circuits 31 to 33 are configured, for example, as shown in FIG. That is, the capacitor C31 is connected between one input terminal T31 and the output terminal T33.
And a parallel circuit of a resistor R31 and a parallel circuit of a resistor R32 and a capacitor C32 between the output terminal T33 and the midpoint terminal T35. A capacitor C33 is connected between the other input terminal T32 and the output terminal T34.
A parallel circuit of a resistor R33 and a capacitor C34 is connected between the output terminal T34 and the midpoint terminal T35.

Thus, the balance type attenuator circuits 31 to 33 are respectively constituted by the elements R31 to R34 and C31 to C34.

The attenuator circuits 31 to 3
Numeral 3 also constitutes a balanced ladder attenuator circuit 30. Of the attenuator circuits 31 to 33, the output terminals T33 and T34 of the previous stage attenuator circuit are connected to the input terminals T31 and T32 of the next stage attenuator circuit. Connected. The input terminals T31, T31 of the attenuator circuit 31
32 is connected to the output terminal of the tuning circuit 12, that is, both ends of the resistor R02, and the terminals T35 are connected to each other.

In this case, the attenuator circuit 31
In each of ~ 33, it is assumed that C31 R31 = C32 R32 C33 R33 = C34 R34.

When the attenuation amounts of the attenuator circuits 31 to 33 are made equal, the values of the elements R31 to R34 and C31 to C34 of the attenuator circuit 31 and the elements R31 to R34 and C31 to C34 of the attenuator circuit 32 are set. Are equal to each other, and the value of the elements R32 and R34 of the attenuator circuit 33 is one of the values of the elements R32 and R34 of the attenuator circuit 31.
/ 2 times the elements C32 and C34 of the attenuator circuit 33.
Is twice the value of the elements C32 and C34 of the attenuator circuit 31.

Further, the attenuation per stage of each of the attenuator circuits 31 to 33 is 1 / n [times] (where n> 1).
Then, R32 / R31 = 2 / (n-1) C31 / C32 = 2 / (n-1) For example, the attenuation per stage is 8 dB.

Then, in FIG. 2, the transistor Q0
1. The emitter of Q02 is the switching transistor Q03
Is connected to a constant current source 60 having ground as a reference potential point to form a differential amplifier 40, and bases of transistors Q01 and Q02 are connected to both ends of a resistor R02, respectively.

Further, the emitters of the transistors Q11 and Q12 are connected to the constant current source 60 through the collector and the emitter of the switching transistor Q13 so that the differential amplifier 41
The bases of the transistors Q11 and Q12 are connected to the output terminals T33 and T34 of the attenuator circuit 31, respectively.

Further, transistors Q21 to Q23 and Q
The differential amplifiers 42 and 43 are similarly configured by 31 to Q33, and the bases of the transistors Q21 and Q22 are connected to the output terminals T33 and T34 of the attenuator circuit 32, respectively.
The base of the transistors Q31 and Q32 is an attenuator circuit 3.
3 are connected to output terminals T33 and T34, respectively. Also,
A DC bias power supply VBB is connected between the terminals T35 of the attenuator circuits 31 to 33 and the ground.

A DC bias power supply VB0 is connected between the base of the transistor Q03 and the ground, and a variable voltage source VB is connected between the bases of the transistors Q03, Q13, Q23 and Q33.
B1, VB2 and VB3 are connected respectively.

In this case, the output voltages VB1, VB2, VB3 of the variable voltage sources VB1, VB2, VB3 are controlled and changed by the AGC voltage V24, and the predetermined voltage level is VL.
, VM, VH (where VL <VM <VH), when V24 <VL, only the transistor Q03 is turned on. When VL≤V24 <VM, only the transistor Q13 is turned on. When VM ≤ V24 <VH, only the transistor Q23 is turned on. When VH ≤ V24, only the transistor Q33 is turned on. It changes to realize.

As an example, in the case of VB1 = −ΔV
(ΔV is negative on the transistor Q03 side,
The voltage on the 13th side is a positive polarity), VB2 = 0 and VB3 = 0. Then, the transistors Q03 and Q13 are connected to the constant current source 60.
, The transistor Q03 is turned on and the transistor Q13 is turned off. Since the transistors Q23 and Q33 have the same base bias voltage as the transistor Q13, the transistors Q23 and Q33 are also turned off. Therefore, this voltage distribution is as follows.

In the case of VB1 = ΔV, VB2 =
−ΔV, VB3 = 0. Then, the transistor Q03,
Since Q13 is differentially connected to the constant current source 60,
The transistor Q03 turns off and the transistor Q13 turns on. The transistors Q23 and Q33 are connected to the transistor Q03.
And the transistors Q23 and Q33 are also turned off. Therefore, this voltage distribution is as follows.

Further, in the case of VB1 = 0, VB2 =
ΔV, VB3 = −ΔV. Then, the transistor Q0
3. Since Q23 is differentially connected to the constant current source 60, the transistor Q03 is turned off, the transistor Q23 is turned on, and the transistor Q13 is turned on.
, The transistor Q13 is also turned off. Further, the transistor Q33 also has the same base bias voltage as the transistor Q03, so that the transistor Q33 is also turned off. Therefore, this voltage distribution is as follows.

In the case of VB1 = 0, VB2 =
0, VB3 = ΔV. Then, the transistors Q03, Q
Since 33 is differentially connected to the constant current source 60, the transistor Q03 is turned off and the transistor Q33 is turned on. The transistors Q13 and Q23 are connected to the transistor Q03.
And the transistors Q13 and Q23 are also turned off. Therefore, this voltage distribution is as follows.

By changing the polarities of the voltages VB1 to VB3 as described above in correspondence with the AGC voltage V24,
The transistors Q03 to Q33 can be turned on and off as indicated by.

Therefore, the control voltages VB1, VB2, VB3
Are transistors Q03 to Q33 corresponding to the AGC voltage V24.
, And the output current of the constant current source 60 is distributed to the collector currents I03, I13, I23, and I33. Alternatively, the control voltages VB1, VB2, and VB3 control the constant current source 60 by using the transistors (Q01, Q02) to (Q31, Q32).
, And selectively operate the corresponding one of the differential amplifiers 40 to 43 effectively.

The control voltages VB1, VB2, and VB3 are not limited to the on / off control described above, and when the voltage V24 is near the boundary of, the transistors corresponding to the boundary among the transistors Q03 to Q33 are activated. It also operates in the area. This will be described below with reference to FIG.

That is, FIG. 4 shows the AGC voltage V24 and the collector current I0 of the transistors Q03, Q13, Q23 and Q33.
3, I13, I23, and I33. And AGC
When the voltage V24 is in the range, the transistor Q03
Is on and the other transistors are off, so that the collector current I03 has a constant magnitude determined by the constant current source 60,
The collector currents I13, I23, I33 are zero.

However, even if the AGC voltage V24 is within the range, the transistor Q03 changes in the off direction and the collector current I03 gradually decreases as the AGC voltage V24 approaches. At this time, the transistor Q13 changes from off to on, and the collector current I13 gradually increases.

Then, when the AGC voltage V24 becomes empty, the collector current I03 further decreases and finally becomes 0, but the collector current I13 further increases, and a constant magnitude determined by the constant current source 60. It will be. And even if the AGC voltage V24 is in the range of
, The collector current I13 gradually decreases. At this time, the collector current I23 gradually increases.

Further, when the AGC voltage V24 is in the range, the collector currents I23 and I33 similarly change.

Therefore, near the boundary of, transistors Q03 to Q33 are operating in the active region.

The collectors of the transistors Q01 and Q11 are connected to the emitter of the transistor Q51 having a common base to form a cascode amplifier 51. The collectors of the transistors Q02 and Q12 are connected to the transistor Q51 having a common base.
The cascode amplifier 52 is configured by being connected to the emitter of the cascode amplifier 52.

Further, the collectors of the transistors Q21 and Q31 are connected to the emitter of the transistor Q53 whose base is grounded to form a cascode amplifier 53.
22, the collector of Q32 is a transistor Q54 with a common base.
And the cascode amplifier 54 is formed.

Furthermore, in this case, the transistors Q51, Q51
Each collector of 53 is connected to a common load resistor R61, and each collector of the transistors Q52 and Q54 is connected to a common load resistor R62. A signal obtained from these load resistors R61 and R62 is tuned to the next-stage tuning circuit. 14. Further, the emitters of the transistors Q51 to Q54 are pulled up to the power supply potential + VCC by the resistors R51 to R54.

According to such a configuration, when the reception signal S12 is output from the tuning circuit 12, this signal S12 is sequentially attenuated by a predetermined amount by the attenuator circuits 31 to 33,
Accordingly, the attenuator circuits 31 to 33 output the reception signals S12 whose levels are sequentially reduced by, for example, 8 dB.

The bias voltage from the DC bias power supply VBB is applied to the resistors R31 to R31 of the attenuator circuits 31 to 33.
It is supplied to the bases of the transistors Q01 to Q32 through R34.

When the AGC voltage V24 is:
Only the transistor Q03 is turned on by the control voltages VB1 to VB3, and the constant current source 60 is connected to the emitters of the transistors Q01 and Q02. Therefore, in the case of, the differential amplifier 40 operates effectively, and the transistor Q
01 and Q02 and the transistors Q51 and Q52 form cascode amplifiers 51 and 52. At this time, since the transistors Q13 to Q33 are off, the transistors of the differential amplifiers 41 to 43 and the cascode amplifiers 53 and 54 are off.

Therefore, in the case of
Is received by the differential amplifier 40 and output to the next stage through the cascode amplifiers 51 and 52.

When the AGC voltage V24 is, only the transistor Q13 is turned on by the control voltages VB1 to VB3, so that the differential amplifier 41 operates effectively. Therefore, the reception signal S12 output from the first-stage attenuator circuit 31 is selected by the differential amplifier 41 and output to the next stage through the cascode amplifiers 51 and 52.

Further, when the AGC voltage V24 is:
Only the transistor Q23 is turned on by the control voltages VB1 to VB3, and the differential amplifier 42 operates effectively. At this time, since the transistors Q03, Q13, and Q33 are off, the differential amplifiers 40, 41, and 43 and the cascode amplifier 5
Each of the transistors 1 and 52 is off.

Therefore, the received signal S12 output from the second-stage attenuator circuit 32 is selected by the differential amplifier 42 and the cascode amplifiers 53 and 54 are selected.
Is output through

When the AGC voltage V24 is:
Since only the transistor Q33 is turned on by the control voltages VB1 to VB3 and only the differential amplifier 43 operates effectively, the received signal S12 output from the third-stage attenuator circuit 33 is selected by the differential amplifier 43. And output through the cascode amplifiers 53 and 54.

Therefore, the circuit shown in FIG.
24 operates as a variable gain amplifier in which the gain changes in four stages.

Further, the variable gain amplifier further comprises:
Since the collector currents I03 to I33 of the transistors Q03 to Q33 are changed as shown in FIG. 7 and the transistors Q03 to Q33 are operated also in the active region, the gain can be continuously changed with respect to the control voltage VCTL. .

That is, for example, when V24 = VL, the output current of the constant current source 60 is reduced by the transistors Q03 and Q13.
Therefore, both of the differential amplifiers 40 and 41 operate effectively. Therefore, the output signal of the tuning circuit 12 is extracted through the differential amplifier 40, and is output from the attenuator circuit 31.
Is taken out through the differential amplifier 41, and at this time, the output current of the differential amplifier 40 and the output current of the differential amplifier 41 are added in the cascode amplifiers 51 and 52.

However, at this time, the differential amplifiers 40 and 41
Is the shunt current of the output current of the constant current source 60, and is smaller than when the transistors Q03 and Q13 are completely turned on. Therefore, the gain of the differential amplifiers 40 and 41 is It is smaller than when Q13 is completely on.

Therefore, when V24 = VL, this variable gain amplifier has a gain when only the differential amplifier 40 is operating effectively and a gain when only the differential amplifier 41 is operating effectively. Gain between the two. And A
If the GC voltage V24 moves away from the reference voltage VL, the ratio when the output current of the constant current source 60 is shunted to the transistors Q03 and Q13 changes according to the AGC voltage V24.
The gain of the variable gain amplifier changes from the gain when V24 = VL.

Therefore, the variable gain amplifier has a continuous gain ranging from the maximum gain determined by the differential amplifier 40 to the minimum gain determined by the attenuator circuits 31 to 33 and the differential amplifier 43, corresponding to the AGC voltage V24. Will change.

As described above, according to the circuit of FIG. 2, the output signals of the tuning circuit 12 and the attenuator circuits 31 to 33 are output from the differential amplifiers 40 to 43 in accordance with the AGC voltage V24.
Selected or synthesized by the cascode amplifier 51,
It is taken out through 52 or 53,54. Therefore, the circuit of FIG. 2 operates as the variable gain amplifier 13 whose gain changes continuously. At this time, AGC is performed.

In this case, in particular, according to the variable gain amplifier 13 described above, the collector-emitter of the transistors Q01 to Q32 and the base-emitter of the transistors Q03 to Q33 are connected in series.・ Emitter voltage + base-emitter voltage =
The device operates if there is an operating voltage of 0.5 V + 0.7 V = 1.2 V, which is suitable for reducing the voltage of the circuit.

Further, the reception signal S12 of an appropriate level among the output signals of the tuning circuit 12 and the attenuator circuits 31 to 33 is selected and taken out by the differential amplifiers 40 to 43, that is, the reception signal S12 is attenuated by the attenuator circuit. After setting the level to an appropriate level by 31 to 33, the differential amplifier 4
Since it is taken out from 0 to 43, generation of distortion can be suppressed.

Further, in the attenuator circuits 31 to 33, since the signal is divided or attenuated by the capacitors C31 to C34, the value of the resistors R31 to R34 is sufficiently compared with the output impedance of the tuning circuit 12 of 50Ω. 1.25 kΩ, for example, so that the noise figure is not deteriorated by the resistors R31 to R34, and a variable gain amplifier with little noise can be obtained.

Further, since the output current of the constant current circuit 60 flows selectively through all the transistors, unnecessary current is reduced and the circuit can be reduced in current. Further, since the bias voltage from the DC bias power supply VBB is supplied to the transistors Q01 to Q32 through the resistors R31 to R34, it is not necessary to newly provide a circuit for supplying the bias voltage to the transistors Q01 to Q32.

By adding the input capacitance of the transistors Q01 to Q32 to the value of the capacitors C31 to C34,
Its input capacitance can be ignored. In addition, C31
By setting R31 = C32 · R32 and C33 · R33 = C34 · R34, the frequency characteristics can be made flat. Therefore, the frequency characteristics can be broadened.

Further, for example, the reception signal S12 output from the attenuator circuit 33 is supplied to the load resistors R61, R61 through the differential amplifier 43 and the cascode amplifiers 53, 54.
When the signal is taken out to 62 (in the case of), since the transistors Q51 and Q52 are off, the reception signal S12 from the tuning circuit 12 leaks to the collector through the base-collector capacitance of the transistors Q01 and Q02. However, the leak signal is blocked by the transistors Q51 and Q52, and is not output to the load resistors R61 and R62. Therefore, the resistors R61 and R62 do not include the leak signal.
That is, the reception signal S12 of the target level is obtained.

Therefore, the attenuator circuits 31 to 33
When the attenuator circuits and the differential amplifiers corresponding to the differential amplifiers 41 to 43 are connected in multiple stages to widen the gain control range or widen the AGC range, this can be reliably realized. For example, if five stages of an attenuator circuit and a differential amplifier are connected in cascade and the attenuation per stage of the attenuator circuit is 8 dB, a variable gain range of 40 dB can be obtained.

Further, for example, the transistors Q51 and Q52
Is off, its emitter is pulled up to the power supply potential by the resistors R51 and R52.
Since the transistors 51 and Q52 are sufficiently off, leak signals leaking to the collectors through the base-collector capacitances CBC and CBC of the transistors Q01 and Q02 can be reliably prevented.

Further, for example, when the transistors Q51 and Q52 are off, their emitters are pulled up to the power supply potential by the resistors R51 and R52, and the base and collector are reverse-biased. Can be suppressed. Therefore, an input signal having a large level can be handled, and from this point, the gain control range can be widened.

Further, since the transistors Q51 to Q54 are cascode-connected to the differential amplifiers 40 to 43, even if the differential amplifiers 40 to 43 are connected in multiple stages, an increase in output parasitic capacitance can be suppressed. A decrease in gain at high frequencies can be suppressed.

Further, the frequency of the received signal S12 processed by the variable gain amplifier 13 can be made much higher than the frequency determined by the CR product of the element to be used. In this case, the attenuation of the attenuator circuits 31-33 Since the amount is determined only by the capacitance ratio of the capacitors C11 to C34, the transistor Q
It is only necessary to correct the input capacitance of 01 to Q32. Furthermore, I
C conversion is also possible.

[Another Example of ISDB-T Receiver] FIG.
This is a case where a receiver for narrowband ISDB-T is configured in a superheterodyne system.

That is, the broadcast wave of the narrow band ISDB-T is received by the antenna 11, and the received signal is supplied to the antenna tuning circuit 12 of the electronic tuning system, and the received signal S12 of the target frequency is taken out. S12 is AG
It is supplied to mixer circuits 15A and 15B through a variable gain amplifier 13 for C and an inter-stage tuning circuit 14 of an electronic tuning system.

Further, an oscillation signal having a predetermined frequency is formed in the PLL 21, and this oscillation signal is supplied to the frequency dividing circuit 22, and the carrier frequency (center frequency) of the reception signal S12 is obtained.
For example, 500 kHz higher and the phases are 90
The signal is divided into two different signals, and the divided signal is supplied to the mixer circuits 15A and 15B as a local oscillation signal.

Thus, in the mixer circuits 15A and 15B, the received signal S12 is frequency-converted into two intermediate frequency signals S15A and S15B (intermediate frequency is 500 kHz) whose phases are different from each other by 90 °.

At this time, from the PLL 21, the V
A part of the control voltage supplied to the variable capacitance diode of CO (not shown) is extracted, and this control voltage is supplied to the tuning circuit 1.
2 and 14 are supplied as tuning voltages, and tuning to the received signal S12 is realized.

Then, the intermediate frequency signals S15A and S15B from the mixer circuits 15A and 15B are
A, 16B and variable gain amplifiers 17A, 17A for AGC
7B, the signals are supplied to the phase shift circuits 26A and 26B. In the phase shift circuits 26A and 26B, for example, the original signal components included in the intermediate frequency signals S15A and S15B are in the same phase, and the image components are in the opposite phase. Phase. The intermediate frequency signals S15A and S15B after the phase shift
Is supplied to the addition circuit 27, from which an image component is canceled and an intermediate frequency signal S15 having an original signal component is extracted.

Subsequently, the intermediate frequency signal S15 is supplied to the demodulation circuit 19 through the signal line of the band pass filter 28 for the intermediate frequency filter, the variable gain amplifier 17 for the AGC, and the low pass filter 18. , Audio signals L and R of a target program out of a plurality of programs are extracted.

At this time, the intermediate frequency signal S15 from the low-pass filter 18 is supplied to the AGC detection circuit 25 to form an AGC voltage V25. The AGC voltage V25 is supplied to the variable gain amplifier 17 as a gain control signal. You.

Further, low-pass filters 16A and 16B
The intermediate frequency signals S16A and S16B from the AGC detector 2
3 to form a delayed AGC voltage V23.
The GC voltage V23 is supplied to the addition circuit 24, and A
The GC voltage V25 is supplied to the adding circuit 24. Then, the addition circuit 24 outputs the addition voltage V24 of the AGC voltages V23 and V25.
The voltage V24 is supplied to the variable gain amplifier 13 as a gain control signal.

Therefore, AGC is performed on the received signal S12 from the tuning circuit 12 by the AGC voltage V24, and the bandpass filter 28 is controlled by the AGC voltage V25.
The AGC is performed on the intermediate frequency signal S15 from the AGC. At this time, the AGC voltage V24 becomes the delayed AGC voltage V
Since the voltage is an added voltage of the AGC voltage V25 and the AGC voltage V25, the AGC range for the reception signal S12 can be expanded.

[0099] Also in this receiver, the variable gain amplifier 13 can be configured as shown in FIG. 2, for example, and can be integrated into an IC.

In FIG. 2, the cascode amplifier 5
Nos. 1 to 54 prevent the leak signal in the differential amplifier from leaking to another differential amplifier. Therefore, the cascode amplifier may be provided for each of the number of stages where the leak signal in the differential amplifier cannot be ignored. become. For example, the attenuation per stage of the attenuator circuit is 6 to 8
In the case of dB, as shown in FIG. 2, it is effective to provide a cascode amplifier for every two stages of the differential amplifier.

[0101]

According to the present invention, it is possible to operate with a low power supply voltage. Further, since an appropriate level signal is selected and extracted from the output signals of the attenuator circuit, it is possible to suppress the occurrence of distortion.

[Brief description of the drawings]

FIG. 1 is a system diagram illustrating one embodiment of the present invention.

FIG. 2 is a connection diagram illustrating one embodiment of the present invention.

FIG. 3 is a connection diagram illustrating one embodiment of the present invention.

FIG. 4 is a characteristic diagram for explaining the present invention.

FIG. 5 is a system diagram illustrating one embodiment of the present invention.

FIG. 6 is a connection diagram for explaining the present invention.

FIG. 7 is a characteristic diagram for explaining the circuit of FIG. 6;

[Explanation of symbols]

11 antenna, 12 tuning circuit, 13 variable gain amplifier, 14 tuning circuit, 15A, 15B mixer circuit, 1
6A, 16B: low-pass filter, 17A, 17B: variable gain amplifier, 18A, 18B: low-pass filter, 1
9 demodulation circuit, 21 PLL, 22 frequency divider circuit, 23
AGC detection circuit, 24 addition circuit, 25 AGC detection circuit, 26A, 26B phase shift circuit, 27 addition circuit, 28
... Band pass filter, 31-33 ... Attenuator circuit, 40-43 ... Differential amplifier, 51-54 ... Cascode amplifier, 60 ... Constant current source

Claims (7)

[Claims] 1. A plurality of attenuator circuits cascaded to an input signal, a plurality of amplifiers to which respective output signals of the plurality of attenuator circuits are respectively supplied, and a common connection to output terminals of the plurality of amplifiers And a plurality of switch elements provided in series on a current line between the plurality of amplifiers and the operating current source. A variable gain amplifier having a plurality of switch elements selectively on / off controlled in accordance with a control signal to obtain a level-controlled output signal from the extraction circuit. 2. The variable gain amplifier according to claim 1, wherein the input signal is supplied to a first stage of the plurality of amplifiers, and each output signal of the plurality of attenuator circuits is supplied to a first stage of the plurality of amplifiers. A variable gain amplifier that is supplied to each of the second and subsequent stages. 3. The variable gain amplifier according to claim 1, wherein the switch element is controlled to an intermediate state between on and off in accordance with the control signal, so that the switch circuit is controlled from the take-out circuit. A variable gain amplifier that obtains an output signal whose level changes continuously. 4. The variable gain amplifier according to claim 1, wherein the operating current source is configured with a ground as a reference potential point, and each of the plurality of switch elements is connected to the plurality of switch elements. A current line between each ground side of the amplifier and the operating current source is constituted by a transistor having a collector and an emitter connected in series, and a variable voltage source is connected between the bases of these transistors. A variable gain amplifier that controls the output voltage of a voltage source according to the control signal to obtain a level-controlled output signal from the extraction circuit. 5. The variable gain amplifier according to claim 1, wherein each of the plurality of attenuator circuits includes a first resistor and a parallel circuit of a capacitor, A variable gain amplifier, wherein a parallel circuit of a second resistor and a capacitor is connected in series, and an output is taken out from the second parallel circuit in each of the attenuator circuits. 6. A variable gain amplifier is provided on a signal line of a received signal of a broadcast wave. The variable gain amplifier comprises: a plurality of cascade-connected attenuator circuits; A plurality of amplifiers respectively supplied; an extraction circuit commonly connected to the output terminals of the plurality of amplifiers; an operating current source common to the plurality of amplifiers; the plurality of amplifiers; and the operating current A plurality of switch elements provided in series with a current line between the plurality of switch elements, and the received signal is supplied to a first stage of the plurality of attenuator circuits, and an AGC voltage is supplied to the plurality of switch elements. A receiver that extracts an AGC-controlled reception signal from the extraction circuit by selectively performing on / off control according to the following. 7. The receiver according to claim 6, wherein the switch element is controlled to an intermediate state between ON and OFF in accordance with the AGC voltage, so that AGC control is continuously performed from the extraction circuit. A receiver designed to extract the received signal.