JP2001044279A - Three-dimensional multilayer semiconductor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a three-dimensional semiconductor circuit which is enhanced in circuit density, possessed of an interconnection part reduced in length to an irreducible minimum, enhanced in scale, and made complicated and a method of manufacturing the same. SOLUTION: In a method of manufacturing a three-dimensional semiconductor circuit, a conductive layer possessing a doped polysilicon layer at its upper part is formed, patterned, and annealed for the formation of the first single grain polysilicon terminal 16 of a semiconductor device. An insulated gate contact 30 is set separate from the terminal 16 in the vertically direction, a vertical via is specified, polysilicon is deposited in the via to form a conductive channel 35. The upper part of polysilicon filled in the via is doped for the formation of a second terminal 36 of the semiconductor device, the polysilicon is annealed into a single-grain polysilicon. A second conductive layer 39 is deposited on the second terminal 36 and then patterned, by which the second terminal contact of the semiconductor device is specified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor circuit, and more particularly to a three-dimensional semiconductor circuit.

[0002]

2. Description of the Related Art Semiconductor technology is rapidly evolving toward deep submicron geometries in search of minimizing die size and speeding up circuits. As the dimensions of the geometric shapes become smaller,
The main factor that hinders speed and density is interconnect capacitance, not transistor switching speed. In addition, current semiconductor technology is arranged in a two-dimensional array,
Based on high performance transistors. These transistors provide high mobility and low leakage current,
Manufactured in single crystal silicon (Si) material, resulting in high transistor threshold controllability, low operating voltage, high drive current, and high fan-out.
t), ie, bring gain. Critical lithographic dimensions (cri
As the lithographic dimension decreases,
The performance of a transistor arranged in a planar shape depends on the gate-
Tunneling between source and drain
Or punch-through between the source and drain (punch-t
hrough).

[0003] Existing polysilicon materials, usually formed and annealed in layers of amorphous silicon, have been developed to operate as switches or low performance drivers for active matrix LCD displays. These devices have the disadvantage of low mobility and high leakage current, and the performance obtained with these transistors is greatly impaired and much worse than the performance of single crystal transistors.

At present, CMOS circuits are formed in a planar shape,
The elements are interconnected by long metal lines (multilayer). The metal lines extend from one portion of the circuit to other portions on the insulating dielectric. Vias are used to access the device, and multi-layer metal is used to connect the device.
Enhance. With the increasing density and complexity of devices, circuits and long metal lines, interconnecting devices on the same plane has become extremely difficult. Long interconnect lengths and increased RC time constants are affecting circuit speed (and are a limiting factor in many large circuits). Clock skew
kew), signal delay, and parasiticleakage affect the performance of the circuit.

In a planar circuit layout, the number of input / output leads is limited. Also, depending on the tool field size of a tool such as a stepper,
Larger die size is hampered.

Accordingly, it would be highly desirable to provide a convenient method of fabricating an efficient three-dimensional semiconductor circuit.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a new and improved method of manufacturing a three-dimensional semiconductor circuit.

It is another object of the present invention to provide a new and improved method of fabricating three-dimensional semiconductor circuits that increases density and minimizes interconnect length.

It is another object of the present invention to provide a new and improved method of manufacturing a three-dimensional semiconductor circuit that can be conveniently and easily performed without additional cost or labor.

It is yet another object of the present invention to provide a new and improved method of manufacturing large and complex semiconductor circuits while reducing RC time constants, clock skew, signal delay, and parasitic leakage. An object of the present invention is to provide a method for manufacturing a three-dimensional semiconductor circuit.

It is yet another object of the present invention to have high mobility and low leakage current, resulting in high transistor performance.
It is an object of the present invention to provide a new and improved high-performance semiconductor device having threshold controllability, low-voltage operation, high drive current, and high fan-out or gain.

It is a further object of the present invention to provide a new and improved high performance three-dimensional semiconductor circuit which allows for further complications while reducing RC time constants, clock skew, signal delay, and parasitic leakage. It is to provide.

[0013]

SUMMARY OF THE INVENTION At least a partial solution to the above and other problems and the realization of the above and other objects are achieved by a method for manufacturing a three-dimensional semiconductor circuit. The method includes providing a layer of a first conductivity type having a doped polysilicon layer disposed thereon and patterning to form a sub-micron geometry including first terminals of a plurality of first semiconductor devices. Manufactures three-dimensional semiconductor circuits. Annealing the doped polysilicon and expanding the particles avoids grain boundaries within each conductive portion of the first terminal semiconductor contact. An insulated gate contact is formed vertically away from the first terminals of the plurality of first semiconductor elements and further defines a vertical via. Each conductive portion of the first terminal semiconductor contact is the underside of each one of the vias. Polysilicon is grown or deposited in the via on each conductive portion of the first terminal semiconductor contact to form a plurality of first semiconductor device conductive channels. The upper portion of the polysilicon in the via is doped to form second terminal semiconductor contacts of the plurality of first semiconductor devices. Before or after doping, the polysilicon conductive channel and the polysilicon second terminal semiconductor contact are annealed to expand the particles and avoid grain boundaries in the conductive portions of each of the conductive channel and the second terminal semiconductor contact. A second conductive layer is deposited and patterned on the second terminal semiconductor contact to define second terminals and interconnects of the plurality of first semiconductor devices.

By repeating the above steps and using the upper conductive layers of the plurality of semiconductor elements as the first conductive layers of the plurality of continuous semiconductor elements as a whole, the first conductive layers of the plurality of continuous semiconductor elements are respectively formed on the plurality of continuous semiconductor elements. A plurality of second, third, etc. semiconductor elements are produced. Also, in the preferred embodiment, various annealing steps are performed using a laser to reduce heat on other components in the circuit.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Turning now to the drawings, and referring specifically to FIG. 1, a simplified cross-sectional view of a first step in a three-dimensional semiconductor circuit manufacturing process according to the present invention is shown. silicon,
A substrate 10 is provided that can be formed of glass or any other suitable material 11. When the substrate 10 is a conductive material, an integrated circuit, or the like, or includes the same, the insulating layer 12 is formed on the substrate 10, which is also regarded as falling under the term "substrate". . The lower conductive layer 13 is formed on the surface of the substrate 10. The lower conductive layer 13 can include metal, silicide, heavily doped semiconductor material, or any other suitable conductive material. Layer 13 is formed by any convenient technique, such as, for example, deposition, such as evaporation, diffusion, or doping by implantation.

On the surface of layer 13, a polysilicon layer 14 is deposited. During or after deposition, the polysilicon layer 14 is doped to provide a source contact or drain contact.
A p-type or n-type conductivity is formed for a contact of an element such as a contact. An insulating layer 15 is deposited on top of the polysilicon layer 14 and the structure is patterned to form a sub-micron geometry including a plurality of lower terminals 16 of the first semiconductor device, as shown in FIG. I do. To perform the patterning, any of the conventional masking and etching techniques used in the semiconductor industry can be used. Also, submicron geometries typically include interconnects between semiconductor devices.

The portion of the polysilicon layer 14 included in each of the lower terminals 16 forms a semiconductor contact 17 for the lower terminal and expands the polysilicon particles by annealing, usually following a patterning step. In a preferred embodiment, the annealing is, for example, a rapid thermal anneal (R
Unlike a rapid temperature anneal (TA) process, by using a laser that can be annealed at a low temperature, the effect on other components of the structure is reduced. Thus, annealing the semiconductor contact at this point in the process at which laser annealing can be easily performed is the best treatment. Annealing the semiconductor contacts 17 causes the crystal grains to expand and substantially avoids grain boundaries within each conductive portion of the semiconductor contacts 17. However, factors such as the size of the semiconductor device being manufactured, the annealing temperature and time, etc., determine the size of the particles for the semiconductor device.

In practice, the first time this process is performed, annealing and inspection of a single semiconductor contact 17 or a completed semiconductor device will result in an optimum, which minimizes grain boundaries within the semiconductor device. Determine proper annealing conditions and semiconductor size. For example, annealing is performed on the semiconductor contact 17 at a common time and temperature to check the conductivity of the contact. As the number of grain boundaries in the semiconductor contact 17 decreases, the conductivity of the formed conductive portion increases. Optimum annealing can be obtained by changing the annealing time and temperature and testing the conductivity after each change. Also,
Within the limits of current patterning techniques, the size of the semiconductor contact 17 can be varied to further increase its suitability for the size of the expanded particles. In an optimal situation, each semiconductor contact 17 will be a single particle or crystal.

Turning now to FIG. 3, over the entire structure, a layer 20 of dielectric material is deposited and planarized by any convenient technique, such as, for example, chemical mechanical polishing. A gate contact layer 21 is deposited on the surface of the planarized layer 20, and an insulating layer 22 is deposited on the surface of the gate contact layer 21. In the preferred embodiment, the gate contact layer 21 is formed of polysilicon, but other known contact materials are available, and the inclusion of polysilicon here is due to its convenience in the process. Will be understood by those skilled in the art.

As shown in FIG. 4, the structure is patterned, and a via 25 penetrating through the insulating layer 22, the gate contact layer 21 and a part of the layer 20 and reaching the insulating layer 15 is formed. In this patterning, for example, the opening 2
6 separates the gate contact layer 21 into a plurality of individual gate contacts 30;
Provide interconnects, external connections, or connecting junctions (not shown) for 0.
The via 25 is usually formed so that its cross section is circular so that the gate contact 30 forms a wrap-around gate. next,
If the material of the gate contact 30 is polysilicon, it is oxidized and a gate insulating layer 31 is formed in each via 25.
To form The oxidized portion other than the inside of the via 25 does not affect the structure, and is not shown. When the oxidation step is completed, the insulating layer 15 on the upper surface of each semiconductor contact 17 is removed, and the semiconductor contact 17 is exposed on the bottom surface of each via 25.

Turning next to FIG. 5, polysilicon is deposited in via 25 to form conductive channel 35 and upper semiconductor contact 36. Additional dielectric material, generally similar to layer 20, again indicated at 20, is formed between the elements to planarize the entire structure. The polysilicon defining the conductive channel 35 is grown vertically. This allows precise control of the vertical thickness (the length of the conductive channel).

Doping the top of the polysilicon by any convenient technique, such as diffusion or implantation,
An upper semiconductor contact 36 is formed. Before or after doping, the polysilicon is annealed to expand the crystal grains and substantially reduce grain boundaries in the conductive portion of conductive channel 35 and upper semiconductor contact 36, as described generally with respect to semiconductor contact 17. To avoid. In some cases, it is possible to grow single crystal silicon in the via 25 using the semiconductor contact 17 as a seed material. As described above, it is preferable to use a laser to perform annealing,
The annealing and inspection procedures optimize this process for optimal results. In either case, the lateral size of the semiconductor device can be limited to a size much smaller than the size of the expanded polysilicon particles, and the presence of grain boundaries in the active region of the semiconductor device can be avoided. .

A metal layer is deposited on the top surface of the device and patterned using any of the conventional semiconductor techniques to form a second conductive contact 39 on each semiconductor contact 36 to form a plurality of semiconductor devices. Forty second terminals are defined. Further, patterning is performed on the metal layer to define interconnects and the like (not shown).

Turning now to FIG. 6, the semiconductor device 4 of the present invention
A simplified cross-sectional view of a complementary pair of 0, 41 is shown partially exploded. In this specific embodiment, the semiconductor device 40 is
This is the element shown in FIG. Also, in this specific example,
The second conductive contact 39 of the semiconductor element 40 is used as a lower conductive layer of the semiconductor element 41. The semiconductor element 41 is formed on the semiconductor element 40 by repeating the above steps. Also, the semiconductor element 40 is doped with a first conductivity type, N-P-N in this example, and the semiconductor element 41 is doped with an opposite conductivity type, P-N-P in this example, and interconnected complementary pairs. To form The embodiment shown in FIG. 6 shows one element directly above the other element of the same size, but the complementary elements (and elements included only in the same circuit) are placed adjacent to each other at the same or different levels It will be appreciated that other sizes are possible.

In a somewhat different embodiment, shown in FIG. 7, a suitable buffer layer or layers 50 may be added to the first circuit or structure 5.
1 (for example, the structure shown in FIG. 5), and the above-described steps are repeated to form a second layer of the semiconductor element 52. Additional layers are added by depositing a third buffer layer or layers 53 and creating a third layer of semiconductor device 54. In this embodiment, the buffer layer or layers are:
In addition to acting as an interlayer insulator for the device, it also acts as a shield from process conditions to which the upper layers of the device are exposed during the manufacturing process. The material chosen for the buffer layer or layers may not only act as a thermal and electrical shield, but may also be suitable for creating a high quality polysilicon material in some cases.

The components, ie the vertically stacked layers of the circuit, are interconnected by interconnect metal lines 55 and 56, respectively. The interconnect metal lines 55, 56 are much shorter than the long metal lines used in conventional two-dimensional arrays of devices. In general, the length of interconnect lines in the three-dimensional circuit of the present invention is reduced to a few microns, whereas conventional two-dimensional technologies require lengths on the order of hundreds of microns or millimeters. With the three-dimensional circuit described here, a very high density of circuit integration is obtained. As the proximity of the devices is even higher, the stringency of device drive and fan-out requirements is reduced,
As a result, power consumption is reduced. Also, the three-dimensional nature of this integration allows for contacting all surfaces of the three-dimensional die, increasing the number of I / O leads that can be installed. Further, this novel approach for stacking multiple layers of semiconductor devices begins by depositing a non-single crystal material on a suitable buffer layer and then processing it to obtain acceptable device performance. Overall improvement in complexity, performance is achieved.

As described above, a highly convenient method for manufacturing an efficient three-dimensional semiconductor circuit has been disclosed. By this method, an excellent three-dimensional semiconductor circuit having a high density and a minimum interconnect length can be obtained. Further, the new and improved method of manufacturing a three-dimensional semiconductor circuit can be conveniently and easily implemented without additional cost or effort, while reducing RC time constants, clock skew, signal delays, and parasitic leakage. ,
It is possible to manufacture a larger and more complicated semiconductor circuit. Also, the new method is a new method that provides high mobility and low leakage current, resulting in good transistor threshold control, low voltage operation, high drive current, and high fan out or gain. An improved high performance semiconductor device is provided.

While specific embodiments of the present invention have been shown and described, further modifications and improvements will occur to those skilled in the art. Therefore, it is intended that the invention not be limited to the particular forms shown, but the claims will cover all modifications that do not depart from the spirit and scope of the invention. It is.

[Brief description of the drawings]

FIG. 1 is a partially cut-away simplified cross-sectional view of a continuous process in a three-dimensional semiconductor circuit manufacturing process according to the present invention.

FIG. 2 is a partially cut-away simplified cross-sectional view of a continuous process in a three-dimensional semiconductor circuit manufacturing process according to the present invention.

FIG. 3 is a partially cut-away simplified cross-sectional view of a continuous process in a three-dimensional semiconductor circuit manufacturing process according to the present invention.

FIG. 4 is a partially cut-away simplified cross-sectional view of a continuous process in a three-dimensional semiconductor circuit manufacturing process according to the present invention.

FIG. 5 is a partially cut-away simplified cross-sectional view of a final step in a three-dimensional semiconductor circuit manufacturing process.

FIG. 6 is a partially cut-away simplified cross-sectional view of a complementary pair of a semiconductor device according to the present invention.

FIG. 7 is a simplified sectional view of a plurality of laminated semiconductor circuits according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate 12 Insulating layer 13 Lower conductive layer 14 Polysilicon layer 15 Insulating layer 16 Lower terminal 17 Semiconductor contact 20 Dielectric material layer 21 Gate contact layer 22 Insulating layer 25 Via 26 Opening 30 Gate contact 31 Gate insulating layer 35 Conductive channel 36 Upper semiconductor contact 39 Second conductive contact 40, 41 Semiconductor device 50 Buffer layer 51 First circuit 52 Semiconductor device 53 Third buffer layer 54 Semiconductor device 55, 56 Interconnect metal line

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kamer Shiraraghi, North Florence Drive 961, Chandler, Arizona, USA ) 5F033 GG03 HH04 JJ01 JJ04 KK04 LL04 LL08 MM05 NN31 NN40 QQ08 QQ09 QQ37 QQ48 QQ59 QQ65 QQ73 QQ80 QQ83 QQ89 TT08 VV03 VV06 XX03

Claims (4)

[Claims] 1. A method for manufacturing a three-dimensional multilayer semiconductor circuit, comprising the step of providing a first conductive layer (13) having a doped polysilicon layer (14), wherein the doped polysilicon layer is the first conductive layer. Wherein said doped polysilicon comprises particles, wherein said doped polysilicon comprises particles, wherein said doped polysilicon comprises particles, wherein said doped polysilicon comprises a first terminal of said plurality of first semiconductor devices and is located on said conductive transport layer. Annealing a layer and expanding the particles to avoid grain boundaries in each conductive portion of the semiconductor contacts of the first terminal; the first terminals (1) of the plurality of first semiconductor elements;
Forming an insulated gate contact (30) vertically spaced from 6), defining a vertical via (25), and connecting each conductive portion of the first terminal semiconductor contact to the underside of one of the vias; Depositing polysilicon including particles in the via on each conductive portion of the first terminal semiconductor contact to form conductive channels for the plurality of first semiconductor elements; The upper portion of the polysilicon in the via is doped to form the plurality of first portions.
Forming a second terminal semiconductor contact (36) on the semiconductor device; annealing the polysilicon conductive channel and the polysilicon second terminal semiconductor contact to expand the particles to expand the conductive channel and the second conductive semiconductor channel;
Avoiding grain boundaries within each conductive portion of the terminal semiconductor contact; and depositing and patterning a second conductive layer (39) on the second terminal semiconductor contact (36) to form the plurality of first semiconductor devices. Of the second terminal (4
Defining 0). 2. By repeating the steps of claim 1,
Forming a plurality of second semiconductor elements (41) on the plurality of first semiconductor elements, and forming the plurality of first semiconductor elements (40);
The method for manufacturing a three-dimensional semiconductor circuit according to claim 1, wherein the second conductive layer (39) is used as the first conductive layer of the plurality of second semiconductor elements. 3. A three-dimensional semiconductor circuit comprising: a first conductive interconnect layer (13), on which a layer (14) of large doped particle polysilicon is arranged and, by patterning, a plurality of first conductive interconnect layers (13). Forming a submicron geometry including a first terminal (16) having a first semiconductor contact of one semiconductor device and substantially avoiding grain boundaries within each conductive portion of the first semiconductor contact; A first conductive interconnect layer (1) on which each first semiconductor contact is located.
3); an insulated gate contact (30) defining a vertical via (25) vertically spaced from the first semiconductor contact of the plurality of first semiconductor elements, wherein each of the first semiconductor contacts is electrically conductive; An insulated gate contact (30), a portion of which forms a lower surface of the via; disposed within the via on the conductive portion of the first semiconductor contact to define a conductive channel of the plurality of first semiconductor elements. A large grain polysilicon avoiding grain boundaries in the conductive channel (35), wherein an upper portion of the large grain polysilicon is doped in each of the vias, and a second semiconductor of the plurality of first semiconductor elements is doped. A large grain polysilicon forming a contact (36); and a plurality of patterned polysilicon disposed on the second semiconductor contact and patterned. The second terminal of the first semiconductor element (37)
And a metallization layer defining interconnects. 4. A plurality of second semiconductor elements (41) are arranged on said plurality of first semiconductor elements, and said second conductive layer (39) of said plurality of first semiconductor elements (40) is arranged on said plurality of first semiconductor elements (40). 4. The three-dimensional semiconductor circuit according to claim 3, comprising the first conductive layer of a plurality of second semiconductor elements.