JP2001042288A - Display device and its driving method, and its inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device capable of protecting pixel transistors, etc., from static destruction in a manufacturing process of a display panel. SOLUTION: Each side of a plurality of columns of switches 36-1 to 36-n is connected to a side opposite to the side to which the signal potential of a plurality of signal lines 12-1 to 12-n is fed, respectively, and each end is connected with a common line 18 to switch these switches 36-1-36-n to off-state for a display driving period and to on-state for the period except the display driving period, and thereby each signal line 12-1-12-n is set to the same potential as the common line 18 for the period except the display driving period to forcibly bring the display screen into white-display to prevent picture disturbance from appearing on the display screen.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, a method for driving the display device, and a method for inspecting the display device, and more particularly to an active matrix type display device represented by a liquid crystal display or an EL (electroluminescence) display, and a driving method therefor. And a method for inspecting the display device.

[0002]

2. Description of the Related Art In an active matrix type display device, for example, an active matrix type liquid crystal display,
Each pixel of the liquid crystal display panel uses a non-linear element such as a transistor or a diode. Specifically, it has a structure in which, for example, a thin film transistor (TFT) is formed as a pixel transistor on a transparent insulating substrate such as a glass substrate.

[0003] Particularly, in a large liquid crystal display,
A driver IC, which is a horizontal drive circuit for sequentially applying a signal potential to each pixel in a column unit, is provided on an external circuit board separate from the liquid crystal display panel, and for example, TAB (T
ape Automated Bonding). At this time, there is usually a one-to-one correspondence between the output of the external driver IC and each signal line in the liquid crystal display panel. That is, the signal potential from each output terminal of the driver IC is directly supplied to each corresponding signal line.

[0004] On the other hand, a so-called time-division driving method is known as a driving method capable of reducing the number of output pins (output terminals) of the driver IC for the purpose of reducing the size of the driver IC. In this time-division driving method, a plurality of signal lines are defined as one unit (block), and signal potentials applied to a plurality of signal lines in the one divided block are output from a driver IC in a time-series manner, while the signal potential is applied to a liquid crystal display panel. Is a driving method in which time-division switches are provided using a plurality of signal lines as one unit, and the time-division switches time-divisionally apply signal potentials output from the driver IC in time series to the plurality of signal lines. .

In the driver IC, as shown in FIG. 8, by grounding each output line 101 via a pull-down resistor 102, the driver IC is stopped at the moment when the driving of the liquid crystal display panel is stopped (display is completed). Is set such that the signal potential output from the device to the panel is set to the GND level. At this time, if the time constant of the output potential from the driver IC does not match the time constant of the common potential (hereinafter, referred to as VCOM potential) in the panel, as shown in FIG. The potential is applied,
This causes image disturbance.

Here, the time constant of the output potential from the driver IC depends on the circuit design in the IC,
The time constant of the OM potential depends on the circuit design of the generating circuit that generates the VCOM potential, and is determined for each circuit design. Therefore, it is difficult to match these time constants. Therefore, in a transmissive liquid crystal display configured to use a backlight, the timing of turning off the backlight is advanced earlier than the timing of stopping the display drive so that the image disturbance due to the mismatch of the time constant is not displayed. It is the present situation.

[0007]

However, in a reflective liquid crystal display which does not use a backlight, the timing control sequence between turning off the backlight and stopping the display driving is not established, so that the display driving is not performed. Unless measures are taken in the system, it is difficult to eliminate image disturbance at the end of display (when driving is stopped).

During a period in which the liquid crystal display panel is not driven for display, that is, a period in which the power is turned off and the liquid crystal display is not used, the pixel potential of the display region (pixel region) of the panel and the VCOM potential are not changed. The potential difference between them must be zero. If a direct current is applied during that period, the ITO / PI (polyimide) interface and the like are charged up, and the optimum VCOM value fluctuates even in the same panel. This is the optimum V for every drive (display).
This means that the COM is deviated, and accordingly, image quality defects such as burn-in, a decrease in contrast, and flicker in the liquid crystal display panel occur.

On the other hand, as shown in FIG. 10, a horizontal drive circuit 111 is mounted on a liquid crystal display
In the case of a dot-sequential drive type liquid crystal display for sequentially applying signal potentials to 3-1, 113-2, 113-3,..., A video line 114 for inputting a video signal from outside the panel and each signal line 113 in the panel -1, 113-2, 113-3,... Are transfer gates (analog switches) 115-1,
Are connected via 115-2, 115-3,.... Therefore, during the power-off period, the signal lines 113-1 and 13-1 are not used.
The potentials of 13-2, 113-3,... Are the same via transfer gates 115-1, 115-2, 115-3,.

At this time, the signal lines 113-1 and 113
-2, 113-3, ... and the pixel electrode of the liquid crystal cell (liquid crystal capacitor) LC are also connected via the pixel transistor TFT. It is a potential state. Also, as shown in FIG.
If the common line 116 and the video line 114 are connected to each other via a resistor of about 1 MΩ, for example, VCOM
The potential and the pixel potential are the same, and no DC is applied to the liquid crystal and PI.

However, as in the liquid crystal display using the time-division driving method described above, a horizontal driving circuit (driver I
In the case of a panel structure in which C) is arranged on an external circuit board,
In the process of manufacturing a liquid crystal display panel, in a process until an external IC is connected, each signal line has an indefinite potential because each signal line is in an open state. Therefore, in the panel selection, the optimum VCOM shifts, image quality defects such as burn-in, contrast reduction, and flicker occur, and stable selection and inspection cannot be performed.

Further, if a high potential is applied to a pixel due to charging or the like during a manufacturing process of a liquid crystal display panel, there is a possibility that electrostatic breakdown of a pixel transistor or the like is caused due to the high potential. Conventionally, as one of the measures against these problems,
As shown in FIG. 12A, the signal lines 113-1, 113-2, 113-3,.
Are short-circuited by short lines 118 to prevent electrostatic destruction. On the other hand, as shown in FIG. 12B, a method of cutting the short lines 118 with a laser or the like before overlapping the TFT substrate and the counter substrate is used. Had been taken.

However, using the above-described method,
A new problem arises in that an extra step of cutting the short-circuited wiring (short line 118) is required, and no countermeasures can be taken against electrostatic destruction in steps subsequent to the cutting step.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device capable of preventing electrostatic breakdown of pixel transistors and the like in a display panel manufacturing process.

The present invention further provides a high-quality display device free from image disturbance, image sticking, reduced contrast, and flicker, a method of driving the same, and a method of inspecting a display device that facilitates selection of display panels. Aim.

[0016]

According to the display device of the present invention, pixels are arranged at intersections between a plurality of rows of gate lines and a plurality of columns of signal lines arranged in a matrix on a transparent insulating substrate. A plurality of switches, one end of each of which is connected to the end opposite to the side to which the signal potentials of the signal lines for the plurality of columns are supplied, are provided for the pixel portion, and the other ends of these switches are short-circuited. It is configured to be connected to the line in common.

In the display device having the above structure, in a manufacturing process of a display panel in which each pixel is arranged, switches for a plurality of columns are turned on. As a result, signal lines for a plurality of columns are short-circuited to each other through these switches. Therefore, even if a high potential is applied to a part of the signal line due to charging or the like, the high potential charge is discharged to another signal line. As a result, the pixel transistors and the like in the column of the signal line to which the high potential is applied are not damaged by static electricity.

Further, in the display device having the above structure, a common line for giving a predetermined DC potential to each pixel of the pixel portion in common is used as a short line, and switches for a plurality of columns are turned off during a display driving period. By being turned on during periods other than the driving period, the potential of each signal line is set to the same potential as the potential of the common line during periods other than the display driving period. As a result, no voltage is applied to the display element of the pixel, for example, the liquid crystal cell, and thus white display is performed. That is, white display is forcibly performed during periods other than the display drive period, so that image disturbance does not appear on the display screen. Moreover, during the leaving period, ITO / IP
The interface and the like do not charge up.

Further, in the display device inspection method according to the present invention, the display panel of the display device having the above-described structure is
By turning on the switches for a plurality of columns, and applying a predetermined voltage to one end of each of the signal lines for the plurality of columns in the on state of the switches, observing the current flowing through the short line, The presence or absence of a defect such as a disconnection in each of the signal lines is electrically measured.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram illustrating a configuration example of an active matrix liquid crystal display according to an embodiment of the present invention. Note that the liquid crystal display according to the present embodiment is a reflective liquid crystal display that does not use a backlight.

In FIG. 1, on a transparent insulating substrate, for example, a glass substrate (not shown), m rows of gate lines 11-1 to 11-1 are provided.
11-m and n columns of signal lines 12-1 to 12-n are arranged in a matrix. Also, the gate lines 11-1 to 11-m
At the intersection of the signal lines 12-1 to 12-n, unit pixels 13 for m rows and n columns are formed. The glass substrate in which the unit pixels 13 for m rows and n columns are arranged in a matrix forms a liquid crystal display panel (display unit) 14.

As is apparent from FIG. 2, the unit pixel 13 is a thin film transistor (TF) which is a pixel transistor.
T) 15, a storage capacitor 16, and a liquid crystal cell 17. The thin film transistor 15 has its gate electrode connected to the gate lines 11-1, 11-2, 11-3,..., And its source electrode connected to the signal lines 12-1, 12-2, 12-3,. ing.

One electrode of the storage capacitor 16 and the pixel electrode of the liquid crystal cell 17 are connected to the drain electrode of the thin film transistor 15. The other electrode of the storage capacitor 16 and the opposite electrode of the liquid crystal cell 17 are commonly connected to a common (VCOM) line 18 between the pixels. A predetermined DC potential is externally applied to the common line 18 as a VCOM potential (common potential). Here, the configuration is such that the VCOM potential is applied to the pixel portion only from one side (the right side in the drawing), but a configuration in which the VCOM potential is applied from both sides is also possible.

On the liquid crystal display panel 14, a vertical drive circuit 19 is arranged, for example, on the left side of the pixel section in the figure. One end of each of the gate lines 11-1 to 11-m is connected to the output end of each row of the vertical drive circuit 19. And
The vertical drive circuit 19 performs vertical scanning by sequentially applying scanning pulses to the gate lines 11-1 to 11-m and selecting each pixel 13 in a row unit.

On the other hand, assuming that a digital signal is input, it is necessary to convert the signal into an analog signal in order to drive the liquid crystal. Therefore, a horizontal drive circuit 20 for applying a signal potential according to image data to the signal lines 12-1 to 12-n is formed on a circuit board separate from the liquid crystal display panel 14, as described later.

In order to realize time-division driving, the number of signal lines 12-1 to 12-n for n columns is set to the number corresponding to the number of time divisions (in this example, three corresponding to three time divisions). When divided as one unit (block), the horizontal drive circuit 20
As is clear from FIG. 1, k driver ICs corresponding to the divided number k, for example, TABIC (1) 21-1
To TABIC (k) 21-k. These TABIC (1) 21-1 to TABIC (k) 21-k are 1
Signal potentials applied to a plurality of signal lines in the divided block are output in time series.

In response, k time-division switches 3
0-1 to 30-k are provided at the input stage of the signal lines 12-1 to 12-k for n columns. The time-division switch 30-1 includes, for example, three analog switches (transfer gates) 31, 32, and 33 using CMOS transistors, for example, as is apparent from FIG. The thin film transistor is formed over the same substrate as the display panel 14. Other time division switch 30-2
.About.30-k have exactly the same configuration as the time-division switch 30-1.

Then, in the time division switch 30-1,
The input terminals of the three analogs 31, 32, and 33 are connected in common, and the common connection point is connected to the T via a common signal line 34-1.
It is connected to the output terminal of the ABIC (1) 21-1. As a result, signal potentials output in time series from the TABIC (1) 21-1 are supplied to the respective input terminals of the three analog switches 31, 32, and 33 via the common signal line 34-1. The output terminals of these analog switches 31, 32, 33 are
It is connected to one end of each of the three signal lines 12-1, 12-2, and 12-3.

For the time division switch 30-2,
A time-series signal potential is supplied from the TABIC (2) 21-2 via the common signal line 34-2. Similarly, the time-division switch 30-k is supplied with a time-series signal potential from the TABIC (k) 21-k via the common signal line 34-k. Here, for the sake of simplicity, a configuration in which one common signal line is arranged for one TABIC is shown, but a plurality of common signal lines are actually arranged.

On the liquid crystal display panel 14, 1
A total of six control lines 35, two for each analog switch
-1 to 35-6 are wired along the wiring direction of the gate lines 11-1 to 11-m. As an example, in the time division switch 30-1, two input terminals (each gate of a CMOS transistor) of the analog switch 31 are connected to the control line 3.
5-1 and 35-2, two control input terminals of the analog switch 32 are connected to control lines 35-3 and 35-4, and the analog switch 33 is connected.
Are connected to the control lines 35-5 and 35-6, respectively.

Here, the six control lines 35 of the three analog switches 31 to 33 of the time division switch 30-1 are used.
The connection relations between -1 to 35-6 have been described, but the other time division switches 30-2 to 30-k have the same connection relation. The six control lines 35-1 to 35-6 include:
Control signals S1 to S3 for selecting each of the three analog switches 31 to 33 of the time division switches 30-1 to 30-k.
XS1 to XS3 are externally provided. However, the control signals XS1 to XS3 are inverted signals of the control signals S1 to S3.

On the liquid crystal display panel 14, the signal line 1
Short-circuit (short-circuit) switches 36-1 to 36-36 made of, for example, PchMOS transistors are connected to the other ends of 2-1 to 12-n, respectively.
Each end (ie, drain) of -n is connected. The other ends (that is, the sources) of the short switches 36-1 to 36-n are commonly connected to, for example, the common line 18. That is, the other ends of the short switches 36-1 to 36-n are connected to each other via the common line 18. Further, a control voltage Vc is applied to the control input terminals (ie, gates) of the short switches 36-1 to 36-n from a reset circuit 37 which is a switch control unit.

As shown in FIG. 3, for example, the reset circuit 37 includes a resistor 3 having one end to which the power supply voltage Vdd is applied.
71, and a capacitor 372 connected between the other end of the resistor 371 and the ground.
A control voltage Vc is applied to each control input terminal 6-n. FIG. 4 shows waveforms of the control voltage Vc when the power is turned on and when the power is turned off.

In this reset circuit 37, a resistor 37
1 and the capacitance Co of the capacitor 372
Is determined as a time constant to be set for the control voltage Vc.
Here, the capacitance value viewed from the gate per one of the short switches 36-1 to 36-n is Csw, and the liquid crystal display panel 14
Let n be the number of signal lines 12-1 to 12-n. In this case, the time constant T of the control voltage Vc is as follows: T = (Co + n * Csw) * Ro

The time constant T of the control voltage Vc is set to, for example, 16.7 msec for one field period of the liquid crystal display panel 14.
For example, if it is desired to make a transition in about 1 msec, n * Csw = 200 [pF] and Co = 0.1 [μ
F] and Ro = 10 [kΩ].

The operation of the short switches 36-1 to 36-n provided between the other ends of the signal lines 12-1 to 12-n and the common line 18 on the liquid crystal display panel 14 will be described. .

First, when the power is turned on (ON), the output voltage of the reset circuit 37 rises with a predetermined time constant. This time constant is set to be larger than the rising time constant on the horizontal drive circuit 20 side, that is, the rising is delayed. At the start of the rise, the output voltage of the reset circuit 37, that is, the control voltage Vc is changed to the short switch 36-1.
Since it is lower than the threshold voltage of
Short switches 36-1 to 36-n composed of transistors
Is turned on.

Then, the other ends of the signal lines 12-1 to 12-n are connected to the common line 18 through the short switches 36-1 to 36-n.
Shorted to That is, when the power is turned on, each potential of the signal lines 12-1 to 12-n instantaneously becomes the same potential as the VCOM potential. When the potentials of the signal lines 12-1 to 12-n and the VCOM potential are the same, it means that no voltage is applied to the liquid crystal cell 17, so that white display is performed. When the control voltage Vc reaches the threshold voltage, the short switch 3
6-1 to 36-n are turned off, and the display shifts to the display period.

In an active matrix type liquid crystal display of a time division drive system, a time division switch 3 is connected between the horizontal drive circuit 20 and the signal lines 12-1 to 12-n.
Since 0-1 to 30-k are interposed, it is not known what the potentials of the signal lines 12-1 to 12-n are in when the power is turned on. Black display or the like is partially performed, and this appears on the display screen as image disturbance at power-on.

However, in the liquid crystal display according to the present embodiment, as described above, when the power is turned on, the signal line 12 is turned off.
The other ends of -1 to 12-n are short switches 36-1 to 36-n
Short-circuit to the common line 18 so that the potentials of the signal lines 12-1 to 12-n are set to the same potential as the VCOM potential so that the screen display is forcibly displayed in white. Disturbance can be eliminated.

In the display period in the power-on state, the reset circuit 37 outputs a control voltage Vc at the level of the power supply voltage Vdd.
-n is applied to each gate. These short switches 3
Since 6-1 to 36-n are composed of Pch MOS transistors, they are off in the display period. At this time, the other ends of the signal lines 12-1 to 12-n are open. Therefore, as usual, each pixel 13 is driven in accordance with the signal potential applied to one end of each of the signal lines 12-1 to 12-n through the time division switches 30-1 to 30-k.

When the power is cut off (off), the reset circuit 3
The output voltage 7 falls from the power supply voltage Vdd with a predetermined time constant. At the start of the fall, the reset circuit 37
Since the output voltage of the short switches 36-1 to 36-n is higher than the threshold voltage of the short switches 36-1 to 36-n,
-n is off. When the output voltage of the reset circuit 37 drops to the threshold voltage of the short switches 36-1 to 36-n, the short switches 36-1 to 36-n are turned on.

Here, the short switches 36-1 to 36-n
Consider the case where does not exist. In this case, assuming that, for example, a black level has been written to a certain signal line immediately before power-off, the horizontal drive circuit 20 and the signal lines 12-1 to 12-1
2-n, the time-division switches 30-1 to 30-k are interposed.
When 0-k is turned off, the black level is held on the signal line, and this is displayed as a single line on the display screen, resulting in image disturbance.

However, as described above, by turning on the short switches 36-1 to 36-n immediately after the power is turned off, the signal lines 12-1 to 12-n are turned on in the same manner as when power is turned on.
12-n is short-circuited to the common line 18 through the short switches 36-1 to 36-n.
Since each of the potentials 2-1 to 12-n becomes the same potential as the VCOM potential, the screen display becomes a white display, and image disturbance at the time of power-off can be eliminated.

As described above, the short switches 36-1 to 36-3
When 6-n is composed of only PchMOS transistors,
As the potential difference between the source and the drain decreases, the potential between the gate and the source also decreases, and the drain-source current I
ds decreases. Therefore, the reset circuit 37 shown in FIG.
In the charge / discharge circuit configuration shown in (1), the potential of the common line 18 and the potentials of all the signal lines 12-1 to 12-n do not become the same within several msec.

However, in terms of image quality, a decrease in the potential between the source and the drain reduces the difference between the potential of the common line 18 and the potentials of all the signal lines 12-1 to 12-n (same for pixel potentials). This means that a normally black liquid crystal display becomes white. When the potential difference between the source and the drain is reduced to about 1 V, generally, as shown in FIG.
−T curve), and within the region where the reflectance difference in the liquid crystal applied voltage-reflectance relationship (VR curve) is small.

As is apparent from the above description, in the active matrix type liquid crystal display of the time division driving system, the other ends of the signal lines 12-1 to 12-n and the short lines 3
7, short switches 36-1 to 36-n are provided, and these short switches 36-1 to 36-n are turned on except during the display period, and the signal lines 12-1 to 12-n are connected to the common line 18.
And forcibly display white, even in a reflective liquid crystal display, such as a timing control between turning off the backlight and stopping display driving, as in a transmissive liquid crystal display. Even if the complicated control is not performed, the phenomenon of the image disturbance at the time of turning on the power and at the time of turning off the power can be eliminated.

The short switches 36-1 to 36-n remain on even during the idle period after the power is cut off, and the respective signal lines 12-1
~ 12-n is shorted to the common line 18,
The pixel potential is maintained at the same potential as the potential of the common line 18 and also prevents the charge-up of the ITO / PI interface and the like when the drive is turned off (left). By preventing the charge-up, the shift of the optimum VCOM can be prevented.
In addition, it is possible to prevent a problem in image quality such as flicker.

The operation of the short switches 36-1 to 36-n in the liquid crystal display after commercialization has been described above.
Also has a function of preventing electrostatic breakdown of the thin film transistor 15 and the like in the manufacturing process of the liquid crystal display panel 14. However, as shown in FIG.
It is necessary that a resistor 38 of about 1 MΩ be connected between each of the 6-n gates and the common line 18. This resistance 3
8 has no effect on the reset operation at the time of turning on the power and at the time of turning off the power.

Since the resistor 38 is connected between each gate of the short switches 36-1 to 36-n and the common line 18, each gate potential is the same as the potential of the common line 18; The switches 36-1 to 36-n are turned on, and the signal lines 12-1 to 12-n are short-circuited through the common line 18. Here, when a high potential is applied to part of the signal lines 12-1 to 12-n due to charging or the like during the manufacturing process of the liquid crystal display panel 14, each of the signal lines 12-1 to 12-n is short-circuited. Since the high potential charge is discharged to other signal lines, the thin film transistor 15 and the like can be prevented from being damaged by static electricity.

In the manufacturing process of the liquid crystal display panel 14, external ICs (TABIC (1) 21-1 to TABIC
(k) Even before 21-k) is connected, each signal line 12
Since -1 to 12-n are short-circuited through the common line 18, the potential of each pixel is determined. Therefore, the optimum VCOM does not shift in the panel selection, so that stable selection and inspection can be performed while preventing burn-in, contrast reduction, flicker, and the like.

When only prevention of electrostatic breakdown in the manufacturing process of the liquid crystal display panel 14 is considered, it is not always necessary to use the common line 18 as a short line for shorting each source of the short switches 36-1 to 36-n. Instead, as shown in FIG. 6, a dedicated short line 39 different from the common line 18 can be used. At this time, the reset circuit 37 in FIG. 1 may be omitted. However, when the reset circuit 37 is omitted, the liquid crystal display panel 14
Since the short switches 36-1 to 36-n must be turned off after the manufacture of the
It is necessary to apply an "H" level to each of the gates -1 to 36-n.

Further, in the above embodiment, the case where the short switches 36-1 to 36-n are constituted by only PchMOS transistors has been described as an example. However, a CMOS transistor in which an NchMOS transistor is connected in parallel to a PchMOS transistor is used. A configuration in which a transfer gate is used is also possible. In the case of the configuration using this transfer gate, one Nch per switch is used as compared with the configuration using only PchMOS transistors.
Although the circuit configuration becomes complicated due to the increase in the number of MOS transistors, there is an advantage that the common line 18 and all the signal lines 12-1 to 12-n can be instantaneously brought to the same potential.

However, the short switches 36-1 to 36-n
Is a transfer gate composed of a CMOS transistor, it is necessary to configure a system for applying an “H” level potential to the gate of the NchMOS transistor, for example, for about several milliseconds after the timing of transition from power on to power off. There is. As an example, the control voltage Vc output from the reset circuit 37 is inverted so that Nch
What is necessary is just to make it the structure applied to the gate of a MOS transistor.

In the above embodiment, the case where the present invention is applied to a time-division driving type liquid crystal display has been described as an example. However, a dot sequential driving type in which a signal potential is sequentially applied to each signal line on a panel is described. It is equally applicable to liquid crystal displays. Further, the present invention is not limited to a liquid crystal display, and is similarly applicable to an EL display using an EL element as a display element of a pixel.

Further, in the liquid crystal display according to the above embodiment, the vertical drive circuit 19 is connected to the liquid crystal display panel 14.
The vertical drive circuit 19 is also arranged on the same substrate as the horizontal drive circuit 20.
Needless to say, the configuration may be arranged on another external circuit board. In this case, the reset circuit 37 is also arranged outside the liquid crystal display panel 14.

Next, a description will be given of an inspection method according to the present invention when inspecting the liquid crystal display according to the above embodiment or its modification. In this inspection, an inspection is performed to determine whether or not each of the signal lines 12-1 to 12-n in FIG. 1 has a defect such as a disconnection (line defect).

First, as shown in the conceptual diagram of FIG. 7, "L" level is given to each gate of the short switches 36-1 to 36-n to turn on the short switches 36-1 to 36-n. On the other hand, it is assumed that a measuring instrument, for example, an ammeter 41 is connected between one end of the common wire 18 which is a short wire and the ground. The probe 43 to which a predetermined measurement voltage is applied from the DC voltage source 42 is connected to the signal lines 12-1 to 12-n.
The above measurement voltages are sequentially applied to these signal lines 12-1 to 12-n by sequentially making contact with the respective ends.

At this time, when there is no defect such as disconnection in the signal lines 12-1 to 12-n, these signal lines 12-1 to 12-n
A current determined by the resistance component of 12-n and the applied measurement voltage flows to the ammeter 41 through the signal lines 12-1 to 12-n and the common line 18. On the other hand, if a certain signal line is disconnected, for example, even if a measurement voltage is applied to the end of the signal line through the probe 43, no current path is formed, and no current flows through the ammeter 41 at all.

As described above, in the liquid crystal display according to the above embodiment or its modification, the signal lines 12-1 to 12-1
12-n and common line 18 (or short line 3
9) are connected to the short switches 36-1 to 36-n.
Is turned on, a measurement voltage is sequentially applied to each end of the signal lines 12-1 to 12-n through the probe 43, and it is only necessary to observe whether the needle of the ammeter 41 swings at that time. It is possible to easily inspect whether a defect such as a disconnection exists in the signal lines 12-1 to 12-n.

The present invention can be applied not only to the inspection of the line defect of the liquid crystal display but also to the inspection of the aforementioned line defect of the EL display.

[0062]

As described above, according to the present invention,
In a display device in which pixels are arranged at intersections of a plurality of rows of gate lines and a plurality of columns of signal lines arranged in a matrix on a transparent insulating substrate, signal potentials of a plurality of columns of signal lines are supplied. One end of each of a plurality of rows of switches is connected to the end opposite to the side to be connected, and each other end is commonly connected to a short line, and in the display panel manufacturing process, the plurality of rows of switches are turned on. In this state, signal lines for a plurality of columns are short-circuited to each other through these switches, so that electrostatic breakdown of pixel transistors and the like can be prevented.

In the display device having the above structure, a common line is used as a short line, and switches for a plurality of columns are turned off during a display driving period, turned on during periods other than the display driving period, and turned on during periods other than the display driving period. By setting the potential of the signal line to the same potential as the potential of the common line, when the display element is, for example, a liquid crystal cell, the entire display screen is forcibly displayed in white, so that image disturbance does not appear on the display screen. In addition, since the ITO / IP interface and the like do not charge up during the idle period, burn-in, decrease in contrast, flicker, and the like can be prevented.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a configuration example of an active matrix liquid crystal display according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration around a pixel portion and a time division switch.

FIG. 3 is a circuit diagram illustrating an example of a configuration of a reset circuit.

FIG. 4 is a waveform diagram of the control voltage Vc when the power is turned on and when the power is turned off.

FIG. 5 is a characteristic diagram of liquid crystal applied voltage-transmittance.

FIG. 6 is a schematic configuration diagram showing a configuration example of an active matrix liquid crystal display according to a modification of the present invention.

FIG. 7 is a conceptual diagram showing the procedure of the inspection method of the present invention.

FIG. 8 is a circuit diagram illustrating an example of a configuration of an output unit of the driver IC.

FIG. 9 is a waveform diagram showing a change in potential of a signal line when power is cut off.

FIG. 10 is a schematic configuration diagram of an example of a dot-sequential drive type liquid crystal display.

FIG. 11 is a circuit diagram showing a method for making the VCOM potential and the pixel potential the same.

FIG. 12 is a diagram for explaining a conventional technique for preventing electrostatic breakdown.

[Explanation of symbols]

11-1 to 11-m ... gate lines, 12-1 to 12-n ... signal lines,
13 unit pixel, 14 liquid crystal display panel, 15 thin film transistor (pixel transistor), 17 liquid crystal cell, 1
8 common line, 19 vertical drive circuit, 20 horizontal drive circuit, 30-1 to 30-k time division switch, 31 to 33 analog switch, 36-1 to 36-n short switch,
37: reset circuit, 39: short line

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NA43 NC12 NC21 ND10 ND12 ND35 5C006 AA11 AC24 AF43 AF53 AF61 AF78 BB15 BB28 BC23 BF24 EB01 FA33 5C080 AA06 AA10 BB06 DD15 DD19 DD30 EE29 FF11 GG02 GG03 JJ02 JJ

Claims (13)

[Claims] A pixel portion having pixels arranged at intersections of a plurality of rows of gate lines and a plurality of columns of signal lines arranged in a matrix on a transparent insulating substrate; A plurality of switches provided with one end connected to an end of the plurality of signal lines opposite to a side to which the signal potential is supplied, and the other ends of the plurality of switches are shared. And a short line connected to the display device. 2. The display device according to claim 1, wherein the short line is a common line that commonly supplies a predetermined DC potential to each pixel of the pixel portion. 3. The display device according to claim 2, further comprising switch control means for controlling the switches in the plurality of columns to be in an off state during a display drive period and to be in an on state during periods other than the display drive period. 4. An end portion of the signal lines for the plurality of columns to which signal potentials are supplied is provided with a predetermined number as one unit, and each of the one unit signal lines is signal-divided in a time-division manner. The display device according to claim 1, wherein a time division switch to which a potential is supplied is connected. 5. The display device according to claim 1, wherein the display elements forming the pixels are liquid crystal elements. 6. The display device according to claim 1, wherein the display element forming the pixel is an electroluminescent element.
The display device according to the above. 7. A pixel portion in which pixels are arranged at intersections between a plurality of rows of gate lines and a plurality of columns of signal lines arranged in a matrix on a transparent insulating substrate; A switch for a plurality of columns provided with one end connected to an end of the signal line for the plurality of columns opposite to a side to which the signal potential is supplied, and a predetermined DC potential applied to each pixel of the pixel portion. And a common line for commonly connecting the other ends of the switches for the plurality of columns.The display device further includes a switch for turning off the switches for the plurality of columns during a display driving period, and for a period other than the display driving period. A method for driving a display device, which is turned on. 8. The method according to claim 7, wherein a display element forming the pixel is a liquid crystal element. 9. The display device according to claim 7, wherein the display element forming the pixel is an electroluminescent element.
The driving method of the display device according to the above. 10. A pixel section in which pixels are arranged at intersections between a plurality of rows of gate lines and a plurality of columns of signal lines, which are wired in a matrix on a transparent insulating substrate; The other end of each of the plurality of columns of switches is connected to one end of each of the plurality of columns of signal lines, and the other end of each of the plurality of columns of switches is connected to the other end of the signal line. And a short line connected to the display device, wherein the plurality of columns of switches are turned on, and the plurality of columns of signal lines are turned on in the plurality of columns of switches. While applying a predetermined voltage to one end,
A method for inspecting a display device, comprising observing a current flowing through the short line. 11. The inspection method for a display device according to claim 10, wherein the short line is a common line that commonly supplies a predetermined DC potential to each pixel of the pixel unit. 12. The inspection method for a display device according to claim 10, wherein the display elements forming the pixels are liquid crystal elements. 13. The method according to claim 10, wherein the display element forming the pixel is an electroluminescent element.