JP2001036817A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device with good responsiveness capable of picking up an image of an object in a wide luminance range from a high luminance region to a low luminance region with high definition and by which each pixel is reset to an original state at high speed even in the low luminance area. SOLUTION: Reset is promptly performed by re-coupling positive electric charges stored in a drain, a gate of a MOS transistor T1, a gate of a MOS transistor T2 and an anode of a photodiode by setting a signal ϕVPS to be provided to a source of the first MOS transistor T1 as low level and making a state that negative electric charges are easy to flow in the MOS transistor T1 after image pickup operation of each pixel is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a plurality of pixels.

[0002]

2. Description of the Related Art Solid-state imaging devices are not only compact, lightweight and low power consumption, are free from image distortion and image sticking, and are resistant to environmental conditions such as vibration and magnetic fields. LSI (Large Scale)
Since it can be manufactured by a process common to or similar to that of an integrated circuit, it has high reliability and is suitable for mass production. For this reason, solid-state imaging devices having pixels arranged in a line are widely used in facsimile and flatbed scanners, and solid-state imaging devices having pixels arranged in a matrix are widely used in video cameras, digital cameras, and the like. By the way, such a solid-state imaging device is roughly classified into a CCD type and a MOS type by means for reading out (extracting) photocharges generated by a photoelectric conversion element. The CCD type has a drawback that the dynamic range is narrow because the photoelectric charge is transferred while being accumulated in the potential well. On the other hand, the MOS type uses the charge accumulated in the pn junction capacitance of the photodiode as M
Reading is performed through an OS transistor.

Here, one of the conventional MOS-type solid-state imaging devices is described.
The structure per pixel is shown in FIG. 18 and described. In the figure, PD is a photodiode whose cathode is M
The gate of the OS transistor T1 and the MOS transistor T
2 drain. MOS transistor T
1 is connected to the drain of the MOS transistor T3, and the source of the MOS transistor T3 is connected to the output signal line V3.
connected to out. The DC voltage VPD is applied to the drain of the MOS transistor T1, and the DC voltage VPS is applied to the source of the MOS transistor T2 and the anode of the photodiode.

When light enters the photodiode PD,
Photocharge is generated, and the charge is stored in the gate of the MOS transistor T1. Here, the MOS transistor T3
Pulse φV to the gate of the MOS transistor T3
Is turned on, a current proportional to the electric charge of the gate of the MOS transistor T1 is led to the output signal line Vout through the MOS transistors T1 and T3. In this way, an output current proportional to the amount of incident light can be read. After reading the signal, the MOS transistor T3 is turned off and the signal φRS is applied to the gate of the MOS transistor T2.
And turning on the MOS transistor T2,
The gate voltage of the S transistor T1 can be initialized.

[0005]

As described above, the conventional M
The OS-type solid-state imaging device reads out the photocharge generated by the photodiode in each pixel and stored in the gate of the MOS transistor as it is, so the dynamic range is narrow, and therefore, the exposure amount must be precisely controlled. In addition, even if the exposure amount is precisely controlled, dark portions are blackened and bright portions are saturated. On the other hand, the present applicant has disclosed a photosensitive means capable of generating a photocurrent corresponding to the amount of incident light, a MOS transistor for inputting the photocurrent, and a bias means for biasing the MOS transistor to a state in which a subthreshold current can flow. Prepared,
A solid-state imaging device that converts the photocurrent into a logarithm has been proposed (see Japanese Patent Application Laid-Open No. 3-192664).

After this solid-state imaging device performs an imaging operation,
When resetting to the original state, each pixel tends to receive a current having a polarity opposite to that of the photocurrent (referred to as “reset current”) into the MOS transistor until the state is in the low luminance range.
Photocharges charged in the OS transistor are recombined and reset at high speed. However, when each pixel is in the low-luminance region, the reset current is less likely to flow due to the influence of the threshold voltage of the MOS transistor. Therefore,
Since it is difficult for the photocharges charged in the MOS transistors to be recombined, it takes time to reset. As described above, since the response of each pixel deteriorates in the low luminance region, there is a problem that an afterimage is easily generated when the imaging operation is performed again.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and it is possible to image a subject in a wide luminance range from a high luminance region to a low luminance region with high definition. It is an object of the present invention to provide a solid-state imaging device with good responsiveness, which is quickly reset to the original state.

[0008]

According to a first aspect of the present invention, there is provided a solid-state imaging device, comprising: a photosensitive element for generating an electric signal corresponding to the amount of incident light; and a first electrode provided on the photosensitive element. A photoelectric conversion unit having a first transistor connected thereto and operating the first transistor in a subthreshold region to convert the electric signal into a natural logarithm; and an output signal of the photoelectric conversion unit to an output signal line. And a lead-out path for leading-out, wherein a first voltage is applied to a second electrode of the first transistor, and
The transistor is operated in the sub-threshold region to perform imaging, and the second electrode of the first transistor is connected to the second electrode.
A voltage is applied so that a larger current can flow through the first transistor than before applying the second voltage.

According to a second aspect of the present invention, there is provided a solid-state imaging storage device, comprising: a photoelectric conversion unit for generating an output signal obtained by natural number conversion of an incident light amount; and an output signal of the photoelectric conversion unit to an output signal line. In a solid-state imaging device having a plurality of pixels including a lead-out path for leading out, the photoelectric conversion unit includes a photoelectric conversion element having a first electrode to which a DC voltage is applied, a first electrode, a second electrode, and a control electrode. A first transistor in which a first electrode and a control electrode are connected to a second electrode of the photoelectric conversion element, and a first transistor into which an output current from the photoelectric conversion element flows, and a first electrode, a second electrode, and a control electrode. A DC voltage is applied to the first electrode, and a control electrode is connected to the first electrode and the control electrode of the first transistor;
A second transistor for outputting an electric signal from the electrode, applying a first voltage to a second electrode of the first transistor, and operating the first transistor in a sub-threshold region equal to or less than a threshold value to perform imaging. And the first
The reset is performed by applying a second voltage to the second electrode of the transistor and allowing a larger current to flow than before applying the second voltage to the first transistor.

According to a third aspect of the present invention, in the solid-state imaging device according to the second aspect, the pixels are arranged in a matrix.

According to a fourth aspect of the present invention, there is provided a solid-state imaging device according to any one of the first to third aspects, further comprising an integration circuit for integrating an electric signal output from the photoelectric conversion means. And deriving the signal integrated by the integration circuit to the output signal line via the derivation path.

According to such a configuration, since the output signal from each pixel is integrated by the integration circuit, the fluctuation component of the light source and high frequency noise contained in the output signal are absorbed and removed by the integration circuit. Also, as described in claim 5,
By providing reset means for releasing the charge of the integration circuit after outputting the integrated signal to the output signal line, initialization can be performed after each pixel outputs. The reset means includes a first electrode, a second electrode, and a control electrode, and a control electrode of the transistor, the first electrode being connected to the integration circuit. , The level of the voltage applied to the transistor is changed to make the transistor conductive, and the electric charge accumulated in the integration circuit can be released.

According to a seventh aspect of the present invention, in the solid-state imaging device according to the second or third aspect, each of the pixels has an amplifying transistor for amplifying an output signal of the photoelectric conversion unit. And outputting an output signal of the amplifying transistor to the output signal line via the output path.

According to such a solid-state imaging device, the output signal is amplified by the amplifying transistor and output with a sufficient magnitude, so that an imaging signal with high sensitivity is obtained. In such a solid-state imaging device, a load resistance or a constant current source connected to the output signal line and having a total number smaller than the total number of pixels may be provided.

As a load resistance or a constant current source, a first electrode connected to the output signal line, a second electrode connected to a DC voltage, and a control connected to the DC voltage. A resistor transistor having an electrode may be used. Further, when the amplifying transistor is an N-channel MOS transistor,
The DC voltage applied to the first electrode of the amplification transistor may be higher than the DC voltage connected to the second electrode of the resistance transistor. When the amplifying transistor is a P-channel MOS transistor,
The DC voltage applied to the first electrode of the amplification transistor may be lower than the DC voltage connected to the second electrode of the resistance transistor. Further, as the lead-out path, a predetermined path is sequentially selected from all the pixels as described in claim 12, and
A switch including a switch for leading a signal amplified from a selected pixel to an output signal line may be used.

According to a thirteenth aspect of the present invention, in the solid-state imaging device having a plurality of pixels, each pixel has a photodiode, and a first electrode and a gate electrode are connected to one electrode of the photodiode. A first MOS transistor; and a second MOS transistor having a gate electrode connected to a first electrode and a gate electrode of the first MOS transistor, and when the pixel performs an imaging operation, an electric signal output from the photodiode. When a first voltage is applied to a second electrode of the first MOS transistor to operate the first MOS transistor in a sub-threshold region equal to or less than a threshold so as to convert the pixel into a natural logarithm, A second voltage is applied to a second electrode of the first MOS transistor, and the second voltage is applied to the first transistor. Characterized by such a current to flow greater than before granting.

According to another aspect of the present invention, a first electrode is connected to a second electrode of the second MOS transistor, a second electrode is connected to an output signal line, and a gate electrode is connected to a row select transistor. A fourth MOS transistor connected to the line may be provided. In addition, as in the solid-state imaging device according to claim 15, a DC voltage is applied to a first electrode of the pixel, a gate electrode is connected to a second electrode of the second MOS transistor, and the second MOS transistor is connected to the pixel. MO that amplifies the output signal output from the second electrode of
An S transistor may be provided.

A solid-state imaging device according to a sixteenth aspect is the solid-state imaging device according to the fifteenth aspect, wherein the pixel comprises a first pixel.
An electrode is connected to a second electrode of the third MOS transistor, a second electrode is connected to an output signal line, and a gate electrode is connected to a row selection line.

The solid-state imaging device according to claim 17 is the solid-state imaging device according to claim 15 or 16,
The pixel has one end connected to a second electrode of the second MOS transistor, and a capacitor that is reset via the second MOS transistor when a reset voltage is applied to a first electrode of the second MOS transistor. It is characterized by the following.

The solid-state imaging device according to claim 18 is the solid-state imaging device according to claim 15 or 16,
A DC voltage is applied to a first electrode of the third MOS transistor, and the pixel includes a fifth MOS transistor having a first electrode connected to a second electrode of the second MOS transistor and a DC voltage applied to a second electrode. , The second
A capacitor having one end connected to the second electrode of the MOS transistor and being reset via the fifth MOS transistor when a reset voltage is applied to the gate electrode of the fifth MOS transistor. .

According to a nineteenth aspect of the present invention, in the solid-state imaging device according to any one of the thirteenth to eighteenth aspects, a load resistor or a constant resistor connected to the pixel via the output signal line is provided. It is characterized by having a MOS transistor as a current source.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment of Pixel Configuration Each embodiment of the solid-state imaging device of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a partial configuration of a two-dimensional MOS solid-state imaging device according to an embodiment of the present invention. In the figure, G11 to Gmn are arranged in a matrix (matrix arrangement).
FIG. Reference numeral 2 denotes a vertical scanning circuit, which sequentially scans rows (lines) 4-1, 4-2,..., 4-n. Reference numeral 3 denotes a horizontal scanning circuit, which sequentially reads out the photoelectric conversion signals derived from the pixels to the output signal lines 6-1, 6-2,..., 6-m for each pixel in the horizontal direction. 5 is a power supply line. For each pixel, the lines 4-1 and 4-
, 4-n and output signal lines 6-1, 6-2,.
6-m, not only the power supply line 5 but also other lines (for example, a clock line and a bias supply line) are connected, but these are omitted in FIG. 1 and shown in the first embodiment shown in FIG. ing.

The output signal lines 6-1, 6-2,..., 6
As shown, one N-channel MOS transistor Q2 is provided for each m. MOS transistor Q2
Is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3. As described later, an N-channel third MOS transistor T3 for switching is also provided in each pixel. Here, the MOS transistor T3 selects a row, and the MOS transistor Q2 selects a column.

<First Embodiment> A first embodiment (FIG. 2) applied to each pixel of the first example of the pixel configuration shown in FIG.
Will be described with reference to the drawings.

In FIG. 2, a pn photodiode PD
Form a photosensitive portion (photoelectric conversion portion). The anode of the photodiode PD is connected to a first MOS transistor T1.
, And the gate of the second MOS transistor T2. The source of the MOS transistor T2 is connected to the drain of a third MOS transistor T3 for row selection. The source of the MOS transistor T3 is an output signal line 6 (this output signal line 6
,..., 6-m).
The MOS transistors T1 to T3 are N-channel MOS transistors, each having a back gate grounded.

The DC voltage VPD is applied to the cathode of the photodiode PD. On the other hand, M
A signal φVPS is input to the source of the OS transistor T1, and one end of a capacitor C to which the DC voltage VPS is applied is connected to the other end of the source of the MOS transistor T2.
The signal φD is input to the drain of the MOS transistor T2, and the signal φ is input to the gate of the MOS transistor T3.
V is input. The signal φVPS is a binary voltage signal.
MOS transistor T1 at a voltage substantially equal to DC voltage VPS
Is set at a high level, and a voltage lower than this voltage for turning on the MOS transistor T1 is set at a low level.

(1) Operation for converting incident light to each pixel into an electric signal In a pixel having a circuit configuration as shown in FIG. 2, the MOS transistor T1 operates in a sub-threshold region.
The signal φVPS applied to the source of the MOS transistor T1 is set to a high level. At this time, when light enters the photodiode PD, a photocurrent is generated, and a voltage having a value obtained by natural logarithmically converting the photocurrent is generated at the gates of the MOS transistors T1 and T2 due to the subthreshold characteristic of the MOS transistor. With this voltage, a current flows through the MOS transistor T2, and a charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C. That is, a voltage proportional to a value obtained by natural logarithmically converting the integrated value of the photocurrent is generated at the connection node a between the capacitor C and the source of the MOS transistor T2. However, at this time, the MOS transistor T3 is turned off.
This is the state of F.

Next, a pulse signal φV is applied to the gate of the MOS transistor T3 to turn on the MOS transistor T3.
When N is set, the electric charge accumulated in the capacitor C is led out to the output signal line 6 as an output current. This output signal line 6
Is a value obtained by natural logarithmically converting the integrated value of the photocurrent. In this manner, a signal (output current) proportional to the logarithmic value of the incident light amount can be read.
After reading the signal, the MOS transistor T3 is turned off.
I do.

(2) Reset Operation of Each Pixel The reset operation of the pixel having the circuit configuration as shown in FIG. 2 will be described below with reference to the drawings. FIG. 3 is a timing chart of signals applied to each signal line connected to each element in a pixel when performing a reset operation. Also, FIG.
FIG. 9 is a diagram illustrating a potential state of a photodiode PD and a MOS transistor T1 when each pixel is reset. FIG. 4A shows the photodiode PD and the MO.
FIG. 4B is a cross-sectional view illustrating the structure of the S-transistor T1, and FIGS. 4B to 4E are diagrams illustrating potentials of respective portions according to the cross-sectional view of FIG. 4A. FIG.
In (b) to (e), the direction of the arrow indicates that the potential is high.

By the way, the photodiode PD is, for example, as shown in FIG.
It is called "P-type substrate". ), An N-type well layer 11 is formed, and a P-type diffusion layer 1 is formed in the N-type well layer 11.
2 is provided. In the MOS transistor T1, N-type diffusion layers 13 and 14 are formed on a P-type substrate 10, and an oxide film 15 and a polysilicon layer 16 are sequentially formed on a channel between the N-type diffusion layers 13 and 14. It is constituted by doing. Here, the N-type well layer 11
Forms the cathode side of the photodiode PD, and the P-type diffusion layer 12 forms the anode side. Further, the N-type diffusion layers 13 and 14 are respectively formed by MOS transistors T1.
And the oxide film 15 and the polysilicon layer 16 form a gate insulating film and a gate electrode, respectively. Here, in the P-type substrate 10,
The region between the N-type diffusion layers 13 and 14 is referred to as a region under the gate.

As described in (1), by applying the pulse φV to the gate of the MOS transistor T3,
An electric signal (output signal) obtained by logarithmically converting incident light from each pixel having a circuit configuration as shown in FIG. 2 is output to the output signal line 6. When the output signal is output and the pulse φV becomes low level, the reset operation starts. This reset operation will be described with reference to FIGS.

First, the pulse signal φV is applied to the transistor T3
After the output signal is output to the gates of the gates, the reset operation starts. That is, negative charges flow from the source side of the MOS transistor T1, and the positive charges stored in the gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD are recombined. Therefore, as shown in FIG. 4B, the MOS transistor T1 is reset to a certain extent, and the potential of the region under the drain and the gate of the MOS transistor T1 decreases.

As described above, the potential of the region under the drain and the gate of the MOS transistor T1 is about to be reset to the original state, but when the potential reaches a certain value, the speed at which the potential is reset becomes slow. In particular, this tendency becomes remarkable when a bright subject suddenly becomes dark. Therefore, next, the signal φVPS applied to the source of the MOS transistor T1 is set to low level. Thus, M
By lowering the source voltage of the OS transistor T1, the potential of the MOS transistor T1 increases as shown in FIG.
It changes as shown in (c). Therefore, the amount of negative charges flowing from the source of the MOS transistor T1 increases,
Positive charges stored in the gate and drain of the S transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD are quickly recombined.

Therefore, as shown in FIG. 4D, the potential of the region under the drain and gate of the MOS transistor T1 is lower than that in the state of FIG. 4C. When the potential of the MOS transistor T1 changes as shown in FIG. 4D, the signal φ applied to the source of the MOS transistor T1
Set VPS to high level. Therefore, the potential state of the MOS transistor T1 is reset to the original state as shown in FIG. As described above, after resetting the potential state of the MOS transistor T1 to the original state, the voltage of the signal φD is changed to low level, the capacitor C is discharged, and the potential of the connection node a is reset to the original state. After that, the voltage of the signal φD is returned to the high level, and the imaging operation is performed.

As described above, by resetting by controlling the potential applied to the source of the MOS transistor T1 whose drain is electrically connected to the photodiode PD, which is a photosensitive element, the responsiveness of each pixel of the solid-state imaging device can be improved. Is improved. Therefore, even when a dark subject is imaged, or when a bright subject suddenly becomes dark, afterimages are prevented from being generated, and good imaging can be performed.

The signal reading from each pixel may be performed using a charge-coupled device (CCD).
In this case, the charge can be read out to the CCD by providing a potential barrier having a variable potential level corresponding to the MOS transistor T3 in FIG.

<Second Example of Pixel Configuration> FIG. 5 schematically shows a partial configuration of a two-dimensional MOS solid-state imaging device according to another embodiment of the present invention. In the figure, G11 to Gm
n indicates pixels arranged in a matrix (matrix arrangement). Reference numeral 2 denotes a vertical scanning circuit, and rows (lines) 4-1 and 4
.., 4-n are sequentially scanned. Reference numeral 3 denotes a horizontal scanning circuit which outputs output signal lines 6-1 to 6-2,.
.. The photoelectric conversion signals derived in 6-m are sequentially read in the horizontal direction for each pixel. 5 is a power supply line. .., 4-n, output signal lines 6-1, 6-2,.
In addition, other lines (for example, a clock line and a bias supply line) are also connected, but these are omitted in FIG. 5 and are shown in each embodiment after FIG.

The output signal lines 6-1, 6-2,.
As shown in the figure, a set of N-channel MOS transistors Q1 and Q2 is provided for each m. MOS transistor Q1 has a gate connected to DC voltage line 7, a drain connected to output signal line 6-1, and a source connected to DC voltage VPS '.
Is connected to the line 8. On the other hand, the drain of the MOS transistor Q2 is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3.

As described later, the pixels G11 to Gmn have
An N-channel MOS transistor Ta for outputting a signal based on photocharges generated in those pixels is provided. FIG. 6A shows the connection between the MOS transistor Ta and the MOS transistor Q1. This MO
The S transistor Ta corresponds to the fourth MOS transistor T4 in the second and third embodiments, and corresponds to the second MOS transistor T2 in the fourth embodiment. Where MOS
DC voltage VPS 'connected to the source of transistor Q1
And the DC voltage VPD 'connected to the drain of the MOS transistor Ta is VPD'> VPS ', and the DC voltage VPS' is, for example, a ground voltage (ground). In this circuit configuration, a signal is input to the gate of the upper MOS transistor Ta, and a DC voltage DC is constantly applied to the gate of the lower MOS transistor Q1. Therefore, the lower MO
The S transistor Q1 is equivalent to a resistor or a constant current source,
The circuit in FIG. 6A is a source follower type amplifier circuit. In this case, what is amplified and output from the MOS transistor Ta may be a current.

The MOS transistor Q2 is connected to the horizontal scanning circuit 3
And is operated as a switch element. still,
As described later, an N-channel third MOS transistor T3 for switching is also provided in the pixel of each of the embodiments after FIG. If this MOS transistor T3 is also included, the circuit of FIG. 6A is exactly as shown in FIG. 6B. That is, the MOS transistor T3 is inserted between the MOS transistor Q1 and the MOS transistor Ta. Here, the MOS transistor T3 selects a row, and the MOS transistor Q2 selects a column. The configuration shown in FIGS. 5 and 6 is a configuration common to the second to fourth embodiments described below.

With the configuration shown in FIG. 6, a large signal can be output. Therefore, when the pixel converts the photocurrent generated from the photosensitive element in a natural logarithmic manner to expand the dynamic range, the output signal is small as it is, but is amplified to a sufficiently large signal by the present amplifier circuit. Therefore, processing in a subsequent signal processing circuit (not shown) is facilitated. Further, the MOS transistor Q1 forming the load resistance portion of the amplifier circuit is not provided in the pixel, and the output signal line 6 to which a plurality of pixels arranged in the column direction are connected is connected.
.., 6-m, the load resistance or the number of constant current sources can be reduced, and the area occupied by the amplifier circuit on the semiconductor chip can be reduced.

<Second Embodiment> A second embodiment applied to each pixel of the second example of the pixel configuration shown in FIG. 5 will be described with reference to the drawings. FIG. 7 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 7, in this embodiment, FIG.
And a fourth MOS transistor T4 whose gate is connected to the connection node a and amplifies current according to the voltage of the connection node a, and a fifth MOS transistor T4 that initializes the potential of the connection node a
MOS transistor T5 is added. M
The source of the OS transistor T4 is the MOS transistor T
3 and a MOS transistor T3
Is the output signal line 6 (this output signal line 6 is
-1, 6-2,..., 6-m). The MOS transistors T4 and T5 are also MOS transistors.
Similarly to the transistors T1 to T3, an N-channel MOS
The back gate of the transistor is grounded.

The DC voltage VPD is applied to the drain of the MOS transistor T4, and the signal φV is input to the gate of the MOS transistor T3. The DC voltage V RB is applied to the source of the MOS transistor T5, and the signal φVRS is input to its gate. Further, M
The DC voltage VPD is applied to the drain of the OS transistor T2. In this embodiment, the MOS transistors T1 to T3 and the capacitor C perform the same operation as in the first embodiment (FIG. 2), and output an electric signal (output signal) obtained by logarithmically converting incident light. be able to.

(1) Operation for converting incident light to each pixel into an electric signal In this embodiment, the voltage value of signal φVPS is set to a high level, and MOS transistor T1 is operated in a sub-threshold region. As in the first embodiment, an output signal obtained by natural logarithmically converting the photocurrent output from the photodiode PD according to the incident light can be output to the output signal line 6. Hereinafter, the operation of each element in the pixel shown in FIG. 7 when outputting an output signal obtained by converting the photocurrent into a natural logarithm will be described.

When light is incident on the photodiode PD, a photocurrent is generated, and a voltage having a value obtained by natural logarithmic conversion of the photocurrent is generated at the gates of the MOS transistors T1 and T2 due to the subthreshold characteristic of the MOS transistor. With this voltage, a current flows through the MOS transistor T2, and a charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent is accumulated in the capacitor C. That is, a voltage proportional to a value obtained by natural logarithmically converting the integrated value of the photocurrent is generated at the connection node a between the capacitor C and the source of the MOS transistor T2. However, at this time, the MOS transistors T3 and T5 are in the OFF state.

Next, a pulse signal φV is applied to the gate of the MOS transistor T3 to turn on the MOS transistor T3.
When N is set, a current proportional to the voltage applied to the gate of the MOS transistor T4 is led out to the output signal line 6 through the MOS transistors T3 and T4. Since the voltage applied to the gate of the MOS transistor T4 is a voltage applied to the connection node a, the current led out to the output signal line 6 is a value obtained by natural logarithmically converting the integrated value of the photocurrent. After reading a signal (output current) proportional to the logarithmic value of the incident light amount in this manner, the MOS transistor T3 is turned off.
To

(2) Reset Operation of Each Pixel Hereinafter, the reset operation of the pixel having the circuit configuration shown in FIG. 7 will be described with reference to the drawings. FIG. 8 is a timing chart of signals applied to each signal line connected to each element in a pixel when performing a reset operation. As described in (1), by applying the pulse φV to the gate of the MOS transistor T3, each pixel having a circuit configuration as shown in FIG. Output to line 6. When the output signal is output and the pulse φV becomes low level, the reset operation starts. Further, the state of the potential of the MOS transistor T1 when resetting the pixel of the present embodiment is as shown in FIGS. 4B to 4E as in the first embodiment. Therefore, the reset operation will be described with reference to FIGS.

First, after the pulse signal φV is applied to the gate of the MOS transistor T3 to output an output signal, the reset operation starts. Then, similarly to the first embodiment, negative charges flow from the source side of the MOS transistor T1, and the potential of the MOS transistor T1 becomes a state as shown in FIG.

Next, the signal φVPS applied to the source of the MOS transistor T1 is set to low level, and the MOS transistor T1 is turned on as shown in FIG. Therefore, the amount of the negative charge flowing from the source of the MOS transistor T1 increases, and the positive charge stored in the gate and the drain of the MOS transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD is quickly restored. Be combined.

Therefore, as shown in FIG. 4D, the potential of the region under the drain and the gate of the MOS transistor T1 becomes low. When the potential of the MOS transistor T1 changes as described above, the signal φVPS applied to the source of the MOS transistor T1 is set to a high level. Therefore,
FIG. 4 shows the potential state of the MOS transistor T1.
The state is reset to the original state as shown in FIG. After resetting the potential state of the MOS transistor T1 to the original state in this way, a pulse signal φVRS is applied to the gate of the MOS transistor T5, the capacitor C is discharged via the MOS transistor T5, and the potential of the connection node a is determined based on the potential of the connection node a. Reset to state.

<Third Embodiment> A third embodiment will be described with reference to the drawings. FIG. 9 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 9, in the present embodiment, the MO
By applying a signal φD to the drain of the S transistor T2, the potentials of the capacitor C and the connection node a are initialized, thereby eliminating the MOS transistor T5. Other configurations are the same as those of the second embodiment (FIG. 7). During the high level period of the signal φD, integration is performed by the capacitor C as in the first embodiment (FIG. 2). During the low level period, the charge of the capacitor C is discharged through the MOS transistor T2.
The voltage of the capacitor C and the gate of the MOS transistor T4 substantially become the low level voltage of the signal φD (reset).
In the present embodiment, the configuration is simplified because the MOS transistor T5 can be omitted.

In this embodiment, when the imaging operation is performed, the signal φVPS applied to the source of the MOS transistor T1 is set to the high level, as in the second embodiment.
The MOS transistor T1 operates in the sub-threshold state. Also, the signal φD is set to a high level,
A charge equivalent to a value obtained by natural logarithmically converting the integrated value of the photocurrent is stored in the capacitor C. Then, the MOS transistor T3 is turned on at a predetermined timing, and the current proportional to the voltage applied to the gate of the MOS transistor T4 is set to MO.
It is led to the output signal line 6 through the S transistors T3 and T4.

When resetting each pixel, the signals are controlled at the timing shown in FIG. 3 as in the first embodiment.
That is, first, similarly to the first embodiment, the pulse signal φV
, The reset operation starts. Next, MOS
The signal φVPS applied to the source of the transistor T1 is set to low level to make the MOS transistor T1 conductive, thereby increasing the amount of negative charges flowing from the source of the MOS transistor T1. Therefore, similarly to the first embodiment, the positive charges accumulated in the gate and drain of the MOS transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD are quickly recombined.

Then, the signal φVPS applied to the source of the MOS transistor T1 is set to the high level, and the potential state of the MOS transistor T1 is reset to the original state. As described above, after resetting the potential state of the MOS transistor T1 to the original state, the voltage of the signal φD is changed to low level, the capacitor C is discharged, and the potential of the connection node a is reset to the original state. After that, the voltage of the signal φD is returned to the high level, and the imaging operation is performed.

<Fourth Embodiment> A fourth embodiment will be described with reference to the drawings. FIG. 10 is a circuit diagram illustrating a configuration of a pixel provided in the solid-state imaging device used in the present embodiment. Elements and signal lines used for the same purpose as the pixel shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 10, in this embodiment, M
The DC voltage VPD is applied to the drain of the OS transistor T2, and the capacitor C and the MOS transistor T4 are omitted. That is, the drain of the MOS transistor T3 is connected to the source of the MOS transistor T2. Other configurations are the same as those of the third embodiment (FIG. 9).

When the imaging operation is performed in the circuit having such a configuration, as in the third embodiment, the signal φVPS applied to the source of the MOS transistor T1 is set to the high level, and the MOS transistor T1 is in the sub-threshold state. Make it work. By operating the MOS transistor T1 in this manner, a drain current having a value proportional to the natural logarithm of the photocurrent flows through the MOS transistor T2.

When a pulse signal φV is applied to the gate of the MOS transistor T3 to turn on the MOS transistor T3, the drain current having a value proportional to the logarithm of the photocurrent in natural logarithm is obtained.
It is led to the output signal line 6 through the S transistor T3. At this time, the drain voltage of the MOS transistor Q1 determined by the on-state resistance of the MOS transistor T2 and the MOS transistor Q1 (FIG. 5) and the current flowing therethrough appears on the output signal line 6 as a signal. After the signal is read out in this manner, the MOS transistor T3 is turned off.
Set to FF.

When resetting each pixel, similarly to the third embodiment, first, after a pulse signal φV is applied, a reset operation starts. Next, the signal φVPS given to the source of the MOS transistor T1 is set to low level,
By making the MOS transistor T1 conductive, the amount of negative charge flowing from the source of the MOS transistor T1 is increased.

Therefore, as in the first embodiment, the MOS
Positive charges stored in the gate and drain of the transistor T1, the gate of the MOS transistor T2, and the anode of the photodiode PD are quickly recombined.
Then, the signal φVPS applied to the source of the MOS transistor T1 is set to the high level, and the potential state of the MOS transistor T1 is reset to the original state. As described above, the potential state of the MOS transistor T1 is reset to the original state, and the imaging operation can be performed again.

In this embodiment, as in the third embodiment, since the optical signal is not once integrated by the capacitor C, the integration time is not required, and the reset of the capacitor C is not required. As a result, the signal processing can be speeded up accordingly. Further, in the present embodiment, as compared with the third embodiment, since the capacitor C and the MOS transistor T4 can be omitted, the configuration is further simplified and the pixel size can be reduced.

In the first to fourth embodiments described above, the MOS transistors T1 to T5 as active elements in the pixel are all constituted by N-channel MOS transistors. All may be constituted by P-channel MOS transistors. FIG.
15 to 17 show fifth to eighth embodiments, which are examples in which the first to fourth embodiments are configured by P-channel MOS transistors. Therefore, the polarity of the connection and the polarity of the applied voltage are reversed in FIGS. For example, in FIG. 12 (fifth embodiment), the photodiode PD has an anode connected to the DC voltage VPD, a cathode connected to the drain of the first MOS transistor T1, and a gate connected to the gate of the second MOS transistor T2. . The signal φVPS is input to the source of the MOS transistor T1.

By the way, when the pixel as shown in FIG. 12 performs logarithmic conversion, the DC voltage VPS and the DC voltage VPD satisfy VPS> V.
PD, which is the reverse of FIG. 2 (first embodiment). The output voltage of the capacitor C is a voltage having a high initial value and drops by integration. When turning on the third MOS transistor T3, a low voltage is applied to the gate. Further, in the embodiment of FIG. 15 (sixth embodiment), when turning on the fifth MOS transistor T5, a low voltage is applied to the gate. As described above, when the P-channel MOS transistor is used, the voltage relationship and the connection relationship are partially different from those in the case where the N-channel MOS transistor is used, but the configuration is substantially the same. 12 and 15 to 17 are only shown in the drawings, and the description of the configuration and operation is omitted.

FIG. 1 is a block circuit configuration diagram for explaining the overall configuration of a solid-state imaging device including pixels according to a fifth embodiment.
FIG. 13 is a block circuit configuration diagram illustrating the entire configuration of the solid-state imaging device including the pixels according to the sixth to eighth embodiments shown in FIG. 11 and 13, the same portions (same role portions) as those in FIGS. 1 and 5 are denoted by the same reference numerals, and description thereof is omitted. Hereinafter, the configuration of FIG. 13 will be briefly described. Output signal lines 6 arranged in the column direction
, 6-m, P-channel MO
The S transistor Q1 and the P-channel MOS transistor Q2 are connected. MOS transistor Q1 has a gate connected to DC voltage line 7, and a drain connected to output signal line 6.
-1 and the source is connected to line 8 of the DC voltage VPS '.

On the other hand, the drain of the MOS transistor Q 2 is connected to the output signal line 6-1, the source is connected to the final signal line 9, and the gate is connected to the horizontal scanning circuit 3. Here, the MOS transistor Q1 forms an amplifier circuit as shown in FIG. 14A together with the P-channel MOS transistor Ta in the pixel. The MOS transistor Ta corresponds to the fourth MOS transistor T4 in the sixth and seventh embodiments, and corresponds to the second MOS transistor T4 in the eighth embodiment.
This corresponds to the MOS transistor T2.

In this case, MOS transistor Q1 is
It serves as a load resistance or a constant current source for the S transistor Ta. Accordingly, the relationship between the DC voltage VPS 'connected to the source of the MOS transistor Q1 and the DC voltage VPD' connected to the drain of the MOS transistor Ta is VP
D ′ <VPS ′, and the DC voltage VPD ′ is, for example, a ground voltage (ground). The drain of the MOS transistor Q1 is connected to the MOS transistor Ta, and a DC voltage is applied to the gate. The P-channel MOS transistor Q2 is controlled by the horizontal scanning circuit 3, and leads the output of the amplifier circuit to the final signal line 9. Considering the third MOS transistor T3 provided in the pixel as in the sixth to eighth embodiments, the circuit of FIG.
It is represented as shown in FIG.

[0069]

As described above, according to the solid-state imaging device of the present invention, each pixel can be reset quickly, so that the responsiveness at the time of imaging can be improved, and a low-luminance subject can be obtained. Can be eliminated when an image is captured. In addition, since the active element is formed of a MOS transistor, high integration is facilitated and the active element can be formed on a single chip together with peripheral processing circuits (A / D converter, digital system processor, memory) and the like.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of one pixel according to the first embodiment of the present invention.

FIG. 3 is a timing chart of a signal applied to each element of a pixel used in the first embodiment.

FIG. 4 is a diagram illustrating a relationship between a configuration and a potential of a pixel used in the present invention.

FIG. 5 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to an embodiment of the present invention.

FIG. 6 is a partial circuit diagram of FIG. 5;

FIG. 7 is a circuit diagram showing a configuration of one pixel according to a second embodiment of the present invention.

FIG. 8 is a timing chart of signals applied to each element of a pixel used in the second embodiment.

FIG. 9 is a circuit diagram showing a configuration of one pixel according to a third embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of one pixel according to a fourth embodiment of the present invention.

FIG. 11 is a block circuit diagram for explaining the overall configuration of a two-dimensional solid-state imaging device according to the present invention in the case where an active element in a pixel is configured by a P-channel MOS transistor.

FIG. 12 is a circuit diagram showing a configuration of one pixel according to a fifth embodiment of the present invention.

FIG. 13 is a block circuit diagram for explaining the overall configuration of the two-dimensional solid-state imaging device of the present invention in the case of an embodiment in which an active element in a pixel is configured by a P-channel MOS transistor.

FIG. 14 is a partial circuit diagram of FIG. 13;

FIG. 15 is a circuit diagram showing a configuration of one pixel according to a sixth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration of one pixel according to a seventh embodiment of the present invention.

FIG. 17 is a circuit diagram showing a configuration of one pixel according to an eighth embodiment of the present invention.

FIG. 18 is a circuit diagram showing a configuration of one pixel of a conventional example.

[Explanation of symbols]

 G11 to Gmn pixel 2 vertical scanning circuit 3 horizontal scanning circuit 4-1 to 4-n row selection line 6-1 to 6-m output signal line 7 DC voltage line 8 line 9 signal line 10 P-type semiconductor substrate 11 N-type well Layer 12 P-type diffusion layer 13, 14 N-type diffusion layer 15 Oxide film 16 Polysilicon PD Photodiode T1 to T5 First to fifth MOS transistors C Capacitor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA02 AA05 AB01 BA14 CA02 CA03 FA06 5C024 BA01 CA08 CA15 CA20 GA01 GA33 HA05 JA04 JA29 5F049 MA02 NA03 NA19 NB05 QA01 RA02 UA01 UA07

Claims (19)

[Claims] 1. A photosensitive element for generating an electric signal according to an amount of incident light, and a first element having a first electrode connected to the photosensitive element.
A photoelectric conversion means having a transistor of the type described above and operating the first transistor in a subthreshold region to convert the electrical signal into a natural logarithm; and a lead-out path for leading an output signal of the photoelectric conversion means to an output signal line. Wherein a first voltage is applied to a second electrode of the first transistor to operate the first transistor in a sub-threshold region to perform imaging, and a second voltage of the first transistor A solid-state imaging device, wherein a second voltage is applied to the electrode so that a larger current can flow through the first transistor than before the second voltage is applied. 2. A plurality of pixels each comprising: a photoelectric conversion unit for generating an output signal obtained by natural number conversion of an incident light amount; and a derivation path for deriving an output signal of the photoelectric conversion unit to an output signal line. Wherein the photoelectric conversion means comprises: a photoelectric conversion element in which a DC voltage is applied to a first electrode; a first electrode, a second electrode, and a control electrode; A first transistor connected to a second electrode of the conversion element and into which an output current from the photoelectric conversion element flows; a first electrode, a second electrode, and a control electrode; and a DC voltage is applied to the first electrode. A control electrode is connected to the first electrode and the control electrode of the first transistor, and a second transistor outputs an electric signal from the second electrode. The second electrode of the first transistor is connected to the second electrode of the first transistor. 1 den And imaging is performed by operating the first transistor in a sub-threshold region equal to or less than a threshold. A second voltage is applied to a second electrode of the first transistor, and the second voltage is applied to the first transistor. A solid-state imaging device that performs reset so that a larger current than before applying a voltage can flow. 3. The solid-state imaging device according to claim 2, wherein the pixels are arranged in a matrix. 4. An integrated circuit for integrating an electric signal output from the photoelectric conversion means, wherein the signal integrated by the integration circuit is derived to the output signal line via the derivation path. The solid-state imaging device according to claim 1. 5. The solid-state imaging device according to claim 4, further comprising a reset unit that releases the charge of the integration circuit after outputting the integrated signal to the output signal line. 6. The reset means comprises a transistor having a first electrode, a second electrode, and a control electrode, wherein the transistor has a first electrode connected to the integration circuit, and a voltage applied to a control electrode of the transistor. 6. The solid-state imaging device according to claim 5, wherein when the level is changed and the transistor is turned on, charges accumulated in the integration circuit are released. 7. Each of the pixels has an amplifying transistor for amplifying an output signal of the photoelectric conversion means, and outputs an output signal of the amplifying transistor to the output signal line via the output path. The solid-state imaging device according to claim 2, wherein: 8. The solid state according to claim 7, further comprising a load resistor or a constant current source connected to the output signal line, wherein the total number of the load resistors or the constant current source is smaller than the total number of pixels. Imaging device. 9. The load resistor or the constant current source has a first electrode connected to the output signal line, a second electrode connected to a DC voltage, and a control electrode connected to a DC voltage. The solid-state imaging device according to claim 8, wherein the solid-state imaging device is a transistor for use. 10. The amplifying transistor is an N-channel MOS transistor, and a DC voltage applied to a first electrode of the amplifying transistor is lower than a DC voltage connected to a second electrode of the resistor transistor. The solid-state imaging device according to claim 9, wherein the solid-state imaging device has a high potential. 11. The amplifying transistor is a P-channel MOS transistor, and a DC voltage applied to a first electrode of the amplifying transistor is lower than a DC voltage connected to a second electrode of the resistor transistor. The solid-state imaging device according to claim 9, wherein the solid-state imaging device has a low potential. 12. The method according to claim 2, wherein the derivation path includes a switch for sequentially selecting a predetermined one from all the pixels and deriving an output signal of the selected pixel to an output signal line. The solid-state imaging device according to any one of claims 3 to 7. 13. A solid-state imaging device having a plurality of pixels, wherein each pixel includes a photodiode, a first MOS transistor having a first electrode and a gate electrode connected to one electrode of the photodiode, and the first MOS transistor. And a second MOS transistor having a gate electrode connected to the first electrode and the gate electrode. When the pixel performs an imaging operation, an electric signal output from the photodiode is converted into a natural logarithm. Applying a first voltage to a second electrode of the first MOS transistor to operate the first MOS transistor in a sub-threshold region equal to or less than a threshold value; Applying a second voltage to provide a greater current than before applying the second voltage to the first transistor; A solid-state imaging device, characterized in that the solid-state imaging device can flow. 14. The pixel according to claim 1, wherein the first electrode is the second MO.
14. The solid-state imaging device according to claim 13, further comprising a fourth MOS transistor connected to a second electrode of the S transistor, the second electrode connected to an output signal line, and a gate electrode connected to a row selection line. . 15. An output signal output from the second electrode of the pixel, wherein a DC voltage is applied to a first electrode of the pixel, a gate electrode is connected to a second electrode of the second MOS transistor, and a second electrode of the second MOS transistor is provided. The third that amplifies
2. The semiconductor device according to claim 1, further comprising a MOS transistor.
4. The solid-state imaging device according to 3. 16. The pixel according to claim 1, wherein the first electrode is the third MO.
The solid-state imaging device according to claim 15, further comprising a fourth MOS transistor connected to a second electrode of the S transistor, the second electrode connected to an output signal line, and a gate electrode connected to a row selection line. . 17. The pixel according to claim 17, wherein one end of the pixel is connected to a second electrode of the second MOS transistor.
2. A capacitor which is reset via the second MOS transistor when a reset voltage is applied to a first electrode of the MOS transistor.
The solid-state imaging device according to claim 5 or 16. 18. A DC voltage is applied to a first electrode of the second MOS transistor, and a first electrode is connected to a second electrode of the second MOS transistor, and a DC voltage is applied to a second electrode of the second MOS transistor. A fifth MOS transistor, a capacitor having one end connected to a second electrode of the second MOS transistor and being reset via the fifth MOS transistor when a reset voltage is applied to a gate electrode of the fifth MOS transistor; The solid-state imaging device according to claim 15, comprising: 19. The apparatus according to claim 13, further comprising a MOS transistor forming a load resistor or a constant current source connected to said pixel via said output signal line. Solid-state imaging device.