JP2001036594A - Method for digitally demodulating phase modulation signal in hierarchical transmission to detect frame synchronization pattern and its system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a detection time of a frame synchronization pattern in a phase modulation signal (B-PSK) at a lowest transmission rate in hierarchical transmission and to enhance the detection accuracy. SOLUTION: A configuration from an in-phase detector 2a to a B-PSK period detection circuit 17 digitally demodulates a phase modulation signal in hierarchical transmission to detect a frame synchronization pattern. I, Q signals resulting from detecting the received phase modulation signal are digitally converted. Complex multiplication is applied between the I, Q signals and a recovered carrier. Moreover, a phase difference signal is outputted from a complex arithmetic output signal, this phase difference signal is delayed by one symbol, and a detection signal denoting a period of phase modulation for a lowest transmission rate is outputted resulting from applying cosine absolute value arithmetic operation to a phase difference between a phase signal and the phase difference signal delayed by one symbol.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a phase modulated wave (PSK / Phase Sh) having different carrier / noise power (C / N) ratios in satellite / terrestrial digital broadcasting and the like.
In particular, the present invention relates to a method of receiving and demodulating ift keying, and in particular, to a frame synchronization pattern and a quadrature (PS) / 8 modulated by a B (Binary) -PSK using a hierarchical transmission scheme.
A method of digitally demodulating a phase-modulated signal in hierarchical transmission when receiving and demodulating a time-multiplexed PSK-modulated signal that combines PSK modulation and is repeatedly transmitted for each frame to detect a frame synchronization pattern; Related to the device.

[0002]

2. Description of the Related Art Conventionally, in satellite digital communication and satellite digital broadcasting, it has been difficult to enhance the stability of a frequency converter inside a repeater mounted on a satellite, and also in a satellite digital communication / broadcast receiver. Since the frequency conversion is performed by a simple circuit, large frequency detuning is likely to occur. For this frequency detuning, a frequency sweep of the carrier is performed in order to perform carrier regeneration. In the satellite broadcast receiver, this frequency sweep is performed after the power is turned on or after the tuning frequency is changed. When a frame synchronization signal (pattern) is detected, it is determined that the synchronization has been established, and the state shifts to the tracking state.

[0003] As a BS satellite digital broadcast, a plurality of phase modulation (PSK) systems having different C / N ratios, for example, 8-
Combine PSK, Q-PSK, B-PSK, and
Hierarchical transmission schemes are employed in which transmission is repeated for each frame. In this layered transmission, the lower layer Q-PS
The reception performance is extended to the C / N ratio of K, B-PSK modulation. The B-PSK signal can be received at a lower C / N ratio. However, when a low-layer B-PSK modulated wave is received under a low C / N ratio state, only the B-PSK period is used. Carrier pull-in processing is performed.

FIG. 3 is a block diagram showing a configuration of a conventional PSK digital demodulation device using a digital phase locked loop (PLL) carrier recovery system. In FIG. 3, a digital modulation signal input to a phase modulation signal input terminal 1 is distributed to an in-phase detector 2a and a quadrature detector 2b.
Is input to The local oscillation signal (0-degree phase) from the local oscillator 3 is input to the in-phase detector 2a, and the local oscillation signal is 90-degree (π
/ 2) The local oscillation signal that has been shifted by 90 degrees (π / 2 shift) by the phase shift circuit 4 is input to the quadrature detector 2b, and a baseband signal by quadrature demodulation is output.

The baseband signals are converted into digital values by A / D converters 5a and 5b, respectively,
Is input to The output signal of the complex multiplier 6 is input to roll-off filters (digital low-pass filters) 7a and 7b, and is formed here to have transmission characteristics required for preventing intersymbol interference in digital data transmission. In this case, a roll-off characteristic is obtained when combined with the filter characteristic on the transmission side.

In the output signals of the roll-off filters (digital low-pass filters) 7a and 7b, each detection output is subjected to spectral shaping so that the eye opening ratio becomes sufficiently large. The I and Q signals of the complex multiplier 6 and the output signals of the roll-off filters 7a and 7b are branched and clock recovery is performed, and symbol timing components in the signals are extracted and A / D converters 5a and 5b And other circuits. The complex multiplier 6 is realized by the same operation as that of the frequency converter (mixer) in the intermediate frequency band.

The output signals of the roll-off filters 7a and 7 are input to a phase detector 8, and a phase difference between the input signal and a numerically controlled oscillator (NCO) 10 is detected. Also,
The phase difference signal from the phase detector 8 is input to the frequency control terminal of the numerically controlled oscillator 10 through the loop filter 9 for carrier recovery. The numerically controlled oscillator 10 is a cumulative addition circuit that does not inhibit overflow. That is,
The operation is similar to that of a voltage controlled oscillator (VCO) in an analog circuit, but the oscillation frequency is extremely stable.
It has more stability than VCXO using a quartz oscillator and a wide frequency variable range.

The output signal of the numerically controlled oscillator 10 branches into two and is input to the complex multiplier 6 through data conversion circuits 11 and 12 having sine and cosine characteristics, respectively. That is, carrier reproduction is performed by a digital phase locked loop (PLL) having a digital configuration. In the lock signal by the carrier reproduction, the frame synchronization pattern detection circuit 13 detects the frame synchronization pattern to determine the absolute phase axis.

As a method for obtaining the same absolute phase, a digital modulation transmitted by a plurality of modulation signals (for example, 8-PSK, Q-PSK, B-PSK) having different required C / N ratios is used. In this method, a frame synchronization pattern is detected from a demodulated baseband signal, a current reception signal phase rotation direction is detected from a signal arrangement of the detected synchronization signal, and an absolute phase of the signal is detected based on the detected reception signal. There is known a method of calculating the phase of the signal and matching it with the phase transmitted on the transmission side (for example, Japanese Patent Application Laid-Open No. H11-27334).

[0010]

However, in such a conventional example, the frame synchronization pattern is detected after the phase is locked. For this reason, there are drawbacks that the detection time becomes long and the detection accuracy decreases.

The present invention solves such a problem in the prior art. Before the phase lock on the phase-modulated signal by the hierarchical transmission, the frame synchronization pattern in the phase-modulated signal (B-PSK) of the lowest speed transmission is obtained. It is an object of the present invention to provide a method and an apparatus for detecting a frame synchronization pattern by digitally demodulating a phase-modulated signal in hierarchical transmission in which the detection time can be reduced, the detection time is shortened, and the detection accuracy is improved. In this specification,
The lowest-speed transmission indicates a modulation method with a low required C / N ratio. For example, in the case of hierarchical transmission using 8-PSK and B-PSK, B-PSK is treated as the lowest-speed transmission. .

[0012]

In order to achieve the above object, a method for detecting a frame synchronization pattern by digitally demodulating a phase modulation signal in hierarchical transmission according to the present invention is to detect an input phase modulation signal. Digitally converting the I and Q signals, performing a complex multiplication of the I and Q signals and the reproduced carrier, outputting a phase difference signal from the complex operation output signal, Detecting the phase difference from the phase signal with a delay of one symbol, and outputting a detection signal indicating the phase modulation period of the lowest speed transmission obtained by calculating the cosine absolute value.

[0013] Further, as the phase modulation period detection of the lowest speed transmission, a step of delaying the phase difference signal by one symbol, a step of detecting a phase difference between the delayed signal and an output signal of complex multiplication, and a step of detecting the phase difference. Outputting a signal indicating the phase modulation period of the lowest speed transmission for which the cosine absolute value has been calculated, extracting the phase modulation period detection signal by removing other signals, and detecting the extracted phase modulation period. Averaging the signal in the frame direction.

Further, a step of generating a gate pulse based on the phase modulation period detection signal of the lowest speed transmission to perform carrier regeneration in the phase modulation period of the lowest speed transmission; Detecting a frame synchronization pattern based on the C / N ratio based on the output signal of the complex multiplication, and setting a threshold value for detecting the phase modulation period of the lowest speed transmission, The method includes a step of detecting the phase modulation period of the lowest speed transmission based on the phase detection signal without performing the carrier loop operation when performing reproduction, and any one or a combination of the above steps.

An apparatus for digitally demodulating a phase-modulated signal in hierarchical transmission and detecting a frame synchronization pattern according to the present invention is a device for digitally demodulating a phase-modulated signal in hierarchical transmission and detecting a frame synchronization pattern. Detection conversion means for digitally converting the I and Q signals obtained by detecting the phase-modulated signal, and complex multiplication means for performing a complex multiplication of the I and Q signals from the detection conversion means and the reproduced carrier;
Phase detecting means for outputting a phase difference signal from the output signal of the complex multiplying means, and the lowest speed transmission in which the phase difference signal from the phase detecting means is delayed by one symbol, the phase difference from the phase signal is detected, and the cosine absolute value is calculated. And a phase modulation period detecting means for outputting a detection signal indicating the period of the phase modulation.

Further, as the phase modulation period detecting means for the lowest speed transmission, a delay means for delaying the phase difference signal from the phase detecting means by one symbol, and a delay signal from the delay means and a phase signal from the complex multiplying means are used. A phase difference detecting means for detecting a phase difference, and a calculating means for outputting a phase modulation period detection signal of the lowest speed transmission obtained by calculating a cosine absolute value with respect to the phase difference from the phase difference detecting means are provided.

Further, the apparatus comprises filtering means for extracting the phase modulation period detection signal from the arithmetic means, and frame averaging means for averaging the phase modulation period detection signal from the filtering means in the frame direction.

Further, there is provided carrier reproducing means for generating a gate pulse based on the phase modulation period detection signal of the lowest speed transmission from the phase modulation period detecting means and reproducing the carrier in the phase modulation period of the lowest speed transmission. There is a configuration.

Further, the apparatus is provided with a detecting means for detecting a frame synchronization pattern based on a phase modulation period detection signal of the lowest speed transmission from the phase modulation period detecting means.

Further, there is provided C / N ratio detecting means for detecting a C / N ratio with respect to an output signal of the complex multiplying means.
The threshold value for detecting the phase modulation period of the lowest speed transmission by the phase modulation period detecting means is set in accordance with the C / N ratio obtained by the / N ratio detecting means.

Further, when the carrier regenerating means performs the carrier regenerating, the carrier regenerating means having the phase detecting means does not perform the carrier loop operation, and the carrier regenerating means performs the lowest speed transmission based on the phase detection signal of the phase detecting means. It is configured to detect a phase modulation period.

The method and apparatus for digitally demodulating a phase-modulated signal in hierarchical transmission and detecting a frame synchronization pattern according to the present invention are based on an output signal of a complex multiplication between a detected I and Q signal and a reproduced carrier. The phase difference signal is delayed by one symbol, the phase difference from the phase signal is detected, and the cosine absolute value is calculated, and a detection signal indicating the phase modulation period of the lowest speed transmission is output.

As a result, it is possible to detect the frame synchronization pattern in the phase modulation signal of the lowest speed transmission (for example, B-PSK) before the phase lock on the phase modulation signal by the hierarchical transmission, and the detection time is shortened. ,And,
The detection accuracy is improved.

In the present invention, the detection signal indicating the period of the phase modulation of the lowest speed transmission is filtered and extracted, and is averaged in the frame direction. Further, a gate pulse is generated based on the phase modulation period detection signal of the lowest speed transmission, and the carrier is reproduced in the phase modulation period of the lowest speed transmission.

As a result, noise of the phase modulation period detection signal is removed, and an error-free phase modulation period detection signal is generated. Further, carrier regeneration is easily and reliably performed.

In the present invention, the frame synchronization pattern is detected based on the phase modulation period detection signal of the lowest speed transmission. Further, a threshold value for detecting the phase modulation period of the lowest speed transmission is set in accordance with the C / N ratio detected from the output signal of the complex multiplication. Further, when performing carrier regeneration, the phase modulation period of the lowest speed transmission is detected based on the phase detection signal without performing the carrier loop operation.

As a result, a stable frame synchronization pattern can be detected during the phase modulation period of the lowest speed transmission. Further, even when the C / N ratio is low, the phase modulation period of the lowest speed transmission can be detected. Further, the detection time is shortened, and the operation configuration can be simplified.

[0028]

Next, a method and an apparatus for digitally demodulating a phase modulation signal in hierarchical transmission and detecting a frame synchronization pattern according to an embodiment of the present invention will be described with reference to the drawings. In the following text and figures, the same components as those in FIG. 3 described above are denoted by the same reference numerals.
FIG. 1 is a block diagram showing a configuration of a method and apparatus for digitally demodulating a phase modulation signal in hierarchical transmission and detecting a frame synchronization pattern according to an embodiment of the present invention.

In FIG. 1, an apparatus for digitally demodulating a phase modulation signal in this hierarchical transmission and detecting a frame synchronization pattern includes a phase modulation signal input terminal 1, an in-phase detector 2a, a quadrature detector 2b, a local An oscillator 3, a 90-degree phase shifter (shifter) 4, A / D converters 5a and 5b, a complex multiplier 6, roll-off filters 7a and 7b, a phase detector 8, a loop filter 9, Numerically controlled oscillator 10
, A data conversion circuit (SIN) 11, a data conversion circuit (CON) 12, and a frame synchronization pattern detection circuit 13.
, A timing pulse generation circuit 14, a C / N ratio detection circuit 15, an AND gate circuit 16, and a B-PSK period detection circuit 17.

FIG. 2 is a block diagram showing the internal configuration of the frame synchronization pattern detection circuit 13 in FIG. 2, the frame synchronization pattern detection circuit 13 is a delay circuit (for example, a D-type flip-flop (F / F) circuit)
18, a subtraction circuit 19, a COS operation circuit 20, an absolute value circuit 21, an LPF 22, and a frame averaging circuit 23
And

Next, the operation of this embodiment will be described. Here, B having different C / N ratios is used as hierarchical transmission.
-PSK (phase modulation signal of the lowest speed transmission), Q-PSK,
It is assumed that a PSK modulation signal based on time multiplexing, which combines 8-PSK modulation and is repeatedly transmitted for each frame, is received and demodulated.

The digital modulation signal input to the phase modulation signal input terminal 1 is distributed and input to the in-phase detector 2a and the quadrature detector 2b. A local oscillation signal (0-degree phase) from the local oscillator 3 is input to the in-phase detector 2a, and
The local oscillation signal shifted (shifted) by 90 degrees by the degree (π / 2) phase shifter 4 is input to the quadrature detector 2b, and a baseband signal by quadrature demodulation is output.

The baseband signals are converted into digital values by A / D converters 5a and 5b, respectively, and output to the complex multiplier 6. The output signal of the complex multiplier 6 is input to roll-off filters (digital low-pass filters) 7a and 7b, which form transmission characteristics required for preventing inter-symbol interference in digital data transmission, and generally generate transmission signals. Roll-off characteristics can be obtained when combined with the filter characteristics described above.

In the output signals of the roll-off filters 7a and 7b, each detection output is spectrally shaped so that the eye opening ratio becomes sufficiently large. The I and Q signals of the complex multiplier 6 and the output signals of the roll-off filters 7a and 7b are branched and clock recovery is performed, and symbol timing components in the signals are extracted and A / D converters 5a and 5b are output.
b and other circuits. The complex multiplier 6 is realized by an operation similar to that of a frequency converter (mixer) that generates an intermediate frequency.

The output signal of the complex multiplier 6 is input to roll-off filters 7a and 7, respectively. The output signals of the roll-off filters 7a and 7 are respectively input to the phase detector 8, and the phase difference between the input signal and the numerically controlled oscillator 10 is detected. The phase difference signal from the phase detector 8 is output to the frequency control terminal of the numerically controlled oscillator 10 through the loop filter 9 for carrier recovery.

The numerically controlled oscillator 10 is a cumulative addition circuit that does not inhibit overflow. That is, the operation is the same as that of a voltage controlled oscillator (VCO) in an analog circuit, the oscillation frequency is extremely stable, and the stability is higher than that of a VCXO using a quartz oscillator and a wide frequency variable range.

The output signal of the numerically controlled oscillator 10 is divided into two and input to data conversion circuits 11 and 12 having sine and cosine characteristics, respectively, and output from the data conversion circuits 11 and 12 to the complex multiplier 6. Is done. The configuration from the complex multiplier 6 to the data conversion circuits 11 and 12 is a digital phase locked loop (PLL).
Thus, carrier reproduction is performed by the digital PLL. On the other hand, the phase information detected by the phase detector 8 is input to the B-PSK period detection circuit 17, and the B-PSK modulation period is detected from the input phase information.

Next, the operation of the B-PSK modulation period detection circuit 17 will be described. 2, the phase information from the phase detector 8 includes the phase information of each data according to the symbol rate. This signal is a one symbol delay circuit 1
8 and a data delay of one symbol is performed. The signal delayed by one symbol in the delay circuit 18 and the phase signal input from the phase detector 8 are input to a subtraction circuit 19, where a difference operation is performed.

The difference signal from the subtraction circuit 19 indicates the respective phase differences of data between symbols. This phase difference is input to the COS operation circuit 20, where the phase value (angle) is input, and an output result in the range of "-1 to 1+" is obtained to perform the COS operation.

In the signal period of B-PSK, since this data is binary phase data, continuous symbol data is mapped to any one of 0 to 180 degrees in phase.

Therefore, by detecting the phase of the continuous symbol data in the delay circuit 18, the phase difference becomes 0 or 180 degrees during the period in which the B-PSK pattern is continuous. That is, the phase difference data is input to the COS operation circuit 20, and when the input is 0 degree, the value is "1".
Is output, and when the input has a phase difference of 180 degrees,
Output data of "-1" is obtained. Thus, B-PS
In the K period, it concentrates on "1 to -1".

In addition to the B-PSK modulation, mapping is performed at other than 0 ° and 180 °. In the case of Q-PSK modulation, mapping is performed at 45 degrees, 135 degrees, 225 degrees, and 315 degrees. In the case of 8-PSK modulation, 0 degree, 45 degrees
Degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270
Degrees and 315 degrees. Therefore, when an absolute value operation is performed on the output data of the COS operation circuit 20 by the absolute value circuit 21, a signal concentrated on "1" is obtained in the B-PSK period.

This signal is shaped by the LPF 22 and B-PS
A K period detection signal is obtained. Further, since the B-PSK period is at the same position in the frame time direction, the frame averaging circuit 23 in the frame direction enables more stable detection of the B-PSK period.

In FIG. 1, the B-PSK period signal from the BSPK period detection circuit 17 shown in FIG. 2 is input to the frame synchronization pattern detection circuit 13, where the frame synchronization pattern detection in the B-PSK period is performed. Will be Since the frame synchronization pattern detection is a fixed pattern, a pattern matching detection method or the like can be applied. In the C / N ratio detection circuit 15, the C / N ratio is calculated based on the input I and Q signals.
An N ratio is detected.

This C / N ratio is used for switching the modulated wave (B-PSK, Q-PSK, 8-PSK) of the hierarchically transmitted signal. Further, a threshold value for the B-PSK period detection of the B-PSK period detection circuit 17 is set. As a result, even when a signal with a low C / N ratio is input, the B-PSK period can be detected with high accuracy.

The frame synchronization pattern is B-PS
Since the data is transmitted by the K modulation, the accuracy of the frame synchronization pattern detection is improved by performing the frame synchronization pattern detection on the B-PSK period obtained as described above.
Also, once the frame synchronization pattern is detected, the B-PSK period hierarchically transmitted by this frame synchronization pattern can be accurately determined. That is, the transmitted B-PSK period detection signal is generated by the timing pulse generation circuit 14.

The B-PSK period detection signal (gate pulse signal) and the phase difference signal from the phase detector 8 are ANDed.
The signal is input to the gate circuit 16 and the AND output causes P
Control for LL is performed. That is, the loop filter 9 operates during the B-PSK period, and a stable PLL operation is performed even at a low C / N ratio.

The C / N ratio obtained by the C / N ratio detection circuit 15
When the / N ratio is good (high), PL during the B-PSK period
It is not necessary to operate L. In this case, the timing pulse generation circuit 14 can perform the control. In addition, since the B-PSK period detection circuit 17 can detect even when the PLL does not operate, if the B-PSK period can be detected in a state where the frame synchronization pattern detection circuit 13 is not phase locked. , An accurate B-PSK period can be detected before the operation of the PLL. As a result, the synchronization establishment time is reduced.

[0049]

As is apparent from the above description, according to the method and apparatus for digitally demodulating a phase-modulated signal in hierarchical transmission and detecting a frame synchronization pattern according to the present invention, the I and Q signals, the reproduced carrier, , The phase difference signal is delayed by one symbol from the output signal of the complex multiplication, the phase difference from the phase signal is detected, and the cosine absolute value is calculated, and a detection signal indicating the phase modulation period of the lowest speed transmission is output.

As a result, it is possible to detect the frame synchronization pattern in the phase modulation signal transmitted at the lowest speed before the phase lock on the phase modulation signal by the hierarchical transmission is performed, the detection time is shortened, and the detection accuracy is improved. I will be.

In the present invention, the detection signal indicating the phase modulation period of the lowest speed transmission is filtered and extracted, and is averaged in the frame direction, and further, based on the phase modulation period detection signal of the lowest speed transmission. Generate a gate pulse,
Carrier regeneration is performed during the phase modulation period of the lowest speed transmission.

As a result, noise of the phase modulation period detection signal is removed, and an error-free phase modulation period detection signal is generated. Further, carrier regeneration can be performed easily and reliably.

Further, in the present invention, a frame synchronization pattern is detected based on the phase modulation period detection signal of the lowest speed transmission,
Further, a threshold value for detecting the phase modulation period of the lowest speed transmission is set in accordance with the C / N ratio detected from the output signal of the complex multiplication. Further, when performing carrier regeneration, the phase modulation period of the lowest speed transmission is detected based on the phase detection signal without performing the carrier loop operation.

As a result, a stable frame synchronization pattern can be detected during the phase modulation period of the lowest speed transmission, and the phase modulation period of the lowest speed transmission can be detected even when the C / N ratio is low. . Further, the detection time is shortened, and the operation configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a method and apparatus for digitally demodulating a phase-modulated signal in hierarchical transmission and detecting a frame synchronization pattern according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a frame synchronization pattern detection circuit in FIG.

FIG. 3 is a block diagram showing a configuration of an apparatus for digitally demodulating a phase-modulated signal in hierarchical transmission using a conventional digital PLL carrier reproduction method and detecting a frame synchronization pattern.

[Explanation of symbols]

 2a In-phase detector 2b Quadrature detector 3 Local oscillator 4 90 degree (π / 2) phase shifter 5a, 5b A / D converter 6 Complex multiplier 7a, 7b Roll-off filter 8 Phase detector 9 Loop filter 10 Numerical control Oscillator (NCO) 11/12 Data conversion circuit (SIN / CON) 13 Frame synchronization pattern detection circuit 14 Timing pulse generation circuit 15 C / N ratio detection circuit 16 AND gate circuit 17 B-PSK period detection circuit 18 Delay circuit (D type) Flip-flop circuit) 19 subtraction circuit 20 COS operation circuit 21 absolute value circuit 22 LPF 23 frame averaging circuit

Claims (10)

[Claims] 1. A method for digitally demodulating a phase modulation signal in hierarchical transmission and detecting a frame synchronization pattern, comprising the steps of: digitally converting I and Q signals obtained by detecting an input phase modulation signal; Performing a complex multiplication of the signal and the reproduced carrier; then, outputting a phase difference signal from the complex operation output signal; delaying the phase difference signal by one symbol to detect a phase difference with the phase signal; Outputting a detection signal indicating a phase modulation period of the lowest-speed transmission obtained by calculating the cosine absolute value, and digitally demodulating the phase modulation signal in the hierarchical transmission to detect a frame synchronization pattern. 2. A phase modulation period for the lowest speed transmission, wherein a phase difference signal is delayed by one symbol, a phase difference between the delayed signal and a complex multiplication output signal is detected, Outputting a signal indicating the phase modulation period of the lowest speed transmission for which the cosine absolute value has been calculated, extracting the phase modulation period detection signal by removing other signals, and detecting the extracted phase modulation period. 2. The method according to claim 1, further comprising: averaging the signal in a frame direction, and digitally demodulating the phase modulation signal in the hierarchical transmission. 3. A step of generating a gate pulse based on the phase modulation period detection signal of the lowest speed transmission to perform carrier regeneration in the phase modulation period of the lowest speed transmission; Detecting a frame synchronization pattern based on the C / N ratio detected from the output signal of the complex multiplication, and setting a threshold value for detecting the phase modulation period of the lowest speed transmission; 2. The method according to claim 1, further comprising a step of detecting a phase modulation period of the lowest speed transmission based on the phase detection signal without performing a carrier loop operation when performing reproduction, and at least one of the above steps. A method for detecting a frame synchronization pattern by digitally demodulating a phase-modulated signal in hierarchical transmission according to the above. 4. An apparatus for digitally demodulating a phase modulation signal in hierarchical transmission and detecting a frame synchronization pattern, comprising: a detection conversion means for digitally converting I and Q signals obtained by detecting an input phase modulation signal; Complex multiplying means for performing complex multiplication of the I and Q signals from the converting means and the reproduced carrier; phase detecting means for outputting a phase difference signal from an output signal of the complex multiplying means; and a phase difference signal from the phase detecting means. And a phase modulation period detecting means for detecting a phase difference from the phase signal and calculating a cosine absolute value and outputting a detection signal indicating a period of phase modulation of the lowest speed transmission. An apparatus for digitally demodulating a phase modulation signal in hierarchical transmission and detecting a frame synchronization pattern. 5. A delay means for delaying the phase difference signal from the phase detection means by one symbol as the phase modulation period detection means for the lowest speed transmission, a delay signal from the delay means and a phase signal from the complex multiplication means. Phase difference detecting means for detecting a phase difference between the phase difference detecting means, and a calculating means for outputting a phase modulation period detection signal of the lowest speed transmission obtained by calculating a cosine absolute value with respect to the phase difference from the phase difference detecting means. The apparatus for detecting a frame synchronization pattern by digitally demodulating a phase modulated signal in hierarchical transmission according to claim 4. 6. A filtering unit for extracting a phase modulation period detection signal from the arithmetic unit, and a frame averaging unit for averaging the phase modulation period detection signal from the filtering unit in a frame direction. An apparatus for digitally demodulating a phase-modulated signal in hierarchical transmission according to claim 5, and detecting a frame synchronization pattern. 7. A carrier regenerating means for generating a gate pulse based on the phase modulation period detection signal of the lowest speed transmission from the phase modulation period detecting means and reproducing the carrier in the phase modulation period of the lowest speed transmission. 5. The apparatus for detecting a frame synchronization pattern by digitally demodulating a phase modulation signal in hierarchical transmission according to claim 4. 8. The hierarchical transmission according to claim 4, further comprising detecting means for detecting a frame synchronization pattern based on a phase modulation period detection signal of the lowest speed transmission from said phase modulation period detecting means. For digitally demodulating the phase-modulated signal in (1) and detecting a frame synchronization pattern. 9. A C signal for an output signal of said complex multiplying means.
C / N ratio detecting means for detecting the / N ratio, and detecting the phase modulation period of the lowest speed transmission in the phase modulation period detecting means corresponding to the C / N ratio obtained by the C / N ratio detecting means. The apparatus for detecting a frame synchronization pattern by digitally demodulating a phase-modulated signal in hierarchical transmission according to claim 4, wherein a threshold value for setting is set. 10. The method according to claim 1, wherein the carrier regenerating means does not perform a carrier loop operation in the carrier regenerating means provided with the phase detecting means when performing carrier regenerating, and transmits the lowest speed signal based on the phase detection signal of the phase detecting means. The apparatus for detecting a frame synchronization pattern by digitally demodulating a phase modulation signal in hierarchical transmission according to claim 4, wherein the phase modulation period is detected.