JP2001024624A - Device and method for generating and processing code group - Google Patents

Abstract

PROBLEM TO BE SOLVED: To periodically output a partial group and to control its phase by generating the partial group of a long period code group, setting its head pattern and its terminal pattern, generating a detecting signal, when the terminal end pattern is detected and executing initialization corresponding to the head pattern in a code group generating means whenever the detecting signal is generated. SOLUTION: A register control circuit 21 outputs a register initial value Bst corresponding to the bit pattern of a selector, where the initial value is set and a PN code generation generator 22 supplies a PN code to a mask processing circuit 23. A mask control circuit 25 selects a pattern MASKA, where the phase is deviated and a PN code processing generator 20 outputs the partial group as PN-OUT, which deviated from the PN code for the portion of a desired phase difference. The detecting signal is outputted when a terminal pattern detecting circuit 24 detects the terminal pattern, the mask control circuit 25 executes changeover into MASKB, where the phase is not deviated and the register control circuit 21 executes second register initial value setting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for generating a code sequence, and more particularly to generating a partial sequence for a code sequence such as a spread code sequence used for spread spectrum communication such as CDMA (code division multiple access). It can be applied when

[0002]

2. Description of the Related Art In a CDMA system, communication is performed with signals of different users superimposed on the same frequency for the same time. Therefore, the spreading code used in CDMA needs to be able to clearly identify users sharing time and frequency bands.

[0003] The degree of clarity of identification tends to increase as the maximum / minimum ratio of autocorrelation, which is the correlation between the same code sequences, becomes larger and the maximum value of the cross correlation, which is the correlation between different code sequences, becomes smaller. If the maximum value of the cross-correlation is large, mutual interference between users is likely to occur.

[0004] Spreading codes are also required to have as many code sequences as possible. This is because if the number of code sequences is small, the number of users sharing time and frequency bands is limited.

That is, randomness (pseudorandomness), periodicity, a large number of code sequences (code types), orthogonality, and the like are characteristics required for a spread code in a CDMA system.

Generally, a PN code is used in CDMA as a spreading code having such characteristics.

The PN code is a periodic code, but is called a PN, that is, a pseudo-noise code because it has a spectrum that can be regarded as white noise within a predetermined band.

The binary PN code of the PN code is M
The series and the gold series are typical. Gold sign is 2
Since the M-sequence is generated by combining two M-sequences of the same length, the M-sequence will be described here.

[0009] M-sequence on its configuration, 2 N 0 Some repetition period ^-1 (N-1) pieces but the subsequent portion with one 1, 2 ^N inserting the 0 on the following information of the partial The sign of the period is used. This makes it possible to provide a system with a simple circuit configuration and favorable processing.

As a method of changing the generation phase of the code, a mask processing technique is used. FIG. 2 shows a configuration example of a PN code generation circuit having 2 ^N -1 periods.

In FIG. 2, a PN code generation circuit 10
A code generation unit X and a mask processing circuit Y are provided.

The code generation unit X includes an N-stage shift register X
and _n-1 to X _0, with the EXOR (exclusive OR) circuit 1 to obtain input from the feedback taps between _{X 2} and _{X 1,} configuration and corresponding to the generation of the N-th order polynomial ^{X N + ... + X 3 +} X + 1 Has become.

On the other hand, the mask processing circuit Y includes a code generation section X
Circuit that performs phase control of the code generated in
and n two-input AND circuit _{n-1 ~AND 0,} and a EXOR circuit 2 XORing the outputs of all these AND circuits as input.

One input terminal of the AND _n-1 is connected between the shift registers _Xn-1 and _Xn-2 ,.
One input terminal of the AND ₂ is connected between the _{X 2} and _{X 1,} one input terminal of the AND ₁ is connected between the _{X 1} and _{X 0,} one input terminal of the AND ₀ is the _{X 0} Connected to output terminal.

Each of the other input terminals of AND _{n-1 to} AND ₀ is connected to each signal line of a bus B composed of n signal lines, and a mask process corresponding to an n-bit mask pattern MASK is performed. Will be

The amount of phase to be changed is controlled by the mask processing.

The shift register Xn-1 can be set by setting the start pattern of the code sequence anywhere in one cycle.
To X0 are determined.

[0018]

However, some CDMA systems use a PN code having a period that cannot be represented by 2 ^N -1 as described above. As an example, a code having a 3 × 2 ^N period is used. 2 to use
^In some cases, a partial sequence using a 3/4 cycle of an M sequence consisting of ^{(N + 2)} -1 cycles is generated.

The above-described PN code generation circuit 10 is a circuit for outputting one cycle of the M sequence,
It is not possible to output a subsequence of a sequence.

Therefore, a circuit which can output a partial sequence and can control the phase of the output partial sequence is required.

[0021]

According to a first aspect of the present invention, there is provided a code sequence generation processing apparatus for transmitting a partial sequence which is a partial sequence of a code sequence having a long cycle. Code sequence generating means for generating and outputting a code sequence; (2) pattern setting means for receiving settings of a leading pattern and a terminating pattern of the partial sequence; and (3) detecting the terminating pattern from the outputted code sequence. Termination pattern detection means for generating a detection signal when the
(4) initializing means for executing initialization corresponding to the leading pattern to the code sequence generating means when the detection signal is generated, and (5) initializing each time the detection signal is generated. The sub-sequence is periodically output by repeating the conversion.

According to a second aspect of the present invention, there is provided a code sequence generation processing method for transmitting a partial sequence which is a part of a long-period code sequence. Upon receiving the setting, (2) a detection signal is generated when the end pattern is detected from the output code sequence, and (3) when the detection signal is generated, an initial signal corresponding to the head pattern is generated. (4) The sub-sequence is periodically output by repeating initialization each time the detection signal is generated.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (A) Embodiment Hereinafter, an embodiment will be described with an example in which a code sequence generation processing apparatus and method according to the present invention is applied to a PN code generation processing circuit of a CDMA system.

(A-1) Configuration of the Embodiment FIG. 1 shows a PN code generation processing circuit 20 of the present embodiment.
The PN code generation processing circuit 20 is included in a receiver such as a CDMA mobile phone and a base station as a part of a synchronization acquisition unit and a synchronization tracking unit and is used for despreading. In a transmitting device such as a telephone, it can be included as a part of a spread modulation unit.

In FIG. 1, a PN code generation processing circuit 20
Is a register control circuit 21, a PN code generator 22,
A mask processing circuit 23, an end pattern detection circuit 24,
And a mask control circuit 25.

The register control circuit 21 provides a PN code generator 22 having a structure corresponding to an N-th order
This is a control circuit for performing initial setting of the next register value and the like.

Circuits 21 to 25 such as PN code generator 22
FIG. 3 shows an example of the detailed configuration of.

In FIG. 3, the PN code generator 22 outputs X
This is a circuit having the same function as that of the code generation unit X, which includes n (n stages) 1-bit shift registers n-1 to X0 and an EXOR circuit 3. However, in the PN code generator 22, the connection between the shift registers is performed via the selector SEL.

That is, each of the shift registers Xn-1 to Xn-1
The output terminals of the selectors SELn-1 to SELn-0 are connected to the 0 input terminal.

Each of the selectors SELn-1 to SELn-0 switches selection in accordance with a control signal CS1 supplied to its control input terminal. The selection switching is performed between the value of each previous-stage shift register or the register initial value Bst.

The register initial value Bst is a predetermined n-bit bit pattern supplied from the register control circuit 21 through n signal lines.

The register control circuit 21 sets the initial value of the register when a start trigger (STA TRIG) is supplied. However, even when an end pattern detection signal GS described later is generated, the same as when the start trigger is supplied. Repeat the register initial value setting operation.

Another control signal output from the register control circuit 21 is a mask control signal MC supplied to the mask control circuit 25. The mask control circuit 25, which receives the supply of MC at the control input terminal, is a selector circuit of two inputs and one output, and two types of mask patterns MASKA and MASKB according to the detection signal GS output from the MC or the end pattern detection circuit 24. Switch the selection.

MASKA is a pattern for shifting the phase of the partial sequence, and MASKB is a pattern for sending the partial sequence without shifting the phase. The MASK
B is used to transmit a subsequence to which a phase difference has already been added, from the first bit, as described later.

The output of the mask control circuit 25 is supplied to a mask processing circuit 23. The mask processing circuit 23 may have a configuration such as the mask processing circuit Y composed of, for example, AND or EXOR, and is a circuit that performs different mask processing according to the output of the mask control circuit 25.

An end pattern detection circuit 24 monitoring the output of the mask processing circuit 23 is a circuit for detecting an end pattern Bend which is a bit pattern at the end of a predetermined partial series.

The configuration of the end pattern detection circuit 24 may include, for example, a shift register composed of N stages and a comparison circuit for comparing N bits of these shift registers with the end pattern Bend.

When the end pattern is detected, the comparison circuit of the end pattern detection circuit 24 generates the detection signal GS and causes the mask control circuit 25 to select between MASKA and MASKB.

The PN code 1 having one cycle from A0 to AX shown in FIG. 4A is a long-period code sequence corresponding to the N-th generation polynomial specified by the structure of the PN code generator 22. The same figure consisting of a series of one continuous part of the PN code 1
The first bit of the subsequence (PN code 2) of (B) is B0
Assuming that the last bit is B1, the register initial value Bst is a pattern corresponding to the bit pattern immediately after the head B0.

An end pattern Bend, which is a bit pattern from B1-N to B1 immediately before B1, specifies the end of the subsequence.

In general, the set of Bst and Bend is P
One subsequence is specified from a plurality of subsequences that can be extracted from the N code 1. In the present embodiment, a partial sequence (PN code 2) having B0 to B1 as one cycle is considered.

In FIG. 1, MASKA and STA TR
IG is a parameter supplied from outside the PN code generation processing circuit 20.

The operation of this embodiment having the above configuration will be described below.

(A-2) Operation of the Embodiment When a start trigger is supplied to the register control circuit 21 and the PN code generation processing circuit 20 starts operating, first, the selectors SELn-1 to SELn-0 set the register initial values by the control signal SC. Set on the setting side.

The register control circuit 21 determines that B0 to B0 +
By outputting the register initial value Bst corresponding to N, the initial register initial value setting is performed, and the partial sequence (PN code 2) shown in FIG. 23.

At this time, the mask processing circuit 25
MAS in the operating state between points C and D1 in (C)
Since KA is selected, as shown in FIG. 5B, a partial sequence having a phase shifted from the PN code 2 by a desired phase difference PX, that is, a PN code 3 is used as the output PN OUT of the PN code generation processing circuit 20. Sent out. In this process, in the state shown in the figure, the leading part of the first cycle of the partial sequence 3 has been lost.

In FIG. 5C, when the end pattern Bend1 before the point D1 is detected, the end pattern detection circuit 24 supplies the detection signal GS to the register control circuit 21 and selects the mask control circuit 25 by MASKB.
Switch to

Therefore, the register control circuit 21 sets the register initial value (Bst) for the second time at the timing when the detection signal GS is received.

The timing at which the second register initial value setting is performed reflects the phase difference PX.

After the point D1, the mask control circuit 25 returns to the point D
MASKB even if the detection signal GS is generated at 2, D3, etc.
Is continued, the phase difference does not change from the PX, and the timing of setting the register initial value after the third time corresponds to the phase difference PX.

That is, the partial sequence of the phase difference PX is continuously transmitted from the PN code generation processing circuit 20 repeatedly as compared with the PN code 2 in FIG.

Therefore, in the repetition after D1, D
Subsequence in 1, D2, D3, etc. (PN code 2)
To which a phase difference PX is given (PN code 3)
Can be output from the first bit.

In this embodiment, the PN code 1 of FIG. 4A having a long cycle is set by setting the Bst and Bend.
Not only can a desired part be extracted from the subsequence to be a partial sequence, but also a desired phase difference can be given to the partial sequence.

The above-described mask pattern MASK
A, MASKB and the phase difference PX will be described with reference to FIGS. 6 and 7 in order to clarify the relationship.

This is a system used in an IS-95 system standardized by TIA (Telecommunications Industry Association of America) and the like.

(A-2-1) Relationship between Mask Pattern and Phase Difference In FIG. 6, a portion related to the setting of the phase difference of the PN code generation processing circuit 20 is shown in a simplified manner.
0 is a mask processing unit 31, a mask pattern unit 32,
It comprises a PN code generator 33.

The mask processing section 31 corresponding to the mask processing circuit 23 has four two-input AND circuits AND3 to AND3.
D0 and a modulo 2 adder.

The mask pattern section 32 for supplying a 4-bit mask pattern to the AND circuit has four mask patterns M3 to M0.
It consists of two independent 1-bit registers.

A PN code generator 33 corresponding to the PN code generator 22 is composed of a four-stage shift register X3 to X0 and EXOR4, and generates a generator polynomial g (X).
= X4 + X3 + X2 + 1.

At the left end of FIG. 7, shift registers X3 to X
In the state of 0, the output of the modulo 2 adder is shown at the center, and the output of the phase difference processor 30 is shown at the right end in a register expression corresponding to the mask pattern.

X0 of the mask pattern corresponds to a mask pattern in which only M0 is 1 and M3 to M1 are 0. In mask pattern X1, only M1 is 1 and M3, M2, M
0 corresponds to a mask pattern of 0.

Assuming that the phase difference for the mask pattern X0 is 0, the phase difference for the mask pattern X1 is 1 and the phase difference for the mask pattern X2 is 2.

X4 = X1 + X0 means that to set the phase difference 4, 1 is supplied to M1 and M0,
3 indicates that 0 is supplied to M2.

Finally, X15 (= X12 + X11 = X3
+ X1 + X2 + X0 + X3 + X2 + X1) = X0, and the circuit returns to the state without a phase difference.

In relation to the present embodiment, X in FIG.
0 corresponds to the MASKB, the MA
SKA is determined by the X1 to X1 according to a desired phase difference PX.
4 corresponds to one pattern selected from the four patterns.

(A-3) Effects of Embodiment As described above, according to this embodiment, a desired partial sequence can be extracted from a PN code sequence having a long cycle corresponding to the shape of a PN code generator. Further, a desired phase difference can be set for the partial sequence.

(B) Other Embodiments In the above description, the phase difference is given to the partial series using the mask pattern. However, the initial phase or the phase of each shift register at a certain point in time after n shifts from each shift register is added. A desired phase difference can be provided by calculating a value and resetting the obtained value in each shift register.

In the above embodiment, CDMA has been described. However, the present invention can be applied to spread spectrum communication other than CDMA.

Further, the code sequence and the partial sequence of the present invention may be used for applications other than spread spectrum.

Although the above embodiment uses hardware, the present invention can also be realized using software.

That is, the present invention can be widely applied to a code sequence generation processing apparatus and method for transmitting a partial sequence which is a partial sequence of a code sequence having a long cycle.

[0072]

As described above in detail, according to the present invention, a partial sequence of a code sequence can be generated and output.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a configuration of a PN code generation processing circuit according to an embodiment.

FIG. 2 is a schematic diagram showing a configuration of a conventional PN code generation processing circuit.

FIG. 3 is a schematic diagram illustrating a detailed configuration example of a PN code generation processing circuit according to the embodiment;

FIG. 4 is a schematic explanatory diagram showing a relationship between a long-period PN code and a partial sequence thereof.

FIG. 5 is a time chart illustrating a timing relationship between a partial sequence, a phase difference, and mask processing.

FIG. 6 is a simplified configuration diagram for explaining the relationship between the applied phase difference and the mask pattern.

FIG. 7 is a schematic diagram showing a relationship between a phase difference to be applied and a mask pattern.

[Explanation of symbols]

10, 20 PN code generation processing circuit, 21 register control circuit, 22 PN code generator, 23 mask processing circuit, 24 end pattern detection circuit, 25 mask control circuit, Xn-1 to X0 shift register , Bst: register initial value, Bend: end pattern, MC: mask control signal, CS1: control signal, GS: detection signal.

Claims (3)

[Claims] 1. A code sequence generation processing device for transmitting a partial sequence which is a part of a sequence of a code sequence having a long period, comprising: a code sequence generating means for generating and outputting the code sequence; Pattern setting means for receiving an end pattern setting; end pattern detection means for generating a detection signal when the end pattern is detected from the output code sequence; and when the detection signal is generated, the head pattern Initialization means for performing initialization corresponding to the above-mentioned code sequence generation means, and repeating the initialization every time the detection signal is generated, thereby periodically outputting the partial sequence. Code sequence generation processing device. 2. The code sequence generation processing device according to claim 1, further comprising: a phase difference providing unit that provides a phase difference to the partial sequence, wherein the phase difference providing unit includes: The phase difference is set, and the termination pattern of the subsequence after the phase difference is set is detected by the termination pattern detection means.In the next and subsequent cycles, the phase difference is not set and the termination pattern detection means A code sequence generation processing device characterized in that a partial sequence to which a phase difference is added is periodically output by detecting an end pattern. 3. A code sequence generation processing method for transmitting a partial sequence which is a partial sequence of a long-period code sequence, comprising: setting a leading pattern and a terminating pattern of said partial sequence in advance; A detection signal is generated when the end pattern is detected from the code sequence, and when the detection signal is generated, initialization corresponding to the head pattern is performed on the code sequence, and the detection signal is generated. A code sequence generation processing method characterized in that the partial sequence is periodically output by repeating initialization every time the code is generated.