JP2001023379A - Associative storing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to compare data of variable length by providing plural entry having flip-flop storing compared result of entry of which an address is lower by one and a circuit in which product of an output of a flip- flop and compared result of a comparator becomes the compared result of entry. SOLUTION: Plural entry are provided with entry result circuits 14. A flip-flop 23 latches compared result of an entry match line 17 at timing at which a word line WL is made to L from H, and stores compared result of entry of which an address in comparing operation performed in the latest is lower by one. A combination circuit 19 outputs H to an entry match line 74 when comparison result in entry of which the address is lower by one and the present comparison result 72 match with each other in the latest comparison operation, a sequence signal terminal is at L, and the present comparison operation is continuous comparison of the entry.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage circuit, and more particularly to an associative storage circuit for inputting data and outputting a result as to whether the same or plural words exist or not.

[0002]

2. Description of the Related Art FIG.
o Devices CMOS Memory Pro
ducts 1991 Data Book / Hand
FIG. 4 is a configuration diagram of a conventional associative memory circuit shown in “book”, p5-4. In the figure, 49 is an associative memory circuit, 50
Is a comparison register for storing comparison data; 52 is a plurality of entries of the associative memory circuit 49; 53 is a command register for storing a command from the outside to the associative memory circuit 49;
Reference numeral 4 denotes a status register that stores the state of the associative memory circuit 49, and reference numeral 55 denotes a CAM register that reads data stored in the associative memory circuit 49.

Reference numeral 68 denotes a chip enable signal terminal for inputting an external chip enable signal indicating that access to the associative memory circuit 49 is being performed, and 66 denotes an associative memory circuit 49 when the chip enable signal is valid. A write enable signal terminal for inputting a write enable signal instructing that the access is a write operation;
Reference numeral 7 denotes an output enable signal terminal for inputting an output enable signal indicating that access to the associative memory circuit 49 is a read operation of a register in the associative memory circuit when the chip enable signal is valid;
Reference numeral 5 denotes a data / command select signal terminal for inputting a data / command select signal indicating whether the access is a command or data when the chip enable signal is valid; 62, an external output signal terminal; Is a data bus signal terminal.

[0004] 69 is a chip enable signal terminal 68,
This is an I / O control circuit that controls input and output to and from the outside by signals input to a write enable signal terminal 66, an output enable signal terminal 67, and a data / command select signal terminal 65. Reference numeral 56 denotes a CAM result circuit that updates the contents of the status register 54 based on the comparison results from all the entries 52 in the associative memory circuit 49, and generates and outputs a match signal to an output signal terminal 62.

The above-mentioned entry 52 includes a compared register 57 storing data to be compared and a compared register 57.
A comparator 58 for comparing the data of the comparator 50 with the data of the comparison register 50, a comparator match line 72 for notifying the comparison result of the comparator 58, and information indicating the state of the entry, and the data stored in the compared register 57. And an entry result circuit 59 for generating a comparison result of the entry based on the comparison result of the comparator 58 and the information of the empty bit 61.

Reference numeral 74 denotes an entry match line for notifying the CAM result circuit 56 of the comparison result of the entry 52;
Numeral 1 denotes a data bus connecting between each register in the associative memory circuit 49 and the data bus signal terminal 64, and 73 denotes a comparison register 50 and a compared register 57 in each entry 52.
And a comparison bus for connecting the comparator 58.

A plurality of entries 52 exist in the associative memory circuit 49, and the addresses are assigned in ascending order from # 0. In the illustrated example, the size of the compared register 57, the comparison register 50 and the CAM register 55 is 48 bits,
The comparison data size is 48 bits and the command register 5
3 and the size of the status register 54 are 16 bits,
The number of entries in the associative memory circuit 49 is 256.
These values can be changed relatively or independently.

FIG. 16 shows, for example, Japanese Patent Application Laid-Open No. HEI 3-13897.
FIG. 1 is a configuration diagram of a CAM cell stored in Japanese Unexamined Patent Publication (Kokai) No. H10-26095. FIG.
One CAM cell shows a 1-bit circuit configuration of the compared register 57 and the comparator 58 in FIG. Therefore, the size of the compared register 57 is 48
If it is a bit, there are 48 CAM cells in one entry 52.

In FIG. 16, CC is a CAM cell, WL
Is a word line indicating that the entry 52 is selected, BL
Is a true bit line existing for each bit of the compared register 57 and the comparator 58, _BL is a complement bit line which is a complement of the true bit line BL, and RL is a comparator circuit COM for comparing data in the memory cell MC. True-value compared data line to communicate to
_RL is a complement value compared data line that is a complement value of the true value comparison data line RL.

TW1 and TW2 are transfer transistors, Tr1, Tr2, Tr3 and Tr4 are transistors,
Tp is a precharge transistor, Φ is a control signal for controlling Tp, MC is a memory cell storing one bit of data to be compared, ML is a match line indicating the comparison result of the CAM cell CC, and D is a signal of the match line. COM is a comparison circuit that determines whether the data to be compared in the memory cell MC matches the comparison data of the bit lines BL and _BL, and SC is a storage cell composed of the memory cell MC and the transistors TW1 and TW2. It is.

The output of the driver D output to the match line ML corresponds to the comparator match line 72 in FIG. The transistors in the figure are N-channel transistors.

FIG. 17 is a block diagram of the entry result circuit 59 shown in the publication p5-8. In FIG.
75 is a combination circuit, and 84 is an output line of the empty bit 61.

When the value of the empty bit 61 is "1", no data is stored in the to-be-compared register 57 in the entry 52, and the output from the output line 84 is "High" (hereinafter referred to as "High"). , “H”).
When the value of the empty bit 61 is “0”, data is stored in the compared register 57, and the output from the output line 84 is “Low” (hereinafter abbreviated as “L”).

The combination circuit 75 has an empty bit 61
Is a circuit in which the value of the entry match line 74 becomes "H" only when the output from the output line 84 is "L" and the value of the comparator match line 72 is "H". The value of the empty bit 61 is set to “0” when data is stored in the compared register 57. Also, it is set to “0” or “1” by the setting of the command register 53.

FIG. 18 is a configuration diagram of the CAM result circuit 56 of FIG. In the figure, 78 is a driver, 81 is a control signal for controlling the gate of the precharge transistor 82, 79 is a match line, 77 is a priority encoder line for encoding and outputting 256 input signals into 8 signals, 76 is an entry A match circuit corresponding to 52 is formed by a transistor 80. The transistors in the figure are channel transistors.

The priority encoder line 77 is 2
Priority is set for 56 input signals, and entry 52
The smaller the address, the higher the priority. Therefore, when the plurality of entry match lines 74 become “H”, the address of the entry 52 having the higher priority is written into the status register 54.

Next, the operation will be described.

First, the memory cell MC in the CAM cell CC
The operation when data is written to the memory will be described. After a potential of “H” is applied to the true value bit line BL, a potential of “L” is applied to the complementary bit line _BL, and a potential of “H” is applied to the word line WL, the potential of the word line WL is set to “L”. " As a result, the point a is held at the “H” potential and the point b is held at the “L” potential. This state is referred to as a state in which “1” data is written in the memory cell MC. In this state, the transistor Tr1 is off and the transistor Tr2 is on.

On the other hand, an "L" potential is applied to the true bit line BL, an "H" potential is applied to the complementary bit line _BL, and an "H" potential is applied to the word line WL. Is set to “L”. As a result, the point a is held at the “L” potential and the point b is held at the “H” potential. This state is referred to as a state in which “O” data is written in the memory cell MC. In this state, the transistor Tr1 turns on,
The transistor Tr2 is off.

Next, an operation for comparing data stored in each CAM cell CC will be described. In the following description, it is assumed that data “1” is stored and held in the memory cell MC of the CAM cell CC to be compared. First, when a control signal Φ of “H” is applied to the gate of the precharge transistor Tp shown in FIG. 16 for a predetermined time,
The precharge transistor Tp is turned on, and the match line ML is precharged. Next, bit line B
Data to be compared with L and _BL is input.

Assume that "0" is given as the comparison data. That is, assuming that a "L" potential is applied to the true bit line BL and an "H" potential is applied to the complementary bit line _BL, the transistor Tr3 is turned off and the transistor Tr4 is turned on. Therefore, the transistor Tr
2. The precharge of the match line ML is extracted to the ground line as a reference potential source via Tr4.

On the other hand, assume that "1" is given as comparison data. That is, assuming that a "H" potential is applied to the true bit line BL and an "L" potential is applied to the complementary bit line _BL, the transistor Tr3 is turned on and the transistor Tr4 is turned off. Therefore, other CAM cells C
Assuming that the compared data of the C memory cell MC also matches the comparison data, the potential of the match line ML is held.

As described above, when the data to be compared of the memory cell MC and the comparison data given via the bit lines BL and _BL do not match, the potential of the match line ML becomes the ground potential, and conversely, they become If they match, the potential of the match line ML is maintained at the precharge potential. Then, the potential of the match line ML is input to the driver D, and is output to the comparator match line 72 as a comparison result. This operation is the same when the data “0” is stored in the memory cell MC of the CAM cell CC to be compared.

Next, the entry result circuit 5 shown in FIG.
9 will be described. In the entry result circuit 59, the comparator match line 72 and the empty bit 61
Are determined, and an output to the entry match line 74 is generated. As described above, when the compared data and the comparison data match, the comparator match line 72 is set to “H”.
And "L" when they do not match. If the empty bit 61 is set to “1”, the entry 5
"H" is output to indicate that 2 is empty,
When set to “O”, this indicates that the compared data is set in the compared register 57 in the entry 52, and “L” is output. The combination circuit 75 outputs “H” to the entry match line 74 only when the input condition is that the comparator match line 72 is “H” and the output 84 of the empty bit 61 is “L”. Under other conditions, “L” is output.

Next, the CAM result circuit 56 shown in FIG.
The operation of will be described. Precharge transistor 8
The control signal 81 of “H” is applied to the gate 2 for a predetermined time. Thereby, the precharge transistor 8
2 is turned on, and the match line ML is precharged. The result of comparison at each entry 52 is input to the match circuit 76 through an entry match line 74, and the value controls on / off of the transistor 80.

When the entry match line 74 becomes "H", the transistor 80 is turned on, and the precharge of the match line 79 is drawn to the ground line as a reference potential source. When the entry match line 74 becomes “L”, the transistor 80 is turned off, and the entry match line 74 is
Is "L", the potential of the match line 79 is held. The potential of the match line 79 is input to the driver 78 and output to the match signal 62 as a comparison result.
When the comparison result at the entry 52 matches, the potential of the match signal 62 becomes “L”, and when it does not match, it becomes “H”.

The output of the entry match line 74 is also input to the priority encoder 56. Each entry match line 74 has a priority from 0 to 255, with 0 being the highest priority. Accordingly, the priority is higher for the entry match line 74 corresponding to the entry 52 having the smaller address. In the priority encoder 56, the entry match line 7 whose potential is "H"
4, the highest priority is selected, and the address of the entry 52 corresponding to the highest priority is coded into 8-bit data and output. The 8-bit data is stored in the status register 54 and can be read from the outside.

As prior art related to the present invention, for example, JP-A-63-31091 and JP-A-63-2103
Japanese Patent Application Laid-Open Nos. 44496, 3-113897, 4-21997 and 4-271094 disclose such methods.

[0029]

Since the conventional associative memory circuit is constructed as described above, the lengths of the comparison data and the data to be compared are fixed, and data longer than the lengths cannot be compared. .

An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide an associative memory circuit capable of comparing variable-length data.

[0031]

According to the first aspect of the present invention, there is provided an associative memory circuit, comprising: a terminal for inputting a sequence signal from the outside; a plurality of entries having a flip-flop for storing a comparison result of an entry having a youngest address; A circuit is provided which uses the product of the output of the flip-flop and the comparison result of the comparator when the input sequence signal is valid as the comparison result of the entry.

[0032]

The associative memory circuit according to the first aspect of the present invention stores the comparison result of the entry having the next smallest address in the last comparison operation, and stores the information in the entry comparison result circuit. This can be used as a condition for determination.

[0033]

Embodiment 1 "Comparison of size" An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of an associative memory circuit 1 showing an embodiment of the present invention. In FIG. 1, reference numeral 5 denotes a plurality of entries provided in the associative memory circuit 1, and reference numeral 6 denotes a size of data provided in each entry 5. FIG. 15 is a comparator for comparing
Is the same as that of the conventional associative memory circuit shown in FIG.

FIG. 2 is a configuration diagram of the comparator 6 shown in FIG. In FIG. 2, CON11 to CON33 are comparison circuits for determining whether data to be compared in the memory cell MC matches comparison data of the bit lines BL and _BL, and RL is for transmitting data in the memory cell MC to the comparison circuit CON. _RL is the true value compared data line RL
ML1 to ML3 are match lines, SC1 to SC3 are storage cells, and BL1 to BL
3 is a true value bit line, and _BL1 to _BL3 are complementary value bit lines.

FIG. 3 is a configuration diagram of the comparator 6 in the associative memory circuit 1, which detects that the value of the compared data in the compared register 57 is smaller than the value of the compared data in the comparison register 50. In FIG. 3, Trk is a transistor,
ML is a match line, Ca is a combinational circuit, LML is a little line which is the output of the combinational circuit Ca, RML
Is a mismatch line, and DI is an inverter having a signal inversion function.

FIG. 4 is a block diagram of a comparator in the associative memory circuit 1 for detecting that the data to be compared in the register to be compared 57 is smaller than the comparison data in the comparison register 50. Are denoted by the same reference numerals, and duplicate description is omitted.

FIG. 5 shows the relationship between the input and output signals of the combinational circuit Ca used in FIGS. 3 and 4. The little line LML becomes "H" only when the input match line ML is "H", the true value bit line BL is "H", and the true value compared data line RL is "L". The line LML becomes "L". “×” in the figure
Indicates “L” or “H”.

FIG. 6 is a configuration diagram of the comparator 6 in the associative memory circuit 1 for detecting that the value of the compared data in the compared register 57 is larger than the value of the comparison data in the comparison register 50. In FIG. 6, Cb is a combinational circuit,
BML is a big line which is an output of the combinational circuit Cb.

FIG. 7 is a block diagram of a comparator in the associative memory circuit 1 for detecting that the data to be compared in the register to be compared 57 is greater than or equal to the comparison data in the comparison register 50. Are denoted by the same reference numerals, and duplicate description is omitted.

FIG. 8 shows the relationship between the input and output signals of the combinational circuit Cb used in FIGS. 6 and 7. The big line BML becomes "H" only when the input match line ML is "H", the true value bit line BL is "L", and the true value compared data line RL is "H". The line BML becomes “L”.

Next, the operation will be described. The operation of the first embodiment of the data size comparison shown in FIG. 1 will be described with reference to FIG. 2, FIG. 3, FIG. 4, FIG. 6, and FIG. And the comparison of the above.

The data to be compared is a comparison register 5
0 or stored in the compared register 57. In these registers 50 and 57, data is represented by bit strings. The data is a positive integer, and the most significant bit in determining the size of the data in the bit string is MS
B, let the least significant bit be LSB. Bits closer to the MSB in the bit string are upper bits, and LSBs are
Are the lower bits.

In FIG. 2, the MSB value of the data to be compared is stored in storage cell SC3, and LSB is stored in storage cell SC1.
Is stored. As shown in the related art, a comparison result of all bits of the comparison data and the data to be compared is output as a signal to the match line ML1.
Comparison is performed in the comparison circuits CON13, CON12, and CON11, and the comparison result of each bit is output to the match line ML1. When the level of the match line ML1 is "H", it indicates that the comparison data and the data to be compared match, and when it is "L", it indicates that they do not match.

Similarly, the comparison circuits CON23 and CON22 output a comparison result of the upper two bits excluding the least significant bit to the match line ML2. Similarly, the comparison circuit CON33 outputs the comparison result of the most significant bit excluding the lower two bits to the match line ML3. FIG.
Has shown the configuration of three bits, but the same operation is performed when the number of bits changes.

FIG. 3 is a block diagram of the comparator 6 for detecting that the compared data in the compared register 57 is smaller than the comparison data in the comparison register 50. In the drawing, the value of the LSB of the data to be compared is held in the rightmost storage cell SC, and the leftmost storage cell SC has higher bits. The combination circuit Ca exists corresponding to the storage cell SC, and one combination circuit exists for each bit. Each combination circuit Ca
As described with reference to FIG. 2, the comparison result of the higher order bit is output from the combinational circuit Ca to the match line ML which is the input to.

As shown in FIG. 5, in the combinational circuit Ca, when the input match line ML is "H", the true value bit line BL is "H", and the true value comparison data line RL is "L". Only the little line LML becomes “H”.
In other words, the little line LML is set to "H" only when the upper bits of the comparison data and the data to be compared match and all the bits corresponding to the combinational circuit Ca are larger than the comparison data. Under other conditions, the little line LML becomes "L".

The precharge transistor Tp shown in FIG.
Is supplied with a control signal .phi. Of "H" for a predetermined time, the precharge transistor Tp is turned on, and the mismatch line RML is precharged. When the little line LML serving as the gate of the transistor Trk becomes “H”, the transistor Trk turns on. At that time, the precharge of the mismatch line RML is pulled out to the ground line as the reference potential source via the transistor Trk, and becomes the “L” level.

On the other hand, all the little lines LML are "L".
At this time, all the corresponding transistors Trk are turned off. Therefore, the potential of the mismatch line RML is maintained at “H”. The signal on the mismatch line RML is inverted by the inverter DI and output to the comparator match line 72. Under the above conditions, if the value of the compared data in the compared register 57 is smaller than the value of the comparison data in the comparison register 50, “H” is output to the comparator match line 72, and otherwise “L”. Is output.

FIG. 4 is a block diagram of the comparator 6 for detecting that the compared data in the compared register 57 is equal to or smaller than the comparison data in the comparison register 50.
Is added with a circuit for detecting the coincidence of all the bits. The comparison result in this circuit is the match line ML
And the match line ML is set to “H” when the comparison data and the compared data match, and is set to “L” when they do not match.
Becomes This match line ML is connected to the gate of the transistor Trk, and when the match line ML becomes “H”, the transistor Trk turns on. At that time, the precharge of the mismatch line RML is pulled out to the ground line as the reference potential source via the transistor Trk, and becomes the “L” level. Under the above conditions, when the compared data in the compared register 57 is equal to or smaller than the comparison data in the comparison register 50, “H” is output to the comparator match line 72,
At other times, “L” is output.

FIG. 6 is a block diagram of the comparator 6 for detecting that the compared data in the compared register 57 has a larger value than the comparison data in the comparison register 50. The combination circuit Cb exists corresponding to the storage cell SC, and one combination circuit exists for each bit. As described with reference to FIG. 2, the comparison result of the higher-order bits from the combination circuit Cb is output to the match line ML that is an input to each combination circuit Cb.

As shown in FIG. 8, in the combination circuit Cb, when the input match line ML is "H", the true value bit line BL is "L", and the true value comparison data line RL is "H". Only the big line BML becomes “H”.
In other words, the big line BML becomes “H” only when the upper bits of the comparison data and the data to be compared coincide with each other and the data to be compared is large when only the bits corresponding to the combinational circuit Cb are compared. Under other conditions, the big line BML becomes “L”.

The precharge transistor Tp shown in FIG.
Is supplied with a control signal .phi. Of "H" for a predetermined time. Thereby, the precharge transistor Tp
Is turned on, and the unmatched line RML is precharged. Big line B to be the gate of transistor Trk
When ML becomes “H”, the transistor Trk turns on. At that time, the mismatch line RM is connected via the transistor Trk.
The precharge of L is drawn to the ground line as the reference potential source, and becomes "L" level.

On the other hand, all the big lines BML are "L".
At this time, all the corresponding transistors Trk are turned off. Therefore, the potential of the mismatch line RML is maintained at “H”. The signal on the mismatch line RML is inverted by the inverter DI and output to the comparator match line 72. Under the above conditions, “H” is output to the comparator match line 72 when the value of the compared data in the compared register 57 is larger than the value of the comparison data in the comparison register 50, and otherwise “L”. Is output.

FIG. 7 is a block diagram of the comparator 6 for detecting that the compared data in the compared register 57 is equal to or larger than the comparison data in the comparison register 50.
Is added with a circuit for detecting the coincidence of all the bits. The comparison result in this circuit is the match line ML
And the match line ML is set to “H” when the comparison data and the compared data match, and is set to “L” when they do not match.
Becomes

This match line ML is a transistor Tr
k and the match line ML is “H”
, The transistor Trk turns on. At that time, the precharge of the mismatch line RML is pulled out to the ground line as the reference potential source via the transistor Trk, and becomes the “L” level. Under the above conditions, "H" is output to the comparator match line 72 when the compared data in the compared register 57 is equal to or larger than the comparison data in the comparison register 50, and "L" is output otherwise. You.

As described above, the comparator 6 in FIG. 1 compares the size of the comparison data with the data to be compared, and outputs the result to the comparator match line 72. Operations other than the above are the same as those of the conventional associative memory circuit 49 shown in FIG.

Embodiment 2 "Timer" FIG. 9 is a configuration diagram of an associative memory circuit 2 showing Embodiment 2 of the present invention. In FIG. 9, reference numeral 7 denotes a plurality of entries provided in the associative memory circuit 2, 8 denotes an empty bit provided in each entry 7, 10 denotes an initial value register for holding a timer interval as a value, and 47 denotes an external clock signal. Is a clock signal terminal as input means for inputting a clock signal; 23 is a driver for clock input from the outside via a clock signal terminal 47; 11 is a clock signal line which is an output of the driver 23; An entry result circuit that controls the value from the empty bit 8 based on the inputs from the initial value register 10, the comparator match line 72, and the clock signal line 11 in addition to the function of transmitting the signal to the 56.

FIG. 10 is a block diagram of a circuit for realizing the timer function of the associative memory circuit 2. In FIG. 10, 1
Reference numeral 2 denotes a countdown counter having a timer function for counting by transition of a clock signal, _TC denotes a count-up output that outputs that the count value of the countdown counter 12 has become “0”, and CEP denotes an initial value input to the countdown counter 12. The input enable which is a timing, CP is a clock input from the clock signal line 11 for inputting a clock, P is a parallel input for inputting initial value data from the initial value register 10, CQ is a counter value, and 13 is a conventional empty bit 61. A flip-flop in which a preset function is added to the realized flip-flop, _SD is a preset input of the flip-flop 13, Q is an output of the flip-flop 13, and 25 is the countdown counter 12 which sets the value of the initial value register 10 as a counter value. A control signal line as a means for setting the "H" only a predetermined time Rutoki.

FIG. 11 shows the relationship between the input and output signals of the countdown counter 12 of FIG. When the input signal of the input enable CEP is “H” and the input signal of the clock input CP rises from “L” to “H”, the input signal to the parallel input P is held in the counter. When the input signal of the input enable CEP is “L” and the signal of the clock input CP rises from “L” to “H”,
The counter value is reduced by “1”, and when the reduced value is “0”, the count-up output_TC becomes “L” level.

Next, the operation of the second embodiment shown in FIG. 9 will be described with reference to FIGS. Initial value register 10 of FIG.
Is set to the initial value of the timer from outside. When setting the initial value as the counter value CQ of the countdown counter 12, the control signal line 25 connected to the input enable CEP of the countdown counter 12 is held at "H".

The control by the control signal on the control signal line 25 is performed by setting a command register 53 for externally controlling the contents of the associative memory circuit 2. Further, the clock signal line 11 connected to the clock input CP of the countdown counter 12 rises from “L” to “H”.

As shown in FIG. 11, input enable CEP
When the clock input CP rises from “L” to “H” while “H” is set to “H”, the contents of the initial value register 10 are stored in the countdown counter 12 via the parallel input P. After that, the control signal line 25 becomes “L”.
Is returned to. When the clock signal line 11 connected to the clock input CP rises from “L” to “H” while the control signal line 25 connected to the input enable CEP is “L”, the counter value CQ becomes “L”. The count value is reduced by “1”, and when the reduced value is “0”, the output of the count-up output_TC becomes “L” level. The count-up output_TC is connected to the preset input_SD of the flip-flop 13. When the preset input_SD goes to "L" level, the output Q of the flip-flop 13 is forced to go to "H" level, and the value of the empty bit 8 becomes "1" indicating an empty state.

As described above, the entry result circuit 9 shown in FIG.
Implements a timer function by inputting an initial value of a counter and a clock signal provided from the outside through an initial value register 10, and realizes an empty bit 8
Control the value of. The operation other than the above is the same as the operation of the conventional continuous storage circuit 49 shown in FIG.

Embodiment 3 "Comparative Data Variable Length" FIG. 12 is a configuration diagram of an associative memory circuit 3 showing Embodiment 3 of the present invention. In FIG. 12, 16 is a plurality of entries provided in the associative memory circuit 3, and 14 is each entry 16
, An entry match line 17 for branching the entry match line 74 and transmitting information of the entry result circuit 14 to the entry 16 having the next higher address, and 15 as an input means for inputting an external sequence signal. A sequence signal terminal, 22 is an inverter for inverting the sequence signal, and 18 is a sequence inversion signal line which is an output of the inverter 22.

FIG. 13 is a block diagram of the entry result circuit 14 for judging the result of comparison with the data to be compared stored in the plurality of entries 16. In FIG. 13, reference numeral 24 denotes an inverter for inverting the signal on the word line WL, reference numeral 21 denotes an inverter output line thereof, reference numeral 23 denotes a flip-flop for storing a comparison result from the entry match line 17, reference numeral 19 denotes a sequence inversion signal line 18, and a comparator match. This is a combinational circuit that outputs a comparison result of a signal from the line 72 and a signal from the output line 20 of the flip-flop 23 to an entry match line 74.

FIG. 14 shows the relationship between the input and output signals of the combinational circuit 19 of FIG. When the empty bit output line 84 is “H”, the entry match line 7
4 outputs “L”. When the empty bit output line 84 is “L” and the sequence inversion signal line 18 is “L”, the signal of the comparator match line 72 is output to the entry match line 74. When the empty bit output line 84 is “L” and the sequence inversion signal line 18 is “H”, the comparator match line 2
7 and the flip-flop output line 20 are both at "H", "H" is output to the entry match line 74,
Otherwise, "L" is output.

Hereinafter, the operation of the variable length comparison data in the second embodiment shown in FIG. 12 will be described. First, an external operation will be described. When storing the compared data having the bit length of one compared register 57 or more in the associative memory circuit 3, the data is stored in a plurality of entries 16 whose addresses are consecutive in ascending order. The storing procedure is the same as in the conventional example shown in FIG.

In this embodiment, in order to compare all the bits of the data to be compared with the comparison data, the comparison operation needs to be performed a plurality of times. The first comparison operation is shown in FIG.
The operation using the sequence signal terminal 15 is added in the second and subsequent comparison operations. When the chip enable signal is valid and the sequence signal input to the sequence signal terminal 15 is “L”, the access to the content addressable memory
6 indicates the second and subsequent comparison operations on the compared data stored in No. 6. In other comparison operations, the sequence signal is "H".

Next, the operation inside the associative memory circuit 3 will be described with reference to FIG.
3 will be described. When the comparison operation is performed, the word line WL is kept at “H”, and when the comparison operation is completed, it becomes “L”. The word line W
The L signal is inverted. The inverted signal is used as the clock input CP of the flip-flop 23 via the inverter output line 21.

Therefore, the word line WL changes from "H" to "L".
The flip-flop 23 stores data at the timing. When the comparison operation is performed, the comparison result is output to the entry match line 74. "H" is output if they match, and "L" is output if they do not match. The flip-flop 23 latches the comparison result output to the entry match line 17 at a timing when the word line WL changes from “H” to “L”. With the above operation,
The flip-flop 23 in the entry result circuit 14 of FIG.
The comparison result of the next smaller entry is stored. The sequence signal input to the sequence signal terminal 15 is
2 and output to the sequence inversion signal line 18.

With the above operation, in the combination circuit 19 shown in FIG. 13, in the comparison operation performed most recently, the comparison result in the entry 16 having the next smaller address is identical, and the current comparator 58 Is high, the sequence signal terminal 15 is "L", and the current comparison operation is a comparison of successive entries, "H" is output to the entry match line 74. When the sequence signal terminal 15 is at "H", the operation is the same as that of the conventional associative memory circuit 49 shown in FIG.

[0072]

As described above, according to the first aspect of the present invention, the comparison result of the entry whose address is smaller by one in the last comparison operation can be used as the current judgment condition. Since the data to be compared is stored in a plurality of entries whose addresses are consecutive in ascending order and the comparison with the comparison data is performed a plurality of times, there is an effect that the comparison of the variable length data can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an associative memory circuit showing a first embodiment of the present invention;

FIG. 2 is a configuration diagram of a comparator in the associative memory circuit of FIG. 1;

FIG. 3 is a configuration diagram of a comparator that detects that data to be compared is smaller than comparison data.

FIG. 4 is a configuration diagram of a comparator that detects that data to be compared is equal to or smaller than comparison data.

FIG. 5 is a diagram showing an input / output relationship of a combinational circuit in the comparators of FIGS. 3 and 4;

FIG. 6 is a configuration diagram of a comparator that detects that data to be compared is larger than comparison data.

FIG. 7 is a configuration diagram of a comparator that detects that data to be compared is greater than or equal to comparison data.

FIG. 8 is a diagram showing an input / output relationship of a combinational circuit in the comparators of FIGS. 6 and 7;

FIG. 9 is a configuration diagram of an associative memory circuit according to a second embodiment of the present invention.

FIG. 10 is a configuration diagram illustrating a main circuit of a second embodiment in FIG. 9;

11 is a diagram showing an input / output relationship of the countdown counter of FIG.

FIG. 12 is a configuration diagram of an associative memory circuit showing a third embodiment of the present invention.

FIG. 13 is a configuration diagram illustrating a main circuit according to a third embodiment in FIG. 12;

FIG. 14 is a diagram showing an input / output relationship of a combinational circuit in the circuit of FIG.

FIG. 15 is a configuration diagram of a conventional associative memory circuit.

FIG. 16 is a diagram illustrating the operation of a compared register and a comparator of a conventional associative memory circuit.

FIG. 17 is a configuration diagram of an empty bit and entry result circuit of a conventional associative memory circuit.

FIG. 18 is a configuration diagram of a CAM result circuit of a conventional associative memory circuit.

[Explanation of symbols]

 Reference Signs List 1 associative memory circuit 2 associative memory circuit 3 associative memory circuit 5 entry 6 comparator 7 entry 8 empty bit 9 entry result circuit 10 initial value register 12 countdown counter 14 entry result circuit 15 sequence signal terminal 16 entry 23 flip-flop 47 clock signal terminal 50 comparison register 57 register to be compared 58 comparator 59 entry result circuit 61 empty bit

Claims (1)

[Claims] 1. A comparison register for holding data to be compared, a compared register for holding data to be compared, a plurality of entries including an empty bit indicating that no data is stored in the compared register, An input means for inputting a sequence signal from the outside, wherein each entry has a flip-flop for storing a comparison result of an entry having a smaller address by one, and a comparison result for comparing the value of the flip-flop when the sequence signal is valid A circuit that sets the comparison result of the entry to “match” when the flip-flop is set and the output of the comparator indicates a match, as a condition for the determination. Associative memory circuit.