JP2000353955A - Sampling digitizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce test costs by providing a second holding circuit of a low droop which is serially connected to a poststage of each high frequency sampling head and holds its sampling potential by a hold signal from a clock generation part. SOLUTION: An identical high frequency signal is given to sampling heads 41 to 4n and is sampled by the same sampling pulse signal. This sampling potential is immediately held in hold capacitors of 2nd HOLD 201 to 20n. A droop rate of the 2nd HOLD 201 to 20n can be made lower than 0.1 μV/1 μS. That is, they can be reduced less than 10-4 multiple in comparison to the droop rates of the high frequency signal sampling head 41 to 4n. Holding potential of the 2nd HOLD 201 to 20n is given to a digitizer 2. The input potential at this time can correctly be measured since it is a sampling potential without droop.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system requiring a plurality of high-frequency sampling digitizers, without using a dedicated digitizer for each of a plurality of channels, and using a plurality of high-frequency signal sampling heads. The present invention relates to a sampling digitizer for a system in which a signal waveform is sampled, converted into a digital signal by one low-frequency digitizer via an analog multiplexer, and processed.

[0002]

2. Description of the Related Art For example, in an analog semiconductor test apparatus, a DU of an analog IC or an analog / digital mixed IC is used.
Digital (DUT) to test
It has an analog converter (hereinafter referred to as "DAC") and a digitizer. Then, an analog signal is generated by the DAC and supplied to the DUT, and the response signal is digitized by a digitizer to test the analog characteristics of the DUT. Here, the digitizer refers to an analog-to-digital converter that operates with an external digitized signal.

There are various types of digitizers mounted on these systems depending on the purpose and application. For example, 1
Msps (samples / second), low-speed but high-precision digitizer with 18-bit resolution, 20Msps and 100M
There are a 12-bit resolution, which is as fast as sps, and a sampling digitizer capable of measuring up to several GHz. Conventionally, depending on the required number of channels, necessary sampling digitizers and high-precision digitizers have been mounted. The sampling digitizer is a waveform digitizer that samples a repetitive waveform of several hundred MHz to several GHz while shifting the phase at a period lower than the frequency under test, and performs AD conversion while maintaining similarity with the input waveform.

However, the analog LS which is a DUT
The development of I and analog / digital mixed LSIs is remarkable, the degree of integration is higher, the frequency range to be handled is wider from high frequency to low frequency, and the number of input / output pins is increasing more and more. For example, in a communication LSI or a TV LSI, an LSI having a high frequency of several hundred MHz to a low frequency of about 1 KHz for audio has been developed, and the number of input / output pins has increased and the number of pins to be tested has also increased.

[0005] As described above, each time the DUT is diversified, it is expensive to add a dedicated unit digitizer or sampling digitizer to perform a test, which leads to an increase in test cost. Therefore, if the system is equipped with the most required digitizer, for example, a low-speed, high-resolution, high-precision digitizer, and if high-frequency signal testing is required, a sampler option can be added as a front-end for testing. As a result, the test cost can be reduced.

The present applicant has previously filed Japanese Patent Application No.
No. 0332 disclosed part of this technology. As one of the disclosures, as shown in FIG.
(I = 1 to n) and the sampling head 4i (i = 1 to n)
There is a technique in which a plurality of n) are provided in parallel, an output signal of each sampling head 4i is selected by an analog multiplexer 5, and digitized by a digitizer 2.

FIG. 5 shows a timing chart of the operation of FIG. FIGS. 5A, 5B, and 5C show waveforms of a high-frequency signal input to a plurality of sampling heads 4i and output waveforms a, b, and which are sampled and converted to a low frequency.
c. Sampling is performed at the timing of the sampling pulse signal 7 shown in FIG. FIG. 5 (D)
At first glance, it looks like sampling is performed with the same sampling pulse signal 7, but the sampling pulse signal 7
Are given at appropriate timing individually for each sampling head 4i. The output waveforms a, b,..., N of the sampling head 4i are transmitted to the analog multiplexer 5 and selected by the selection signal 8 shown in FIG.
The analog signal converted to the low frequency signal shown in FIG. 5E is transmitted to the digitizer 2. Fig. 5 for digitizer 2
Digitized at the digitized signal shown in FIG.
Analog signals a, b, which are low-frequency signals shown in FIG.
.., N are converted into digital data.

[0008]

Even the configuration of FIG. 4 disclosed above operates properly when the number of sampling heads 4i is small. However, as the number of sampling heads 4i increases, the hold time at the sampling heads 4i increases, and the droop rate has become a problem. The droop rate refers to a change in the output voltage due to leakage of charge accumulated in the holding capacitor, that is, leakage from the holding capacitor, leakage from the switch, bias current of the buffer amplifier, and the like. ΔT).

FIG. 6 shows the sampling head 4i of FIG.
1 shows an example of the configuration diagram. Diode bridge 11 as a switch, holding capacitor Ch, and buffer amplifier 12
Are the main components. The sampling head 4i is normally in a non-conductive state. Only when the sampling pulse signal 7 is applied from the clock generation unit 6 is in the conductive state, and the potential of the input signal from the input terminal 3i is stored in the holding capacitor Ch. The capacity of the holding capacitor Ch is
It is about 2 pF.

In the non-conductive state, the leakage current of the diode bridge 11 and the holding capacitor Ch, which are switches, and the input bias current of the buffer amplifier 12 cause
As described above, the output voltage from the sampling head 4i changes with time. Its droop rate (△
V / ΔT) is as large as about 1 mV / 1 μS. This is because the sampling head 4i is for a high-frequency signal, so that the diode bridge 11 that operates at a high speed is used as a switch, and the capacity of the holding capacitor cannot be increased.

FIG. 7 shows the state of the signal waveform in this case.
The droop rate will be described. FIG. 7A shows a high-frequency input signal waveform and a low-frequency ideal output signal waveform input to the sampling head 4i. FIG. 7B shows a sampling pulse signal whose phase is shifted little by little in order to sample the input signal. However, the actual output potential of the sampling head 4i gradually decreases as shown in FIG. 7C. In one measurement example,
ΔT was 10 mV for T of 10 μS. That is, the droop rate (△ V / △ T) is 10 mV / 10
μS = 1 mV / 1 μS, which is considerably large.

Here, a plurality of sampling heads 4i
Are given the same high-frequency signal and are sampled by the same sampling pulse signal. Then, the analog multiplexer 5 is driven by the selection signal 8 shown in FIG.
Each sampling potential is sequentially applied to the digitizer 2. The digitizer 2 digitizes with the EXT CLK signal shown in FIG. 7F which is a digitizing signal. At this time, the input potential of the digitizer 2 is gradually lower than the voltage at the beginning of sampling as shown in FIG. 7 (E), and a measurement error occurs between channels, resulting in lack of reliability.

The present invention eliminates the aforementioned droop rate disadvantages of the previously disclosed multiple sampling option 1 and provides a multiple sampling option 1 which can incorporate a significantly larger number of sampling heads 4i, and provides a general sampling option. It is an object of the present invention to provide a highly accurate sampling digitizer for a plurality of high frequency signals for a system including a plurality of high frequency sampling heads and one low frequency digitizer. Accordingly, an object of the present invention is to reduce the cost in a general system, and particularly to reduce the test cost in an analog semiconductor test apparatus.

[0014]

In order to achieve the above object, the present invention provides a second holding circuit (2nd HOLD), which operates at a low speed but has a very low droop rate, at the subsequent stage of each sampling head. Thus, the sampling potential is maintained immediately after sampling by the sampling head. Therefore, even if the number of sampling heads increases, an appropriate sampling potential can be digitized without any problem. The configuration is as follows.

The first invention is a plurality of high frequency sampling digitizers to be incorporated into a general system. That is, a clock generation unit that applies a sampling pulse signal to each of a plurality of high-frequency signal sampling heads, applies a hold signal to each of a plurality of second holding circuits, and supplies a digitized signal to an external clock input terminal of a digitizer; A plurality of sampling heads for high-frequency signals that sample the high-frequency signal waveform to be measured by receiving the sampling pulse signal from the section, and a hold signal from the clock generation section connected in series to the subsequent stage of each high-frequency sampling head A low-droop second holding circuit for holding the sampling potential of the high-frequency sampling head, and sampling potentials from the plurality of second holding circuits are selected by a selection signal from a clock generator, and the sampling potential is digitized. Analog transmission to And Sa, the sampling potential from the analog multiplexer, the sampling digitizer comprising a digitizer for digitizing the time digitizing signals from the clock generator.

The second invention is a configuration in a system in which a digitizer that has already been incorporated is present and a plurality of high-frequency signal sampling digitizers are added. In other words, there is a built-in digitizer, a plurality of high-frequency signal sampling heads are arranged in parallel at the preceding stage, and a plurality of high-frequency signal waveforms are sampled. A sampling digitizer comprising a low droop second holding circuit between a high frequency signal sampling head and an analog multiplexer in a multiple sampling option for digitizing a high frequency signal waveform.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram of an example of a second holding circuit used in the present invention, and FIG. 3 is a timing chart of the present invention.
First, FIG. 1 will be described.

FIG. 1 is different from the configuration of FIG. 4 disclosed above in that a second holding circuit (2nd HOLD) 20i is provided between each sampling head 4i and the analog multiplexer 5. Second holding circuit 2
Desirably, the droop rate of 0i is zero. Then, the sampling potential accumulated by the sampling head 4i is immediately transmitted to the second holding circuit 20i as it is in accordance with the hold signal 21 from the clock generator 6. The second holding circuit 20i supplies the sampling potential to the analog multiplexer 5 without droop.

The analog multiplexer 5 transmits a required sampling potential to the digitizer 2 according to the selection signal 8 from the clock generator 6. The digitizer 2 digitizes each sampling potential without droop by the digitizing signal 9 from the clock generator 6, and stores each digital data (not shown) in a memory. The stored digital data is processed or displayed for analysis and testing.

FIG. 2 shows a second holding circuit 2 used in the present invention.
FIG. 2 shows an example of a configuration diagram of Oi. The second holding circuit 20i is a circuit that acquires an analog voltage to the holding capacitor CH under the control of the hold signal 21i and holds the analog voltage at a low droop. For this purpose, the sampling potential from the input terminal 19i is received by the first operational amplifier 23 and transmitted to the holding capacitor CH via the switch 24, and the potential of the holding capacitor CH is changed to the second operational amplifier having a very large input impedance. 25 to the output terminal 22i. The output voltage is fed back to the inverting input terminals of the first operational amplifier 23 and the second operational amplifier 25. Therefore, when the switch 24 is on, the input voltage of the input terminal 19i becomes the output voltage of the output terminal 22i as it is, and when the switch 24 is off, the holding potential of the holding capacitor CH is output via the second operational amplifier 25. It is desired that the impedance when the switch 24 is off is very high.

The droop rate of the second holding circuit (ΔV /
ΔT) can be 0.1 μV / 1 μS or less. That is, the droop rate can be reduced to 10 ^-4 times or more as compared with the droop rate of the high frequency signal sampling head 4i. Reducing the droop rate to this extent is practically sufficient. Note that this low droop
Rate sample / hold amplifier ICs are commercially available and may be used.

FIG. 3 shows a timing chart of the present invention. FIG. 3A shows a high-frequency input signal waveform input to the sampling head 4i and an ideal low-frequency output waveform sampled. FIG. 3B shows a sampling pulse signal whose phase is shifted little by little in order to sample the input signal. FIG. 3C shows the sampling head 4i.
Is the output signal. High droop rate. FIG.
(D) is a hold signal 21 to the second holding circuit 20i, which is given immediately after sampling by the sampling head 4i. Then, as shown in FIG. 3E, the output signal of the second holding circuit 20i sends out a sampling potential with almost no droop.

Therefore, a plurality of sampling heads 4i
Are supplied with the same high-frequency signal and are sampled by the same sampling pulse signal. This sampling potential is immediately held in the holding capacitor CH of the second holding circuit 20i, the analog multiplexer 5 is driven by the selection signal 8 shown in FIG. 3 (F), and the holding potential of each of the second holding circuits 20i is digitized by the digitizer 2. Give to. The digitizer 2 digitizes with the EXT CLK signal shown in FIG. At this time, the input potential of the digitizer 2 is
As shown in FIG. 7G, since the sampling potential has no droop, it can be measured correctly.

[0024]

As described in detail above, in the sampling digitizer disclosed above, as the number of sampling heads 4i is increased, it takes a longer time to digitize, and the influence of the droop rate appears. . That is, since the droop rate of the sampling heads 4i was relatively large, the number of sampling heads 4i was limited.

According to the present invention, the second holding circuit 20i for low frequency and having an extremely low droop rate is provided at the subsequent stage of the sampling head 4i, and the sampling potential is held by the second holding circuit immediately after sampling. Thus, the droop rate could be reduced more than ^10-4 times over the prior art. Therefore, more accurate measurement can be performed, and the number of sampling heads 4i can be increased as necessary.

In a system of electronic equipment, a low-cost sampling digitizer having a plurality of high-frequency sampling heads 4i has been constructed. Furthermore, if there is a digitizer already installed, by adding this multiple sampling option, a plurality of high frequency sampling digitizers can be obtained at low cost. Therefore, the test cost is reduced,
The effect is great.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of an example of a second holding circuit used in the present invention.

FIG. 3 is a timing chart of the present invention.

FIG. 4 is a block diagram of a prior art multiple sampling option.

FIG. 5 is a configuration diagram of an example of a sampling head.

FIG. 6 is a timing chart of FIG. 4 of the related art.

FIG. 7 is an explanatory diagram of a droop rate in the prior art.

[Description of Signs] 1 Multiple sampling option 2 Digitizer (DGT) 3i (i = 1 to n) Input terminal 4i (i = 1 to n) Sampling head 5 Analog multiplexer 6 Clock generator 7 Sampling pulse signal 8 Selection Signal 9 Digitized signal 11 Diode bridge 12 Buffer amplifier 20 Second holding circuit (2nd HOLD) 21 Hold signal 23, 25 Operational amplifier 24 Switch

Claims (2)

[Claims] A clock generating unit for supplying a sampling pulse signal to each of a plurality of high frequency signal sampling heads, supplying a hold signal to each of a plurality of second holding circuits, and supplying a digitized signal to an external clock input terminal of a digitizer; A plurality of high frequency signal sampling heads that sample the high frequency signal waveform to be measured in response to a sampling pulse signal from the clock generation unit, and are connected in series at the subsequent stage of each high frequency sampling head and are held by the clock generation unit. A low-droop second holding circuit that temporarily holds the sampling potential of the high-frequency sampling head, and sampling potentials from a plurality of second holding circuits, which are selected and selected by a selection signal from a clock generation unit. That transmits the sampling potential to the digitizer The sampling potential from the log multiplexer and the analog multiplexer
A digitizer for digitizing a digitized signal from a clock generation unit; and a sampling digitizer. 2. A built-in digitizer exists, a plurality of high-frequency signal sampling heads are arranged in parallel at the preceding stage, and a plurality of high-frequency signal waveforms are sampled. A plurality of sampling options for sequentially digitizing a plurality of high-frequency signal waveforms, wherein the plurality of sampling options include a low-droop second holding circuit provided between a high-frequency signal sampling head and an analog multiplexer. Sampling digitizer.