JP2000348497A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which restrains the area increase rate of a memory cell array and on which an ECC circuit is mounted. SOLUTION: An EEPROM which reads and writes data in units of one byte is provided with a parity-bit generation circuit 19 in which a parity bit used to correct an error regarding data to he written in a memory cell array 11 is generated with respect to a four-byte information bit, an error correction circuit 17 in which a four-byte information bit to be selected by a main column decoder 12 and a parity bit to be given to the information bit are read out so as to correct an error, and a subcolumn decoder 15 which selects and outputs one-byte data corresponding to an input address out of the four-byte information bit to the output from the error correction circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using an electrically rewritable nonvolatile memory cell and incorporating an error correction circuit.

[0002]

2. Description of the Related Art Conventionally, NOR type EEPROMs and NANs have been used as electrically rewritable nonvolatile semiconductor memories.
Various types such as a D-type EEPROM have been developed and put into practical use.
FRAM using ferroelectric capacitors is also EEP in a broad sense.
Included in ROM. In these EEPROMs, for example,
Data is rewritten in units of one byte. In this case, erroneous data may be written at a fixed rate. It is difficult to completely eliminate such erroneous writing by process improvement. In order to correct erroneously written data in a circuit, an EEPROM is equipped with an error correction code (ECC) circuit.

[0003] ECC means regular data (information bits)
This is a method that enables error correction of data by adding redundant bits called parity bits to data. E
There are several types of CC, such as a Hamming code system, a horizontal / vertical parity code check system, and a BCH code system. Here, the Hamming code is taken up. In the case of the Hamming code, the parity bits are determined according to the data pattern of the information bits, and the number m of the parity bits necessary to enable one-bit error correction in the n-bit information bits is as follows:
It is necessary to satisfy n ≦ 2 ^m −m−1.

FIG. 7 shows an EEPRO equipped with an ECC circuit.
The schematic configuration of M is shown. Parity bit generation circuit 3
Is a circuit for generating a parity bit from data to be written (information bits) sent from the I / O terminal via the switching circuit 2, and the generated parity bits are stored in the memory cell array 1 together with the information bits. The error correction circuit 4 corrects data read from the memory cell array 1 based on parity bits, and includes a syndrome generation circuit 6 and a code conversion circuit 5. The syndrome generation circuit 6 performs a predetermined operation (syndrome calculation) on the read information bits and parity bits, and outputs an erroneous address as a result. The code conversion circuit 5 receives the erroneous address output from the syndrome generation circuit 6 and inverts the erroneous bits “1” and “0” of the information bits read from the memory cell array 1. And outputs the corrected information bits. This information bit is taken out to the I / O terminal via the switching circuit 2.

[0005]

When an ECC circuit is mounted on a memory, data errors can be corrected, but there is a problem that the area of a memory cell array is increased by the amount of parity bits. As is apparent from the above equation, the ratio of the parity bit to the required number of bits is larger as the number of information bits is smaller. Assuming that m bits of parity bits are added to k bytes (= 8 × k bits) of information bits, the area increase rate of the memory cell array (Area Penal
The k dependence of ty = 100 × m / 8k (%) is as shown in FIG. Specifically, in the case of a memory in which data is rewritten and read in units of 1 byte, since information bits are 1 byte (= 8 bits), 4 parity bits are required. At this time, the area increase rate of the memory cell array is 50% from FIG. Therefore, the memory chip size increases, and the manufacturing cost increases accordingly.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device having an ECC circuit with a reduced area increase rate of a memory cell array.

[0007]

According to the present invention, there is provided a semiconductor memory device comprising: a memory cell array in which electrically rewritable nonvolatile memory cells are arranged; a decoding circuit for selecting a memory cell in the memory cell array; When reading the n-bit data of the memory cell array in parallel,
An error correction circuit that reads out n × k (k: positive integer) bits of information bits including the n-bit data and a parity bit added to the information bits to perform error correction, and an output from the error correction circuit. and a sub-decoding circuit for selecting and outputting n-bit data corresponding to the input address among the n × k information bits.

According to the present invention, as the data to be read internally for error correction, the number of bits of the data which is to be read out to the outside is multiplied by an integer multiple of the number of bits of the data as a unit of reading. Range. As a result, the number of parity bits of the ECC circuit can be reduced, and the EEPR
It is possible to suppress an increase in the chip area of the OM.

More specifically, a semiconductor memory device according to the present invention has a memory cell array in which bit lines and word lines are arranged to cross each other, and electrically rewritable memory cells are arranged at the respective intersections. And a row decoder that decodes a row address in the input address to select a word line of the memory cell array, and decodes a higher-order address in a column address in the input address to nx
a main column decoder for selecting k (k: positive integer) bit line data, and a parity for generating n × k information bits for error correction of data to be written to the memory cell array A bit generation circuit, an n × k-bit information bit selected by the main column decoder, and an error correction circuit for performing error correction by reading a parity bit added to the information bit; A sub column decoder for decoding and selecting and outputting n-bit data corresponding to an input address among the n × k information bits output from the error correction circuit.

[0010] In the present invention, it is preferable that one bit for transferring data to and from a bit line of a memory cell array is provided.
A page buffer that can hold data for a page, and is provided between the error correction circuit and the sub-column decoder, and stores n × k-bit sub-page data output from the error correction circuit or the main column decoder. And a sub-page buffer for temporarily storing. This gives n
When rewriting data in bit units, it becomes possible to perform error correction and parity bit addition in n × k bit subpage units.

Specifically, in the present invention, when rewriting data of a selected page of the memory cell array in units of n bits, data of an n × k bit subpage of the selected page is read out together with a parity bit. The error correction circuit corrects the error and stores the data in the sub-page buffer, and stores the data stored in the sub-page buffer at a corresponding address of the page buffer by adding a parity bit generated based on the data. Then, of the data stored in the sub-page buffer, n bits specified by the column address are replaced with n-bit rewrite data input from the outside, and the partially replaced sub-page data is The parity bit generated based on the selected A series of operations are performed that writes back over di.

The above-mentioned series of operations will be described more specifically as follows. (A) inputting a row address for selecting a page of the memory cell array to be rewritten,
(B) of the page selected by the row address, the data of the first subpage of n × k bits is read out together with the parity bit, error-corrected by the error correction circuit, and stored in the subpage buffer; And (d) storing the data stored in the sub-page buffer at a corresponding address of the page buffer by adding a parity bit generated based on the data, and (d) updating the sub-page address to Up to the subpage (b),
The operation of (c) is repeated, (e) a column address to be rewritten and n-bit rewrite data are input, and (f) data of a subpage corresponding to the input column address is read from the page buffer and the subpage is read. (G) n of data stored in the sub-page buffer corresponding to the column address
Replacing the bits with the externally input rewrite data, and (h) replacing the partially replaced subpage data with
A parity bit generated based on this is added and stored in a corresponding address of the page buffer, and (i)
The data of the selected page in the memory cell array is erased collectively, and (j) the data of the subpage stored in the page buffer is written in the erased page.

In the present invention, in order to enable a row address, a column address and rewrite data to be continuously input, a main column address latch for latching an address decode signal of the main column decoder and a sub column address latch are provided. A sub or ram address latch for latching an address decoder signal of the decoder is provided.

Further, in the present invention, when rewriting data in units of one page of the memory cell array, it is easier to rewrite data of n × k
Bit-by-bit subpages are sequentially stored at the corresponding addresses of the subpage buffer data, parity bits are added to the data of each subpage, and the data are sequentially stored at the corresponding addresses of the page buffer. The page data may be erased, and one page of rewrite data stored in the page buffer may be written to the page.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows an EEPROM according to a first embodiment.
Is shown. In this embodiment, the memory cell array 11 has a plurality of bit lines B as shown in FIG.
L and the word line WL are arranged so as to intersect, and a nonvolatile memory cell transistor MC having a floating gate is arranged at each intersection. Memory cell transistor M
One end of C is connected to a bit line BL via a select gate transistor SG1, and the other end is connected to a common source line via a select gate transistor SG2. A memory cell including one memory transistor MC and two selection transistors SG1 and SG2 connected in series to the memory transistor MC is called a 3Tr-NAND cell.

The range of the word line WL that commonly connects the control gates of the memory cells MC in one direction of the memory cell array 11 is one page, and the bit line ends receive and transmit data one page at a time with the memory cell array 11. Page buffer 12 is provided. Page buffer 1
2 includes a data latch 21 connected to each bit line BL. Among the externally input addresses, the row decoder 13 selects a word line of the memory cell array 11 by a row address, and the main column decoder 1 selects a bit line by a column address.
4.

Referring to FIG. 2, the operation of reading and rewriting data in memory cell array 11 will be described as follows. In the memory cell MC, the enhancement state in which electrons are injected into the floating gate with a positive threshold value is defined as “0”, and the depletion state in which electrons in the floating gate are emitted with a negative threshold value is defined as “1”. . Data reading is performed by applying 0 V to the selected word line WL and 3.5 V to the selection gate lines SGD and SGS on both sides thereof, and detecting a drop in bit line potential. If the bit line potential decreases from the initial charging potential, it is determined that the data is “1”.

Data rewriting is performed in the memory cell array 11
Is transferred to the page buffer 12 once, the data of the page is collectively erased, necessary data is rewritten in the page buffer, and then the operation of writing back to the same page is performed. In the data erasing, a high voltage of, for example, 20 V is applied to the p-type well in which the memory cell array 11 is formed, and 0 V is applied to the word line WL of the selected page, and all other word lines and the selection gate line are made floating. As a result, in the memory cell of the selected page, electrons of the floating gate are discharged to the p-type well, and become data “1”.

In data writing, the potential of each bit line is set to 0 V or VCC according to data "0" and "1".
These potentials are supplied from each latch of the page buffer 12. Then, VCC is applied to the drain side select gate line SGD and 0 V is applied to the source side select gate line SGS of the selected page, and the bit line potential is transferred to the drain of the selected memory cell. In this state, 16
A high voltage of about V is applied. Thus, in the memory cell transistor of “0” write, a large voltage is applied between the control gate and the channel, and electrons are injected into the floating gate. In the memory cell transistor for writing “1” data, the channel potential rises due to the capacitive coupling with the control gate, so that electron injection does not occur and the “1” state is maintained.

In this embodiment, as an ECC circuit for correcting erroneous write data, a parity bit generation circuit 19 for generating a parity bit added to write data, and an ECC circuit for correcting data read by the sense amplifier 16. An error correction circuit 17 for performing error correction is provided. The error correction circuit 17 has a syndrome generation circuit for generating an error address in the data read based on the parity bit and a code conversion circuit for inverting the bit of the error address by its output, as described in the background art. .

In this embodiment, the memory cell array 11 is mounted while the ECC circuit is mounted as described above.
We are trying to minimize the area increase rate. Specifically, when viewed from the I / O terminal, rewriting and reading of data are performed in parallel in units of n bits, whereas data processing for error correction is an integer (k) times, that is, n × k bits. More specifically, FIG.
While data rewriting and reading are performed in byte units, the memory cell array 11 simulates data rewriting and reading in 4-byte units.
In this way, if the number of information bits is simulated in 4-byte units, the required number of parity bits becomes 6 bits, and the ECC
The area increase rate is 18.8 compared to the case where no circuit is mounted.
%.

Hereinafter, a set of data consisting of 4-byte information bits is referred to as a subpage for convenience of description. In the data read operation, data is read from the memory cell array 11 in subpage units, and only one byte is taken out to the I / O terminal. In the data rewriting operation, data of the selected page is temporarily read out to the page buffer 12 and
After rewriting only the bytes, a process of rewriting is performed. For this purpose, as shown in FIG. 1, a sub-page buffer 18 for holding information bits for 4 bytes is provided. In addition, a sub-column decoder 15 is provided separately from the main column decoder 14 in order to select 1-byte data from sub-page data. One page includes an integer multiple of the sum of a 4-byte subpage and a 6-bit parity bit. Assuming that the net data of one page is 128 bytes, one page includes 32 pairs of subpages and parity bits.

Next, a data read operation in this embodiment will be described. In this embodiment, the column addresses are A1, A2,
.., A5 main column address and each sub page (4
The sub-column address is composed of A6 and A7 for selecting one byte in (byte). At the time of data reading, as shown in FIG.
To A5 are supplied to the main column decoder 14. As a result, the main column decoder 14 selects a sub-page (including 1-byte data corresponding to the input address) specified by the main column address and a parity bit corresponding to the sub-page from the data of one page. As a result, the data and parity bits of the sub-page including one byte corresponding to the input address are transferred to the sense amplifier 16.
And sent to the error correction circuit 17.

The data of the subpage (4 bytes) corrected by the error correction circuit 17 is stored in the subpage buffer 18.
Sent to Then, of the column addresses, one-byte data corresponding to the input address is selected from the subpage buffer 18 by the sub-column decoder 15 to which the sub-column addresses A6 and A7 are supplied, and read out to the I / O terminal. .

Next, the operation of rewriting data in 1-byte units will be described with reference to the timing chart of FIG. In the data rewriting operation, the data of the selected page of the memory cell array 11 is read in subpage units to correct the error,
The operation of storing in the page buffer 12 is repeated. Then, the corresponding one byte in the page buffer is replaced by one byte of rewritten data from the outside, and the data of the selected page is collectively erased, and then the rewritten data is written to the same page. As shown in FIG. 3, at time t1, a row address of data to be rewritten is input (time t1). Then, the first sub-page (4 bytes) of the page selected by the input row address and the corresponding parity bit are read, error correction is performed by the error correction circuit 17, and the data of the obtained sub-page is stored in the sub-page. The data is stored in the buffer 18. Next, the data of the subpage is stored in the head of the page buffer 12 together with the parity bits generated by the parity bit generation circuit 19 based on the data. Hereinafter, the address of the subpage is sequentially updated, and the same operation is repeated up to the address of the last subpage. Thus, one page of data including the data to be rewritten is error-corrected and stored in the page buffer 12.

Next, at time t2, the column address of the data to be rewritten (hereinafter referred to as a selected column address) is input, and then the 1-byte data to be rewritten is input from the I / O terminal. Then, the data of the subpage corresponding to the selected column address is read from the page buffer 12 and is directly read from the subpage buffer 1.
8 is stored. Of the stored data, one byte of data corresponding to the selected column address is replaced with data input from the I / O terminal. The data of the subpage in which the partial data has been replaced in this way is written back together with the parity bits generated by the parity bit generation circuit 19 based on the data to the portion of the page buffer 12 corresponding to the selected column address. When rewriting data of a plurality of bytes, the column address is updated from time t3, and the same data replacement operation is repeated for a plurality of bytes.

After the data replacement in the page buffer 18 is completed, one page of data corresponding to the selected row address is erased at a time t4. However, this data erasing operation can be performed in parallel with the above-described data replacement operation after time t2. Then, at time t5, the partially rewritten data stored in the page buffer 12 is written to the erased page.

As described above, according to this embodiment, for data reading in units of 1 byte, data reading is internally performed in units of subpages (4 bytes) including target 1 byte data. Error correction by the ECC circuit. Similarly, in the case of data rewriting, error correction is performed in units of subpages for data rewriting in units of 1 byte, and only one byte to be rewritten is
An operation of replacing the data with externally input data, adding a parity bit to the subpage again, and writing back the data is performed. As described above, by increasing the data length of the parity bit addition as compared with the data actually input / output from the I / O terminal, the required number of parity bits can be reduced, and the ECC circuit is built in. Can suppress an increase in chip size.

[Embodiment 2] FIG. 4 shows a row address,
1 is an EEPROM according to an embodiment that enables continuous input of a column address and rewrite data. Portions corresponding to those in the above embodiment are denoted by the same reference numerals, and detailed description is omitted. The data read operation is the same as that of the previous embodiment, and FIG. 4 shows the data flow by focusing only on the data rewriting. In this embodiment, the main column decoder 14 in FIG.
The main column address decoder 14a and the main column gate 14b controlled by the sub column decoder 15 correspond to the sub column address decoder 15a and the sub column gate 15b controlled by the sub column decoder 15. In this embodiment, a 32-bit main column address latch 45 holding an address decode signal of the main column address decoder 14a,
There are 32 sets of 4-bit sub-column address latches 46 for holding the address decode signal of the sub-column address decoder 15a.

The page buffer 12 has 4 bytes +
It has a data latch 41 for each number of parity bits and a transfer switch 42 for selectively transferring the latch data, which is controlled by a sub-column address latch 46. Further, an error correction circuit 1 is used as a subpage buffer.
7 for holding the output of the first sub-page buffer 1
8a, and a second sub-page buffer 18b for directly holding data from the main column decoder 14. A transfer switch 47 controlled by the output of the sub column address decoder 44 is provided between the sub page buffers 18a and 18b.

The data rewriting operation will be described with reference to FIG. 5. As shown, a row address and a column address are input at time t1, and one byte of rewriting data is input continuously. The input address is stored in each address latch as follows. That is, the main column address is decoded by the main column decoder 14a, and the position of the hit (that is, "H") decoded signal is stored in the main column address latch 45. The sub-column address is decoded by the sub-column address decoder 15a, and the position of the hit decode signal is stored in the sub-column address latch 46.

The 1-byte rewrite data D1 input from the I / O terminal is supplied to the sub-column address decoder 15a.
The transfer switch 42 is selected by the sub-column gate 15b, is selected by the main column address decoder 14a, passes through the main column gate 14b, and is selectively turned on by the output of the sub-column address latch 46.
Is stored in the data latch 41 corresponding to the input column address in the page buffer 12 via the Latch 41
Has a capacity of 4 bytes + parity bits, and 1-byte rewrite data D1 is transferred to a position designated by the sub-column address. When rewriting data of a plurality of bytes, the column address is updated at time t2, the next one-byte rewrite data D2 is input, and similarly stored in the latch 42 corresponding to the address of the page buffer 12. Hereinafter, the same operation is repeated.

After the rewriting address and the rewriting data are latched as described above, the operation of reading the data of the page specified by the row address in subpage units from time t3 and performing error correction is repeated. That is, the head subpage and the parity bit are read out and error correction is performed by the error correction circuit 17 as in the previous embodiment. The corrected subpage (4 bytes) data is the first
Is stored in the sub-page buffer 18a.

If the sub-page address read above matches one of the main column addresses stored in the main column address latch 45, the next
Perform the above operations. Sub-page data including one-byte rewrite data is read from the latch 41 of the page buffer 12 corresponding to the corresponding main column address, and stored in the second sub-page buffer 18b. The transfer switch 47 is supplied with address data of the sub column address latch 46 corresponding to the corresponding main column address. Then, among the 4-byte data of the second sub-page buffer 18b, the data of 1 byte unit (this is the data to be rewritten) for which the sub-column address latch 46 generates the hit signal is transferred via the transfer switch 47. , First subpage buffer 18a
Overwrite the data of the subpage of. At this time, the hit signal may be set for a plurality of bytes.

The data held in the first sub-page buffer 18a by the above operation is transferred to the page buffer 12 of the corresponding column address together with the parity bit generated from the parity bit generation circuit 19 as in the previous embodiment. Write back. When rewriting data of a plurality of bytes, error correction and data replacement for the next subpage are similarly performed.

After the above operation is completed, at time t4, the page data of the memory cell array 11 specified by the row address is erased collectively. Thereafter, at time t5, the data stored in the page buffer 12 is written to the erased page of the memory cell array 11.

As described above, in this embodiment,
By providing a main column address latch and a sub column address latch, row and column addresses and rewrite data are continuously input, and data rewrite in 1-byte units is performed with error correction and parity bit addition in subpage units. It can be carried out. Further, as in the previous embodiment, error correction and parity bit addition are performed in subpage units, so that the number of necessary parity bits is reduced, and an increase in chip size due to the incorporation of an ECC circuit is suppressed. be able to.

[Third Embodiment] In the first and second embodiments, the unit of data rewriting is 1 byte, and data reading and error correction are performed in units of subpages (4 bytes) including the address to be rewritten. A method of rewriting and rewriting a part of the subpage is used. On the other hand, the unit of data rewriting is larger than the subpage, for example, 1
The same invention can be applied to an EEPROM having a page unit. Operation timing in such an embodiment is shown in FIG. The EEPROM configuration is shown in FIG.
Shall be the same as

In this embodiment, the entire page is rewritten. Therefore, unlike the first and second embodiments, the operations of reading data and correcting errors in subpage units are not required when rewriting data. That is, as shown in FIG. 6, a row address, a column address, and one-byte rewrite data D1 are input. The rewrite data D1 is
The data is stored in the sub-page buffer 18 via the sub-column decoder 15.

The column address is updated, the next rewrite data D2 is input, and this is stored in the subpage buffer 18 in the same manner. When the 4-byte rewrite data is stored in the sub-page buffer 18, the 4-byte data is added with a parity bit generated by the parity bit generation circuit 19 based on the 4-byte data, and the address of the first sub-page of the page buffer 12 is added. Write to. Hereinafter, similarly, the rewrite data of every 4 bytes is added with a parity bit, and the rewrite data of all pages is stored in the page buffer 12.

Thereafter, after the data of the page selected by the row address of the memory cell array 11 is collectively erased, the data stored in the page buffer 12 is written to the erased page. The page erasing operation can be performed in parallel with the operation of sequentially storing the rewrite data in the page buffer 12.

According to this embodiment, since data is rewritten in units of one page, unlike the case where a part of one page is rewritten as in the first and second embodiments, the data of the selected page is not rewritten. Need not be read for each subpage to perform error correction processing, and the data rewriting processing is simplified. As in the first embodiment, the data reading is performed by performing error correction in units of subpages for reading in units of 1 byte, thereby reducing the number of parity bits and chip size by incorporating an ECC circuit. Increase can be suppressed.

Although the embodiment has been described with respect to the case where data is read and rewritten in units of 1 byte, the same applies to an EEPROM which reads data in units smaller than one page size, such as in units of 2 bytes or 3 bytes. However, the present invention is effective. In the embodiment, 3Tr
-Although the NAND type EEPROM has been described, the normal NAN
The present invention can be similarly applied to a D-type or NOR-type EEPROM.

[0044]

As described above, according to the present invention, error correction is performed in a range of a number of bits larger than the number of bits as a unit of data reading and rewriting.
It is possible to suppress an increase in chip size when a CC circuit is mounted.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an EEPROM according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a memory cell array of the embodiment.

FIG. 3 is a timing chart of a data rewriting operation of the EEPROM of the embodiment.

FIG. 4 is a diagram showing a configuration of an EEPROM according to another embodiment.

FIG. 5 is a timing chart of a data rewriting operation of the EEPROM of the embodiment.

FIG. 6 is a timing chart of a data rewriting operation according to another embodiment.

FIG. 7 is a diagram showing a schematic configuration of a conventional EEPROM equipped with an ECC circuit.

FIG. 8 is a diagram showing the relationship between the number of information bits to which parity bits are added and the area increase rate.

[Explanation of symbols]

11: memory cell array, 12: page buffer, 13
... row decoder, 14 ... main column decoder, 15 ...
Sub column decoder, 16 sense amplifier, 17 error correction circuit, 18 sub page buffer, 45 main column address latch, 46 sub column address latch.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 (72) Inventor Junichiro Noda 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Corporation F term in microelectronics center (reference) 5B025 AA03 AB01 AC01 AD02 AD04 AD05 AD08 AD13 AE00 5F001 AA01 AB02 AD12 AE01 AE50 5F083 EP02 EP22 EP76 EP77 FR05 GA09 LA04 LA05 LA10 5L106 AA10 BB13

Claims (7)

[Claims] A memory cell array in which electrically rewritable nonvolatile memory cells are arranged; a decoding circuit for selecting a memory cell in the memory cell array; and a memory for reading n-bit data in the memory cell array in parallel. An error correction circuit for reading out n × k (k: positive integer) bits of information bits including the n-bit data and a parity bit added to the information bits to correct the error, and an error correction circuit output from the error correction circuit and a sub-decoding circuit for selecting and outputting n-bit data corresponding to the input address among the n × k information bits. 2. A memory cell array comprising bit lines and word lines intersecting each other, and electrically rewritable memory cells arranged at each intersection, and decoding a row address among input addresses. A row decoder for selecting a word line of the memory cell array; a main column decoder for decoding an upper address among column addresses among the input addresses to select n × k-bit bit line data; A parity bit generation circuit for generating n × k (k: a positive integer) information bits for error correction for data to be written; and a n × k bit selected by the main column decoder. Error correction for reading out information bits and the parity bits assigned to the information bits to correct errors A sub-column decoder that decodes a lower address of the column addresses and selects and outputs n-bit data corresponding to an input address among the n × k-bit information bits output from the error correction circuit. A semiconductor memory device comprising: 3. A page buffer for transferring data to and from a bit line of the memory cell array, the page buffer being capable of holding one page of data, and being provided between the error correction circuit and the sub-column decoder. 3. The semiconductor memory device according to claim 2, further comprising: a sub-page buffer for temporarily holding nxk-bit sub-page data output from said error correction circuit or main column decoder. 4. When rewriting data of a selected page of the memory cell array in units of n bits, of the selected page, data of a subpage of n × k bits is read together with a parity bit and read by the error correction circuit. Correcting the error and storing the data in the sub-page buffer; storing the data stored in the sub-page buffer at a corresponding address of the page buffer with a parity bit generated based on the data; Of the data stored in the buffer, n bits specified by the column address were replaced by n-bit rewrite data input from the outside, and the data of the partially replaced subpage was generated based on this. Writing back to the selected page of the memory cell array together with the parity bit 4. The semiconductor memory device according to claim 3, wherein a series of operations are performed. 5. When rewriting data in units of n bits, (a) a row address for selecting a page to be rewritten in the memory cell array is input; and (b) n × k bits among pages selected by the row address. The data of the first subpage is read out together with the parity bit, error-corrected by the error correction circuit and stored in the subpage buffer, and (c) the data stored in the subpage buffer is generated based on the data. (D) updating the address of the subpage and repeating the operations (b) and (c) until the last subpage, and (e) Input the column address to be rewritten and the n-bit rewrite data, and (f) enter a subpage corresponding to the input column address. Stored in the subpage buffer data read from the page buffer,
(G) replacing n bits corresponding to the column address among the data stored in the subpage buffer with the externally input rewrite data, and (h) replacing the partially substituted subpage data with: A parity bit generated based on this is added and stored in a corresponding address of the page buffer, and (i) data of the selected page in the memory cell array is erased collectively;
4. The semiconductor memory device according to claim 3, wherein a series of operations of (j) writing the data of the subpage stored in the page buffer to the data-erased page is performed. 6. A main column address latch for latching an address decode signal of the main column decoder, and a sub or ram address latch for latching an address decoder signal of the sub column decoder, wherein a row address, a column address and n 4. The semiconductor memory device according to claim 3, wherein bit rewrite data can be continuously input. 7. When rewriting data in one page unit of the memory cell array, sub-pages of n × k bits are sequentially stored in a corresponding address of the sub-page buffer data among rewriting data of one page. A parity bit is added to the data of the sub-page, the data is sequentially stored at the corresponding address of the page buffer, the data of the selected page of the memory cell array is erased, and one page stored in the page buffer is stored in the page. 4. The semiconductor memory device according to claim 3, wherein the rewrite data is written.