JP2000347815A - Disk array system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the disk array system which adds a guarantee code based upon the property of data to data and is improved in transfer efficiency. SOLUTION: A host input/output means 208 sends and receives data between a host 100 and a cache 240 according to a transfer list containing an LA(logical address) generated by an MPU 250. An LA holding means 320 in a host information holding means 240 acquires and holds the LA when the data are transmitted and received between the host input/output means 208 and cache 240. An LA adding means 300 adds the LA stored in the LA holding means 320 to the data to be written to the cache 240.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a disk array system having a plurality of disk devices arranged in an array, and more particularly to a disk array system suitable for use as a storage system of a computer system.

[0002]

2. Description of the Related Art Disk array systems use RAID (R)
edundant Arrays of Inexpensive Disks)
Take a configuration in which multiple disk devices are arranged in an array,
A storage device in which read requests (data read requests) and write requests (data write requests) from a host are processed at high speed by parallel operation of disks, and reliability is improved by adding redundant data to data. is there. Disk array systems are, for example, "AC
ase for Redundant Arrays of Inexpensive Disks (RAI
D) ", David A. Patterson, Garth Gibson, and Randy H.
Katz, Computer Science Division Department of Elec
trical Engineering and Computer Sciences, Universi
As noted in the ty of California Berkeley,
The redundant data is classified into five levels according to the type and configuration.

At the time of a write request from the host, the data received from the host is divided by a special address conversion in the disk array, temporarily stored in a cache, and then sequentially written in parallel to the disk device. At the time of a read request from the host, the divided data is read in parallel from the disk device and stored in the cache, and the divided data read from the cache is bundled as original data and transferred to the host.

In a disk array, redundant data is created and stored in a disk device so that data can be restored even in the event of a disk device failure. In addition, for the purpose of increasing the reliability of the entire disk array, each logical data is created. It is known to add a guarantee code to each data block. As a method of adding a guarantee code, for example, as described in US Pat. No. 5,706,298, an LRC (Longitudinal Redundancy) for performing an exclusive OR operation in the vertical direction of each logical data block is used. Check)
There is known a device which adds a guarantee code called "data" and checks for a data bit error during data transfer inside the disk array.

[0005]

However, at the time of writing / reading in the disk array, a special address conversion is performed in order to perform parallel transfer to the disk.
Transfer data in a divided state. Therefore, a data bit error during transfer can be detected by the LRC that performs an exclusive OR operation in the vertical direction of each logical data block.
Writing cannot be detected.

Therefore, as a method of detecting read / write of the divided data with respect to an abnormal address, a method of adding a data guarantee code such as a transfer source address based on an attribute of data that can specify data to be transferred, to the data is also available. Conceivable.

On the other hand, in recent years, transfer efficiency has been improved by using host input / output means with a transfer function instead of providing the transfer function to the cache controller.

Here, if an attempt is made to add a guarantee code based on the attribute of data to data using the host input / output means with a transfer function, it is necessary to interrupt the processor every time data is transferred. It was found that the processor was involved in the transfer operation, and as a result, the transfer efficiency was reduced.

An object of the present invention is to provide a disk array system capable of adding a guarantee code based on data attributes to data and improving transfer efficiency.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention writes data from a host to a disk array having a plurality of disk devices arranged in an array, and writes data to the disk array. In the disk array system that reads out the data to the host, the disk array specifies host input / output means for performing input / output with the host, a cache for temporarily holding data, and a guarantee code based on the attribute of the data. And a MPU for creating a transfer list of the host input / output means. When a data write request is issued from the host, the MPU transmits the data to the host input / output means. Create a list, set a value in this transfer list that identifies a guarantee code based on the attributes of the data, The host input / output unit transmits the data to the cache according to the transfer list including a value specifying the guarantee code based on the attribute of the data, and the guarantee code holding unit transmits the data when the data is transmitted to the cache. A value for specifying a guarantee code based on the attribute of data is obtained, and a value for specifying a guarantee code based on the attribute of data is held. The assurance code adding means is based on the attribute of the data stored in the guarantee code holding means. The value specifying the guarantee code is added to the data written in the cache. With this configuration, the value specifying the guarantee code based on the attribute of the data is added to the data to be written by referring to the value specifying the guarantee code based on the attribute of the data in the transfer list. A value for specifying the guarantee code based on the attribute can be added to the data, and the value for specifying the guarantee code can be added without using the MPU, so that the transfer efficiency can be improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a disk array system according to a first embodiment of the present invention will be described below with reference to FIGS. First, the configuration of the disk array system according to the present embodiment will be described with reference to FIG.

The hosts 100, 110, and 120 are connected to host input / output means 208, 209, and 210 in the disk array 200 connected by host cables via a bus switch 130 connected by host cables. . The number of the hosts 100, 110, and 120 may be at least one.

The disk array 200 includes host input / output means 208, 209, 210 and disk input / output means 21.
8, 219, 220 and disk device groups 228, 22
9, 230, a cache 240, an MPU 250 for controlling the entire disk array, a memory 260, and a cache controller 270.

Host input / output means 208, 209, 210
Executes the transfer between the hosts 100, 110, 120 and the cache controller 270, and is executed by the host-side internal bus 212.
Connected to 0. The host input / output means 208 is a DMA2 for executing data transfer on the host-side internal bus 212.
11 is provided. DMA 211 can also access memory 260. Host input / output means 2
09 and 210 also have the same function as the host input / output unit 208. The host input / output means 208, 20
9, 210 need only be at least one or more.

Disk unit groups 228, 229, 230
Are each composed of at least one or more disk devices. For example, it is assumed that the disk device group 228 includes disk devices 234, 235, and 236.
Note that the disk device groups 228, 229, and 230 only need to be at least one or more.

The disk input / output means 218 executes data transfer between the disk device group 228 and the cache controller 270.
1 to the disk device group 228, and the cache controller 27 by the disk-side internal bus 222.
0 is connected. The disk input / output means 218 is a DM for executing data transfer on the disk-side internal bus 222.
A221. The DMA 221 has a memory 260
Access to can also be performed. Similarly to the disk input / output unit 218, the disk input / output units 219 and 220 are connected to the disk device groups 229 and 230 by disk cables 232 and 233, respectively, and are connected to the cache controller 270 by the disk-side internal bus 222. . The disk input / output units 219 and 220 also have the same function as the disk input / output unit 218. The number of disk input / output units 218, 219, 220 is at least one. Further, the cache 240 is connected to the cache controller 270 via the cache bus 241.

Next, regarding the data assurance code used in the present embodiment, the host 100, the host input / output means 208,
A description will be given by taking data transfer relating to the disk input / output means 218 and the disk device 234 as an example. Here, host 1
Writing data from 00 to the disk array 200 is referred to as a disk array write, and reading data from the disk array 200 to the host 100 is referred to as a disk array read. A data flow during disk array write / read will be described. The following description refers to the cache 24
Although there is no request data at 0, that is, a cache miss, the content of the data guarantee code is the same when there is request data in the cache 240, that is, a cache hit.

When writing to the disk array, the host 10
The host input / output unit 208 that has received the write command from 0 notifies the MPU 250 of the command reception. The MPU 250 analyzes the contents of the write command,
Performs address conversion specific to the disk array, and
A transfer list is created for transferring the data sent from 00 to the cache 240 by dividing it. The host input / output unit 208 transfers the divided data to the cache 240 according to the transfer list. The divided data may be in a physically continuous area of the cache 240. Next, the MPU 250 transfers the divided data in the cache 240 to the disk device group 22.
8, 229, and 230 are created as transfer lists for writing. The transfer list is created corresponding to all the disk devices to be transferred. The MPU 250 creates, for example, a transfer list for writing to the disk device 234, and the disk input / output means 218 follows this transfer list,
The divided data is transferred from the cache 240 to the disk device 2
Transfer to.

When reading the disk array, the host 10
The host input / output unit 208 that has received the read command from 0 notifies the MPU 250 of the command reception. The MPU 250 analyzes the contents of the read command,
The address conversion unique to the disk array is performed, the storage location of the requested data distributed and stored in the disk device groups 228, 229, and 230 is specified, and a transfer list corresponding to all the disk devices to be read is created. .
The MPU 250 creates, for example, a transfer list for transfer from the disk device 234 to the cache 240, and the disk input / output means 218 transfers the divided data from the disk device 234 to the cache 240 according to the transfer list. . Next, the MPU 250 creates a transfer list for transferring the divided data in the cache 240 to the host 100 in a state of being bundled with the original data. The host input / output unit 208 transfers data from the cache 240 to the host 100 according to the transfer list.

As described above, at the time of writing / reading the disk array, the data transfer is performed in a divided state. Therefore, in order to enhance the reliability of the system, the cache 240 and the disk device groups 228, 229,
The data assurance method is used to monitor that writing / reading to / from the 230 has been performed at a normal address. Normally, when the host 100 transfers data to the disk array 200, it writes by designating a logical data block address. Therefore, the value of the logical data block address is added as a data guarantee code for each logical data block corresponding to the address. In the present embodiment, the value of the logical data block address is referred to as LA (Logical Address). The present embodiment can be applied not only to the LA but also to a data guarantee code based on an attribute of data that can specify data to be transferred, such as a transfer source address.

That is, in this embodiment, when data is written to the cache 240 at the time of writing to the disk array, the LA corresponding to the logical data block is added to the logical data block, and the LA is read from the cache 240 and read out from the disk device 234. When writing to the logical data block, the LA value added to the logical data block is compared with the expected value of the LA to check. Also, at the time of reading the disk array, when reading from the disk device 234 and writing it to the cache 240, when reading from the cache 240,
When the data is transferred to "0", the LA value added to the logical data block is compared with the expected value of the LA and inspected. The LA value added to the logical data block is deleted when the data is transferred to the host 100, and is returned to the original data state.

As described above, a data assurance code for identifying a logical data block to be read / written is added to each logical block data, and the reliability of the system is improved by confirming that the read / written address is correct.

Here, a specific example of the LA will be described with reference to FIG. FIG. 2 is an explanatory diagram of a specific example of the LA used in the disk array system according to the first embodiment of the present invention.

Logical data blocks 4000, 4001,
Reference numeral 4002 denotes a part of host data when the host 100 transfers data to the disk array 200, and includes a logical data block 4000 and a logical data block 400.
1, logical data block 4002. LA sections 5000, 5001, and 5002 are logical data block addresses or values representing a part of the logical data block addresses.
001 and 4002. When LA is added as a data guarantee code, each logical data block 400
0, 4001, and 4002,
The logical data block 4000, the LA section 5000, the logical data block 4001, the LA section 5001, the logical data block 4002, and the LA section 5002 are successive data. The extended data 3000, 3001, 3002 is
Logical data blocks 4000, 4001, 40 respectively
02 and the LA units 5000, 5001, and 5002.

Further, as shown in FIG. 1, the cache controller 270
, Disk-side internal bus buffer 272, cache control unit 273, LA adding unit 300, LA deleting unit 310, host-side LA checking unit 330, disk-side LA checking unit 350, host information holding unit 360
And disk information holding means 370.

The host-side internal bus buffer 271 is provided between the host input / output means 208, 209, 210 and the cache 24.
Buffering data transfer between 0. The disk-side internal bus buffer 272 buffers data transfer between the disk input / output means 218, 219, 220 and the cache 240. The cache control unit 273 controls the transfer between the cache 240 and the cache controller 270.

The LA adding means 300 adds LA to the data transferred from the host input / output means 208, 209, 210 to the cache 240, and the operation thereof will be described later in detail with reference to FIG. LA deletion means 3
10 indicates that the host input / output means 20
This deletes the LA added to the data transferred to 8, 209 and 210, and details of the operation will be described later with reference to FIG. Host side LA inspection means 33
0 indicates that the host 240 is in the cache 240
LA added to data transferred to 209 and 210
Is compared with the expected LA to check that they are the same, and details of the operation will be described later with reference to FIG. The disk-side LA inspection unit 350 includes the disk input / output units 218, 219, 220,
This compares the LA added to the data transferred between and the expected LA with each other to check that they are the same, and details of the operation will be described later with reference to FIG.

The host information holding means 360 acquires / holds a host-side internal bus transfer list 400 described later when data is transferred between the host input / output means 208, 209, 210 and the cache 240. The details will be described later with reference to FIG. The disk information holding means 370 includes the disk input / output means 218, 21
9, 220 and the cache 240, when data is transferred between the disk-side internal bus transfer list 44 and the
0 is obtained / retained. For details,
This will be described later with reference to FIG.

Here, the configuration of the host information holding means 360 used in this embodiment will be described with reference to FIG.
The host information holding means 360 stores transfer information parameters of the host based on a host-side internal bus transfer list 400 described later with reference to FIG. The host information holding means 360 includes an LA holding means 320, a LUN holding means 321, a channel number holding means 322, a host number holding means 323, a tag number holding means 324,
A valid information holding unit 325 and transfer address holding unit 3
26. Host information holding means 360
Has a plurality of sets by combining the above-mentioned units 320,..., 326.

LA holding means 320 holds the expected value of LA. The LUN holding unit 321 holds a LUN which is a logical unit number of the disk array as viewed from the host. The channel number holding means 322 holds a channel number for identifying the host input / output means 208, 209, 210 used for transfer. Host number holding means 323
Holds the host number identifying the host that issued the transfer request. The tag number holding unit 324 holds a tag number for identifying a tag of a multiplex command of the host. The LA validity information holding means 325 holds LA validity information for identifying whether addition, inspection, and deletion of LA are performed on the logical data block. The transfer address holding unit 326 holds the address of the cache 240 to be transferred.

Next, the configuration of the disk information holding means 370 used in this embodiment will be described with reference to FIG.
The disk information holding unit 370 stores disk transfer information parameters based on a disk-side internal bus transfer list 440 described later with reference to FIG. The disk information holding unit 370 includes an LA holding unit 340 and an LU
N holding means 341 and channel number holding means 342
, Disk number holding means 343, tag number holding means 344, LA valid information holding means 345, and transfer address holding means 346. The disk information holding means 370 has a plurality of sets by combining the above means 340,..., 346.

The LA holding means 340 holds the expected value of LA. The LUN holding unit 341 holds a LUN which is a logical unit number of the disk array as viewed from the host. The channel number holding means 342 holds a channel number for identifying the disk input / output means 218, 219, 220 used for transfer. Host number holding means 343
Holds the disk number for identifying the disk that issued the transfer request. The tag number holding unit 344 holds a tag number for identifying a tag of a multiplex command of the disk. LA
The valid information holding unit 345 holds LA valid information for identifying whether addition, inspection, and deletion of LA are performed on the logical data block. Transfer address holding means 346
Holds the address of the cache 240 to be transferred.

Next, the configuration and operation of the LA adding means 300 used in the present embodiment will be described with reference to FIG.
The LA adding means 300 adds LA to data transferred from the host input / output means 208, 209, 210 to the cache 240 at the time of disk array write. The LA adding unit 300 includes a counter 301 and a buffer value setting unit 302.

At the time of writing to the disk array, data transferred from the host input / output means 208 is buffered in the host-side internal bus buffer 271. The counter 301
The number of data buffered in the host-side internal bus buffer 271 is counted, and when reaching the count for adding LA, the count is notified to the buffer value setting means 302. The buffer value setting unit 302 acquires the LA from the LA holding unit 320 of the host information holding unit 360 and adds the LA to the data in the host-side internal bus buffer 271 at the timing of receiving the notification from the counter 301. L
The data to which A has been added is controlled by the cache control unit 273 and transferred to the cache 240. In the case of transfer in which a plurality of logical data blocks continue, LA
If the LA value taken into the holding means 320 is incremented by the counter 301, LA can be added continuously. By using the LA adding means 300, the LA can be added to the data without the MPU 250 intervening immediately before the start of the data transfer.

Next, the configuration and operation of the host-side LA inspection means 330 used in this embodiment will be described with reference to FIG. The host side LA checking means 330 compares the LA added to the data transferred from the cache 240 to the host input / output means 208, 209, 210 with the expected LA at the time of reading the disk array, and confirms that they are the same. It is to be inspected. The host-side LA inspection means 330
It includes a counter 331, a buffer value acquisition unit 332, and a comparator 333.

When the disk array is read, the data transferred from the cache 240 by the cache control means 273 is buffered in the host-side internal bus buffer 271. The counter 331 counts the number of data buffered in the host-side internal bus buffer 271,
When the count for acquiring the LA has been reached, the buffer value acquiring unit 332 is notified. The buffer value acquisition unit 332 includes:
At the timing when the notification from the counter 331 is received, the LA added to the data in the host-side internal bus buffer 271 is acquired and transmitted to the comparator 333. Comparator 333
Obtains the LA from the LA holding unit 320 of the host information holding unit 360 and compares the LA with the LA received from the buffer value obtaining unit 332. If the LAs compared by the comparator 333 are not the same, the host-side LA
The inspection unit 330 performs the LA inspection by, for example, notifying the MPU 250 of an error. In the case of a transfer in which a plurality of logical data blocks continue, if the LA value taken into the LA holding means 320 is incremented by the counter 301, the LA can be inspected continuously. By using the host-side LA inspection unit 330, it is possible to inspect the LA added to the data without the MPU 250 immediately before the start of data transfer.

Next, the configuration and operation of the LA deleting unit 310 used in the present embodiment will be described with reference to FIG.
The LA deletion unit 310 sends the host input / output units 208, 209,
This is to delete the LA added to the data transferred to 210. The LA deleting unit 310 includes a counter 311
And a buffer value deleting unit 312.

At the time of reading the disk array, data transferred from the cache 240 by the cache control means 273 is buffered in the host-side internal bus buffer 271. The counter 311 counts the number of data buffered in the host-side internal bus buffer 271,
When the count for deleting the LA has been reached, the buffer value deleting unit 312 is notified. The buffer value deletion means 312
L added to the data in the host-side internal bus buffer 271 at the timing of receiving the notification from the counter 311
Delete A.

Next, the configuration and operation of the disk-side LA inspection means 350 used in this embodiment will be described with reference to FIG. The disk-side LA inspection means 350 is used for writing / reading the disk array.
The LA added to the data transferred between the caches 240, 219, 220 and the cache 240 is compared with the expected LA, and it is checked that they are the same. The disk-side LA inspection unit 350 includes a counter 351, a buffer value acquisition unit 352, and a comparator 353.

During a disk array write, data transferred from the cache 240 by the cache control means 273 is buffered in the disk-side internal bus buffer 272. Further, at the time of reading the disk array, the data transferred from the disk input / output means 218 is buffered in the disk-side internal bus buffer 272.

The counter 351 counts the number of data buffered in the disk-side internal bus buffer 272, and notifies the buffer value acquiring means 352 when the count for acquiring LA has been reached. Buffer value acquisition means 35
2 acquires the LA added to the data in the disk-side internal bus buffer 272 at the timing of receiving the notification from the counter 351 and sends it to the comparator 353. The comparator 353 acquires the LA from the LA holding unit 340 of the disk information holding unit 370, and
2. Compare that the LA received from 2 is the same. If the LAs compared by the comparator 353 are not the same,
The disk-side LA inspection unit 350 includes, for example, the MPU 25
By performing an error notification to 0, the LA check is executed. In the case of a transfer in which a plurality of logical data blocks continue, if the LA value taken into the LA holding means 320 is incremented by the counter 351, the L value is continuously set.
A can be inspected. By using the disk-side LA inspection means 350, the MPU
LA added to data without the intervention of 250
Can be tested.

Here, returning to FIG.
Are the disk array control means 261 and the LA setting means 2
62, a transfer list storage unit 263, and a command information storage unit 264. The disk array control means 261 is used by the MPU 250 to execute disk array control. The LA setting unit 262 sets the LA in the host-side internal bus transfer list 400 and the disk-side internal bus transfer list 440 described later with reference to FIG.
The transfer list storage unit 263 is a host
8, 209, 210 and disk input / output means 21
8, 219 and 220 store a host-side internal bus transfer list 400 and a disk-side internal bus transfer list 440 which are referred to for executing data transfer. The command information storage unit 264 stores the host input / output units 208, 209, and 21.
0 and disk input / output means 218, 219, 220
Command information is stored.

Here, the configuration of the transfer list storage means 263 will be described with reference to FIG. The transfer list storage unit 263 includes a host-side internal bus transfer list 400 and a disk-side internal bus transfer list 440. The host-side internal bus transfer list 400 contains the host input / output unit 2
08 is obtained by using the DMA 211 to execute the data transfer. The disk-side internal bus transfer list 440 is obtained by using the DMA 221 for the disk input / output unit 218 to execute data transfer.

Note that the transfer list similar to the host-side internal bus transfer list 400 is also stored in the transfer list storage unit 263 for the host input / output units 209 and 210.
Hereinafter, only the transfer list of the host input / output unit 208 will be described. Also, disk input / output means 219, 220
, A transfer list similar to the disk-side internal bus transfer list 440 is stored in the transfer list storage unit 263. Hereinafter, only the transfer list of the disk input / output unit 218 will be described. Host-side internal bus transfer list 400
And a plurality of disk-side internal bus transfer lists 440 may exist. Host-side internal bus transfer list 4
00 and the disk-side internal bus transfer list 440 are the MPU
250, and stores it in the transfer list storage unit 263. Host input / output means 208, 209, 210;
The disk input / output units 218, 219 and 220 have a transfer function, and the cache controller 270 operates according to the transfer commands received from the host input / output units 208, 209 and 210 and the disk input / output units 218, 219 and 220. It just sends and receives data. Therefore, since the transfer list acquisition and the data transfer are performed by the host input / output means 208 and the disk input / output means 218, the intervention of the MPU 250 is not required until the data transfer is completed.

The host-side internal bus transfer list 400 stores a host-side internal bus transfer size 410 for specifying the address of the cache 240 and m host-side internal bus transfer sizes 420 for specifying the data transfer size. is there. m is a natural number. Host-side internal bus transfer address 410 and host-side internal bus transfer size 42
0 is added to the host side list 1000, 1001,
1002, 1003,...

Host-side list 1000, 1001, 10
, The internal bus transfer address 4 of the host side
10 each have LA as a host transfer parameter.
LUs such as 1200, 1201, 1202, 1203,.
N1220, 1221, 1222, 1223,... And channel numbers 1240, 1241, 1242, 124
3,... And host numbers 1260, 1261, 1262
1263,... And tag numbers 1280, 1281, 128
2, 1283,... And LA valid information 1300, 130
, And the transfer address 140
0, 1401, 1402, 1403, ... are stored. In addition, host-side lists 1000, 1001, 1002, 1
The host-side internal bus transfer size 420 of 003,.
Transfer sizes 1600, 1601, 1602, 1 respectively
603,... Are stored.

LUNs 1220, 1221, 1222, 1
. 223,...
LUN (Logical Unit Number) designated by 10, 120
r). Channel numbers 1240, 1241, 12
Are identification numbers of the host input / output means 208, 209, 210 used at the time of the data write request. Host numbers 1260, 1261, 126
Are identification numbers of the hosts 100, 110, and 120 that have requested data write / read.
Tag numbers 1280, 1281, 1282, 1283, ...
Is the tag number of the command issued by the host 100, 110, or 120. LA validity information 1300, 1301,
1302, 1303,... Are information indicating that the data to be transferred is ordinary data or parity data for ordinary data, and that LA is valid for ordinary data. is there.

In the conventional system, the transfer addresses 1400, 1401,
Are stored, but in the present embodiment, the above-described host transfer parameters are stored in addition to the transfer address. The portion storing the host transfer parameter is, for example, an upper bit of the address, and is an area that does not affect the designation of the address of the cache 240. Further, the address of the portion where the host controller stores the host transfer parameter may not be regarded as the address for the transfer by the cache controller 270.

When the host input / output means 208 performs data transfer using the host-side internal bus transfer list 400, the value of the host-side internal bus transfer address 410 is used as it is for the address specification, and the value of the host-side internal bus transfer address 410 is transferred to the host-side internal bus 212. Sent out. Therefore, the host side internal bus transfer address 4
The cache controller 270 receiving the value of 10
Are LA1200, 1201, 1202, 1203, ...
And transfer addresses 1400, 1401, 1402, 140
By making it possible to recognize 3,..., It becomes possible to acquire the LA immediately before starting the data transfer. Therefore, as described above, the cache controller 270
The LA can be obtained and held by the LA holding means 320 in the inside.

In summary, in the present embodiment, by setting the LA in the host-side internal bus transfer list 400, from the creation of the host-side internal bus transfer list 400 to the end of data transfer. Does not require the intervention of the MPU, and adds LA to the transfer data between the host input / output means 208 and the cache 240.
The cache controller 270 can execute the A inspection and the LA deletion. Further, the cache controller 270 uses the values of the received internal bus transfer address 410 as LUN 1220, 1
..., channel number 1
, 240, 1241, 1242, 1243,... And host numbers 1260, 1261, 1262, 1263,.
Tag numbers 1280, 1281, 1282, 1283, ...
And LA valid information 1300, 1301, 1302, 13
03,..., And each of them is
1, a channel number holding unit 322, a host number holding unit 323, a tag number holding unit 324, and an LA effective information holding unit 325. Therefore, the cache controller 270 determines the information on the transfer parameters of the command received from the host-side internal bus 212 as LUN, channel number, host number, tag number,
It is possible to discriminate whether the LA is valid or not, and even if the command execution is interrupted and resumed on the way, LA addition, LA inspection, and LA deletion of the received data can be performed. That is, the host input / output means 208, 209, 210
The disk input / output units 218, 219, and 220 have a transfer function, and the cache controller 270
Are host input / output means 208, 209, 210;
It only sends and receives data according to the transfer command received from the disk input / output means 218, 219, 220. Therefore, there is no problem if the command is executed without interruption from the command reception to the data transfer and only one command is issued at the same time. However, commands are issued from multiple hosts and disk devices in a multiplex manner, and In the case where the execution is interrupted and resumed, the cache controller 270 cannot determine which command was previously executed to which transfer, and the LA addition, the LA inspection, and the LA deletion cannot be performed. Even in such a case, in the present embodiment, such a problem does not occur because the cache controller 270 can distinguish the command received from the host-side internal bus 212 for each transfer parameter. . Further, the cache controller 270 can distinguish the command received from the disk-side internal bus 222 for each transfer parameter.

Next, the disk-side internal bus transfer list 44
0 indicates a disk-side internal bus transfer address 450 that specifies the address of the cache 240 and a disk-side internal bus transfer size 460 that specifies the data transfer size.
Each of them stores n pieces. n is a natural number.
A combination of the disk-side internal bus transfer address 450 and the disk-side internal bus transfer size 460 is referred to as a disk-side list 2000, 2001, 2002, 2003,.

Disk side list 2000, 2001, 2
., 2003,..., LA-2200, 2201, 2022, 2203,.
And LUNs 2220, 2221, 2222, 2223,
... and channel numbers 2240, 2241, 242,
2243,... And disk numbers 2260, 2261, 2
262, 2263,... And tag numbers 2280, 228
, 1,282,2283,... And LA valid information 230
., And transfer addresses 2400, 2401, 2402, 2403,. Also, the disk-side lists 2000, 2001, 2
., 2003,..., Disk-side internal bus transfer sizes 460 include transfer sizes 2600, 2601,
2602, 2603,... Are stored.

LUNs 2220, 2221, 2222, 2
. 223,...
LUN (Logical Unit Number) designated by 10, 120
r). Channel numbers 2240, 221, 22
Are identification numbers of the disk input / output means 218, 219, 220 used for the data write request. Disk numbers 2260, 2261, 22
Are identification numbers of the disk devices 234, 235, 236,... Which have requested data write / read. Tag numbers 2280, 2281, 2282
Are disk devices 234, 235, 23
Are the tag numbers of the commands issued. The LA valid information 1300, 1301, 1302, 1303,.
Whether the data being transferred is plain data,
This is information indicating that LA is valid for ordinary data by identifying whether the data is parity data for ordinary data.

In the conventional system, the transfer addresses 2400 and 240
Are stored, but in the present embodiment, the above-described disk transfer parameters are stored in addition to the transfer address. The portion for storing the disk transfer parameters is, for example, the upper bits of the address and an area that does not affect the designation of the address of the cache 240. In addition, the address of the portion where the cache controller 270 stores the disk transfer parameter may not be regarded as the address for transfer.

When the disk input / output means 218 transfers data using the disk-side internal bus transfer list 440, the value of the disk-side internal bus transfer address 450 is the same value as the address for specifying the disk-side internal bus 2
22. Therefore, the cache controller 270, which has received the value of the disk-side internal bus transfer address 450, determines whether the LA 2200, 2201, 2022, 2
203,... And transfer addresses 2400, 2401, 240
By recognizing 2,2403, ...
The LA can be obtained immediately before starting the data transfer. Therefore, as described above, the LA can be acquired and held by the LA holding means 340 in the cache controller 270.

In summary, in the present embodiment, by setting LA in the disk-side internal bus transfer list 440, the disk-side internal bus transfer list 440 is set.
From the time the data transfer is completed until the data transfer ends.
U is not required, and the disk input / output means 21
8 can be performed by the cache controller 270 on the data transferred between the cache controller 240 and the cache 240. In addition, the cache controller 270 uses the values of the received disk-side internal bus transfer address 450 as the disk transfer parameters as LUNs 2220, 2221 and 2221.
.., And channel numbers 2240, 2
, 241, 242, 2243,...
, And tag numbers 2280, 2281, 2282, 2283,..., LA
Effective information 2300, 2301, 2302, 2303, ...
, The LUN holding means 341, the channel number holding means 342, and the disk number holding means 34
3, tag number holding means 344, LA valid information holding means 3
Can be acquired and held at 45. Therefore, the cache controller 270 can distinguish the LUN, the channel number, the disk number, the tag number, and whether the LA is valid or not as the information on the disk transfer parameter of the command received from the disk-side internal bus 222. Even when the execution is interrupted and resumed, the LA inspection of the received data can be performed. As described above, in the present embodiment, the host input / output unit 2
08, 209, 210 and disk input / output means 21
MPU to use the transfer functions of
250 can be reduced, and the performance as a disk array can be improved. It is to be noted that LA addition and LA inspection can be easily performed on redundant data as a disk array by using the units of the present embodiment.

Next, the disk array write / read operation in the disk array system according to the present embodiment will be described with reference to FIGS. First, FIG.
The operation at the time of the disk array write of the present embodiment will be described with reference to FIGS. FIG. 10 is a flowchart showing data transfer from the host input / output unit 208 to the cache 240. FIG.
9 is a flowchart showing data transfer from a disk to a disk input / output unit 218. Note that, as described above, the cache controller 270 communicates with the host-side internal bus 21.
2 or when a command is received from the disk-side internal bus 222, the transfer can be distinguished by the transfer parameters included in the transfer list, and the description of the operation is omitted. The redundant data generation of the disk array is omitted because it can be realized without any problem by the existing technology.

First, the transfer flow of the disk array write on the host side internal bus will be described with reference to FIG. 10, and FIG. 10 will be described separately for the processing of the MPU 250, the host input / output means 208, and the cache controller 270. It is.

When a data write request is issued from an application or the like on the host 100, the host input / output means 208 receives the host write command in step s540, and in step s541, the command information storage means in the memory 260 The contents of the write command are transferred to the H.264, and in step s542, the MPU
An interrupt signal is issued to 250.

Upon receiving the interrupt signal in step s520, the MPU 250 analyzes the contents of the write command in the command information storage means 264 in step s521, and performs address conversion unique to the disk array. Next, in step s522, the MPU 250 creates a transfer command to be used by the host input / output means 208 and stores it in the command information storage means 264. In step s523, creates the host-side internal bus transfer list 400 in which LA is set. Transfer list storage means 26
3 is stored.

On the other hand, the host input / output means 208 issues an interrupt signal to the MPU 250 in step s542, and then repeatedly references in step s543 whether a transfer command or the host-side internal bus transfer list 400 has been created. . Then, in step s544, the host input / output means 208 acquires the host-side internal bus transfer list 400 if it exists, and
At 545, a write command for the host-side internal bus 212 is issued to the cache controller 270.

On the other hand, the cache controller 270
In step s560, when a write command for the host-side internal bus 212 is received, in step s561, the LA is acquired from the host-side internal bus transfer address 410 of the received write command, and held in the LA holding unit 320. Next, the host input / output unit 208 transmits the data of the host-side internal bus 212 to the cache controller 270 in step s546, and the cache controller 270 receives the data in step s562. As a result, the data on the host-side internal bus 212 is transferred from the host input / output means 208 to the cache controller 270.

Next, the cache controller 270
In step s563, the LA is added, and in step s564, the data is transmitted to the cache 240. In the case of a transfer in which a plurality of logical data blocks 4000 continue, the LA
If the value is incremented by the counter 301, LA can be added continuously.

On the other hand, the host input / output means 208, which has completed the data transfer, determines in step s547 that the MPU 25
Issue an interrupt signal to 0. Upon receiving the interrupt signal in step s524, MPU 250 performs termination processing in step s525.

Next, the transfer flow of the disk array write to the disk-side internal bus will be described with reference to FIG. 11, and FIG. 11 is described separately for the processing of the MPU 250, the disk input / output means 218, and the cache controller 270. It is.

From the cache 240 to the disk device 234
When it becomes necessary to write data to the MPU 250,
In step s620, the disk input / output unit 218
Is created and stored in the command information storage means 264. In step s621, the disk-side internal bus transfer list 440 in which the LA is set is created and stored in the transfer list storage means 263.

On the other hand, in step s640, the disk input / output means 218 is in a waiting state,
At 641, it is repeatedly referred to whether a transfer command or a disk-side internal bus transfer list 440 has been created. Next, in step s642, the disk input / output unit 218 acquires the disk-side internal bus transfer list 440 if it exists, and issues a read command for the disk-side internal bus 222 to the cache controller 270 in step s643.

On the other hand, the cache controller 270
In step s660, the disk-side internal bus 222
Is received, in step s661, the LA is acquired from the disk-side internal bus transfer address 450 of the received read command, and the LA holding unit 34
Hold at 0. Next, the cache controller 270
Receives the data from the cache 240 in step s662, and checks the LA in step s663. In the case of a transfer in which a plurality of logical data blocks 4000 continue, the L
If the value A is incremented by the counter 351, the LA can be inspected continuously.

Further, the cache controller 270
In step s664, the disk input / output unit 2
In addition to transmitting the data of the disk-side internal bus 222 to the disk 18, the disk input / output
At 4, the data is received. As a result, the data on the host-side internal bus 212 is transferred from the cache controller 270 to the disk input / output unit 218.

Next, the disk input / output means 218 that has completed the data transfer determines in step s645 that the MPU 2
An interrupt signal is issued to 50. On the other hand, the MPU 250
In step s622, when receiving the interrupt signal,
In step s623, end processing is performed.

As described above, the processing of the MPU is not performed until the data transfer is completed after the transfer list is created, and the LA addition and the LA inspection can be executed without the intervention of the MPU.

Next, the operation at the time of reading the disk array of this embodiment will be described with reference to FIGS. FIG. 12 is a flowchart showing data transfer from the cache 240 to the host input / output unit 208, and FIG. 13 is a flowchart showing data transfer from the disk input / output unit 218 to the cache 240.

First, the transfer processing of the disk array read from the host side internal bus will be described with reference to FIG. 12, and FIG. 12 will be described separately for the processing of the MPU 250, the host input / output means 208, and the cache controller 270. It is. When a data read request is issued from an application or the like on the host 100, the host input / output unit 208 receives the host read command in step s740, and reads the command to the command information storage unit 264 in the memory 260 in step s741. The contents of the command are transferred, and in step s742, MP
An interrupt signal is issued to U250.

Upon receiving the interrupt signal in step s720, the MPU 250 analyzes the contents of the read command in the command information storage means 264 in step s721, and performs an address conversion unique to the disk array. Next, in step s722, the MPU 250 creates a transfer command used by the host input / output unit 208 and stores it in the command information storage unit 264. In step s723, creates the host-side internal bus transfer list 400 in which LA is set. Transfer list storage means 26
3 is stored.

On the other hand, the host input / output means 208 issues an interrupt signal to the MPU 250 in step s742, and then repeatedly references in step s743 whether a transfer command or the host-side internal bus transfer list 400 has been created. . Then, in step s744, the host input / output means 208 acquires the host-side internal bus transfer list 400 if it exists, and
At 745, a read command for the host-side internal bus 212 is issued to the cache controller 270.

On the other hand, the cache controller 270
In step s760, when the read command of the host-side internal bus 212 is received, in step s761, the LA is acquired from the host-side internal bus transfer address 410 of the received read command, and stored in the LA holding unit 320. Next, the cache controller 270 receives the data from the cache 240 in step s762, and checks the LA in step s763. In the case of transfer in which a plurality of logical data blocks 4000 continue, if the LA value taken into the LA holding unit 320 is incremented by the counter 331, the LA can be inspected continuously. Next, the cache controller 270 deletes the LA in Step s764.

Further, the cache controller 270
In step s765, the host input / output
8 and the host input / output unit 208 receives the data in step s746. Thereby, the data of the host-side internal bus 212 is transferred to the cache controller 2.
70 to the host input / output means 208.

Then, the host input / output means 208 having completed the data transfer determines in step s747 that the MPU2
An interrupt signal is issued to 50. On the other hand, the MPU 250
In step s724, when receiving the interrupt signal,
In step s725, end processing is performed.

The above operation of FIG.
Is the data for which a read request has been made, that is, a cache hit. In the case of a cache miss where the requested data is not in cache 240, FIG.
After the step s720 of step 2, the operation of FIG. 13 described below is performed, and then the operation proceeds to step s721 of FIG.

Next, the transfer processing of the disk array read on the disk side internal bus will be described with reference to FIG. 13, and in FIG. 13, the processing of the MPU 250, the disk input / output means 218, and the cache controller 270 will be described separately. I have.

The cache 240 from the disk device 234
When it is necessary to read data from the MPU 250,
In step s820, the disk input / output unit 218
Is created and stored in the command information storage unit 264. In step s821, the disk-side internal bus transfer list 440 in which the LA is set is created and stored in the transfer list storage unit 263.

At this time, the disk input / output means 21
8 is a waiting state in step s840,
In step s841, a transfer command or
It is repeatedly referred to whether the disk-side internal bus transfer list 440 has been created. Next, the disk input / output means 2
In step s842, if there is a disk-side internal bus transfer list 440 in step s842, the process proceeds to step s84.
At 3, the write command for the disk-side internal bus 222 is issued to the cache controller 270.

On the other hand, the cache controller 270
In step s860, the disk-side internal bus 222
When the write command is received, in step s861, the LA is acquired from the disk-side internal bus transfer address 450 of the received write command, and the LA holding unit 34 is acquired.
Hold at 0.

Next, the disk input / output means 218 determines in step s844 that the cache controller 270
The cache controller 270 transmits the data of the disk-side internal bus 222 to the
At 2, the data is received. As a result, the data on the disk-side internal bus 212 is transferred from the disk input / output means 208 to the cache controller 270.

Next, the cache controller 270
In step s863, the data is sent to the cache to the disk input / output unit 208 in step s864 while checking the LA. In the case of a transfer in which a plurality of logical data blocks 4000 continue, the LA holding unit 34
If the LA value taken into 0 is incremented by the counter 351, the LA can be inspected continuously.

On the other hand, the disk input / output means 218 that has completed the data transfer determines in step s845 that the MPU 2
An interrupt signal is issued to 50. On the other hand, the MPU 250
In step s822, upon receiving the interrupt signal,
In step s823, end processing is performed.

As described above, there is no MPU process between the time the transfer list is created and the time the data transfer is completed, and LA inspection and LA deletion can be executed without the intervention of the MPU.

As described above, according to the present embodiment, by setting the LA in the transfer list, even when the host input / output unit with the transfer function and the disk input / output unit are used, the LA is set. Addition, LA inspection, and LA deletion can be realized, and high performance can be achieved when a data assurance code is added. Also, the transfer parameters LUN, channel number, host number,
By setting the disk number, tag number, and LA validity information, host I / O means with a transfer function and disk I / O means are used, and commands are issued in multiplex from many hosts and disk devices. Also, even in a state where execution is interrupted and resumed in the middle, the cache controller can distinguish commands, and can perform LA addition, LA inspection, and LA deletion of received data. .

The hosts 100, 110, and 120
Interfaces between the host input / output means 208, 209, 210 and between the disk device groups 228, 229, 230 and the disk input / output means 218, 219, 220 are, for example, fiber channel, SCSI
However, other interfaces can be used. The buses of the host-side internal bus 212 and the disk-side internal bus 222 may be, for example, a PCI having a width of 64 bits. However, if the assignment of the address area of the cache 240 is changed, a bus having a width of 32 bits may be used.
A CI or other bus could also be used. Further, in this embodiment, the LA is added to the end of the logical data block. However, the LA may be added to any location as long as it can be determined from the position of the logical data block. Further, in the present embodiment, the data assurance code is a logical data block address or a part thereof, but any other value may be used as long as the attribute of the divided data can be specified. The cache 240 is a memory that can be read and written at a high speed, and the type of the memory is not limited.

Further, in this embodiment, it is possible to use together with the data guarantee method by LRC.

Next, the configuration and operation of the disk array system according to the second embodiment of the present invention will be described with reference to FIGS. First, referring to FIG.
The configuration of the disk array system according to the present embodiment will be described. The same reference numerals as those in FIG. 1 indicate the same parts.

Here, for the sake of simplicity, the description will focus on differences from the first embodiment shown in FIG.
As shown in FIG. 14, in the present embodiment, the cache 240 includes a host-side LA storage unit 242 and a disk-side LA storage unit 243. The cache controller 270 includes an LA acquisition unit 380.

The host-side LA storage means 242 and the disk-side LA storage means 243 are used for setting the LA by the LA setting means 262 described later, which is executed by the MPU 250. This LA is set in the transfer list in the embodiment shown in FIG. Host side LA storage means 242 and disk side LA storage means 243
Can store at least one LA.

The LA acquisition means 380 acquires the LAs set in the host-side LA storage means 242 and the disk-side LA storage means 243, and holds the LAs in the LA holding means 320, 340.

Next, referring to FIG. 15, the transfer list storage means 2 used in the disk array system according to the present embodiment will be described.
The configuration of 63 will be described. The same reference numerals in FIG. 9 indicate the same parts.

Here, for the sake of simplicity, the description will focus on the differences from the first embodiment shown in FIG.
The transfer list storage means 263 includes a host-side internal bus transfer list 400 and a disk-side internal bus transfer list 440, as in the embodiment shown in FIG.

The host-side internal bus transfer list 400 is similar to the embodiment shown in FIG.
0, 1001,... However,
As the host transfer parameters in the host-side internal bus transfer address 410, LA points 1320, 1321,
.. Are stored. The disk-side internal bus transfer list 440 stores the disk-side lists 2000 and 2 similarly to the embodiment shown in FIG.
001,... However, as the disk transfer parameters in the disk-side internal bus transfer address 450, LA points 2320, 2321, and
322, 2323,... Are stored.

Next, the operation of the disk array system according to the present embodiment will be described. Here, for the sake of simplicity, the description will focus on the differences from the first embodiment shown in FIGS. 1 and 9.

LA setting means 2 provided in memory 260
62 sets the LA in the host-side LA storage means 242 or the disk-side LA storage means 243 in the cache 240 unlike the embodiment shown in FIG.
In the host-side internal transfer bus 400 or the disk-side internal bus transfer list 440, the host-side LA storage means 24
2, and the LA set in the disk-side LA storage unit 243.
Set the pointer address of

The host information holding means 360 acquires and holds the host-side internal bus transfer list 400 when data is transferred between the host input / output means 208, 209, 210 and the cache 240. LA holding means 320
Temporarily store the LA pointer. When the LA pointer is stored, the LA holding unit 320 uses the cache control unit 273 to store the LA pointer from the host-side LA storage unit 242 in the cache 240 based on the LA pointer.
Is acquired and stored in the LA holding unit 320.

The disk information holding means 370 includes the disk input / output means 218, 219, 220 and the cache 240.
When the data is transferred between the internal bus transfer list 440 and the internal bus transfer list 440, the disk-side internal bus transfer list 440 is acquired / held. LA holding means 34
At 0, the LA pointer is temporarily stored. When the LA pointer is stored in the LA holding unit 340, the LA acquisition unit 380 uses the cache control unit 273 to store the LA pointer in the cache 240 based on the LA pointer.
The LA is acquired from the storage unit 243, and the LA holding unit 340 is acquired.
To be stored.

Next, the disk array write / read operation in the disk array system according to the present embodiment will be described with reference to FIGS. First, an operation during a disk array write will be described with reference to FIGS. Here, for simplicity of explanation,
The following description focuses on the differences from the first embodiment.

First, the transfer flow of the disk array write of FIG. 10 through the host-side internal bus will be described. In the present embodiment, in step 523, the MPU 250 uses the LA
Is set in the host-side LA storage means 242 in the
Thereafter, the host-side internal bus transfer list 400 in which the LA pointer is set is created and stored in the transfer list storage unit 263.

Also, the cache controller 270
In step 561, an LA pointer is acquired from the host-side internal bus transfer address 410 of the received write command, and the LA acquisition means 380 uses the LA-pointer to store the LA pointer in the cache 240 based on the LA pointer.
And obtains the LA and stores it in the LA holding unit 320. Other processes are the same as in the first embodiment.

Next, a description will be given of the transfer flow of the disk-array internal bus of the disk array write of FIG. In the present embodiment, the MPU 250 uses the LA setting unit 262 to execute the cache 24
0 is set in the disk-side LA storage means 243 in the disk-side LA, and then the disk-side internal bus transfer list 440 in which the LA pointer is set is created.
3 is stored.

Also, the cache controller 270
In step 661, the LA acquisition unit 380 acquires the LA pointer from the disk-side internal bus transfer address 450 of the received read command, and based on the LA pointer, stores the LA pointer in the disk-side LA storage unit 24 in the cache 240.
3 is acquired from the LA and stored in the LA holding unit 340.
Other processes are the same as in the first embodiment.

As described above, in the present embodiment, there is no MPU process from the time the transfer list is created until the data is completed.
LA addition and LA inspection can be performed without the intervention of U.

Next, the operation at the time of reading the disk array will be described with reference to FIGS. here,
For the sake of simplicity, the description will focus on the differences from the first embodiment.

First, the transfer flow of the disk array read of the host side internal bus in FIG. 12 will be described. In the present embodiment, in step 723, the MPU 250 uses the LA
Is set in the host-side LA storage means 242 in the
Thereafter, the host-side internal bus transfer list 400 in which the LA pointer is set is created and stored in the transfer list storage unit 263.

Also, the cache controller 270
In step 761, the LA pointer is acquired from the host-side internal bus transfer address 410 of the received read command, and the LA acquisition unit 380 determines the host-side LA storage unit 242 in the cache 240 based on the LA pointer.
And obtains the LA and stores it in the LA holding unit 320. Other processes are the same as in the first embodiment.

Next, a description will be given of a transfer flow of the disk-side internal bus of the disk array read of FIG. In the present embodiment, in step 821, the MPU 250 uses the LA
0 is set in the disk-side LA storage means 243 in the disk-side LA, and then the disk-side internal bus transfer list 440 in which the LA pointer is set is created.
3 is stored.

Also, the cache controller 270
In step 661, the LA acquisition unit 380 acquires an LA pointer from the disk-side internal bus transfer address 450 of the received write command, and based on the LA pointer, stores the LA pointer in the disk-side LA storage unit 24 in the cache 240.
3 is acquired from the LA and stored in the LA holding unit 340.
Other processes are the same as in the first embodiment.

As described above, in the present embodiment, there is no MPU processing from the creation of the transfer list to the end of the data.
LA addition and LA inspection can be performed without the intervention of U.

As described above, in the first embodiment, the MPU 250 sets the substance of the LA in the transfer list, whereas in the present embodiment, the MPU 250
The entity of A is set in the cache 240 and the cache 24
The pointer address of the LA on 0 is set in the transfer list. Further, in the first embodiment, the cache controller 270 acquires the entity of the LA from the transfer list, whereas in the present embodiment, the cache controller 270 acquires the pointer address of the LA from the transfer list, and Cache 2 based on address
Acquire the LA from 40. The operation after the cache controller 270 acquires the LA is the same as that of the first embodiment.

As described above, by setting the LA in the cache and setting the LA pointer in the transfer list, even when the host I / O unit with the transfer function and the disk I / O unit are used, the MPU is interposed. Without adding, LA addition, LA inspection, and LA deletion can be realized, and high performance can be achieved when a data guarantee code is added. Also, LU, which is a transfer parameter, is included in the transfer list.
By setting N, channel number, host number, disk number, tag number and LA effective information, host input / output means with transfer function and disk input / output means can be used, and a large number of hosts and disks can be used. Even in a state where multiple commands are issued from the device and the execution is interrupted and resumed in the middle, the cache controller can distinguish the commands, and can add LA to the received data, check the LA, LA deletion can be performed.

The hosts 100, 110, and 120
Interfaces between the host input / output means 208, 209, 210 and between the disk device groups 228, 229, 230 and the disk input / output means 218, 219, 220 are, for example, fiber channel, SCSI
However, other interfaces can be used. The buses of the host-side internal bus 212 and the disk-side internal bus 222 may be, for example, a PCI having a width of 64 bits. However, if the assignment of the address area of the cache 240 is changed, a bus having a width of 32 bits may be used.
A CI or other bus could also be used. Further, in this embodiment, the LA is added to the end of the logical data block. However, the LA may be added to any location as long as it can be determined from the position of the logical data block. Further, in the present embodiment, the data assurance code is a logical data block address or a part thereof, but any other value may be used as long as the attribute of the divided data can be specified. The cache 240 is a memory that can be read and written at a high speed, and the type of the memory is not limited.

Further, in the present embodiment, it is possible to use together with the data guarantee method by LRC.

[0118]

According to the present invention, a guarantee code based on data attributes such as LA can be added to data, and the transfer efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a disk array system according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a specific example of an LA used in the disk array system according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a configuration of a host information holding unit used for a disk array configuring the disk array system according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a configuration of a disk information holding unit used for a disk array configuring the disk array system according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a configuration of an LA adding unit used for a disk array configuring the disk array system according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a host side L used for a disk array configuring the disk array system according to the first embodiment of the present invention;
FIG. 3 is an explanatory diagram illustrating a configuration of an A inspection unit.

FIG. 7 is an explanatory diagram showing a configuration of an LA deletion unit used for a disk array configuring the disk array system according to the first embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a configuration of a disk-side LA inspection unit used for a disk array configuring the disk array system according to the first embodiment of the present invention.

FIG. 9 is an explanatory diagram showing a configuration of a transfer list storage means used for a disk array constituting the disk array system according to the first embodiment of the present invention.

FIG. 10 is a flowchart illustrating data transfer from a host input / output unit to a cache in the disk array system according to the first embodiment of the present invention.

FIG. 11 is a flowchart showing data transfer from the cache to the disk input / output means in the disk array system according to the first embodiment of the present invention.

FIG. 12 is a flowchart illustrating data transfer from a cache to a host input / output unit in the disk array system according to the first embodiment of the present invention.

FIG. 13 is a flowchart illustrating data transfer from a disk input / output unit to a cache in the disk array system according to the first embodiment of the present invention.

FIG. 14 is a block diagram illustrating a configuration of a disk array system according to a second embodiment of the present invention.

FIG. 15 is an explanatory diagram showing a configuration of a transfer list storage unit used for a disk array configuring a disk array system according to a second embodiment of the present invention.

[Explanation of symbols]

 100, 110, 120 Host 130 Bus switch 200 Disk array 208, 209, 210 Host input / output means 211, 221 DMA 218, 219, 220 Disk input / output means 228, 229, 230 Disk group 234 , 235, 236 disk device 240 cache 250 MPU 260 memory 261 disk array control unit 262 LA setting unit 263 transfer list storage unit 264 command information storage unit 270 cache controller 271 host internal bus buffer 272: Disk-side internal bus buffer 273: Cache control means 300: LA adding means 310: LA deleting means 320, 340: LA holding means 330: Host-side LA checking means 350: Disk-side LA checking means 4 0 ... host-side internal bus transfer list 440 ... disk-side internal bus transfer list 3000,3001,3002 ... extension data 4000,4001,4002 ... logical data blocks 5000,5001,5002 ... LA portion

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masayuki Yamamoto 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside Hitachi, Ltd.System Development Laboratory (72) Inventor Jun Matsumoto 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Stock Company (72) Inventor Yasuyuki Yasuyuki 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture, Japan Incorporated Hitachi System Development Laboratory (72) Masahiko Sato 2880 Kozu, Kozu, Odawara City, Kanagawa Prefecture Co., Ltd. F-term in Hitachi Storage Systems Division (reference) 5B018 GA01 GA04 HA14 HA40 MA14 QA16 5B065 BA01 CA11 CA30 CH01 EA02 EA12 EA21

Claims (5)

[Claims] 1. A disk array system for writing data from a host to a disk array having a plurality of disk devices arranged in an array and reading data written to the disk array to the host. A host input / output unit having a transfer function of performing input / output with the host, a cache for temporarily holding data, a guarantee code holding unit for holding a value specifying a guarantee code based on the attribute of the data, And an MPU for creating a transfer list of the host input / output means. When a data write request is issued from the host, the MPU creates a transfer list referred to by the host input / output means, and stores data in the transfer list. Set a value that specifies the guarantee code based on the attribute, and the host input / output The data is transmitted to the cache according to the transfer list including a value specifying a guarantee code based on the property, and the guarantee code holding unit specifies a guarantee code based on an attribute of the data when the data is transmitted to the cache. A value for specifying the guarantee code based on the attribute of the data, and the guarantee code adding means caches the value for specifying the guarantee code based on the attribute of the data stored in the guarantee code holding means. A disk array system characterized by adding data to data written to a disk. 2. The disk array system according to claim 1, wherein said disk array further comprises host-side checking means for checking a value for specifying a guarantee code based on a data attribute, and wherein a data read request from the host is provided. In some cases, the MPU creates a transfer list referred to by the host input / output means, sets a value specifying a guarantee code based on data attributes in the transfer list, and the host input / output means Receiving the data from the cache according to the transfer list including a value specifying a guarantee code based on the security code; and specifying the guarantee code based on the attribute of the data when the data is received from the cache. And a value that specifies a guarantee code based on the attribute of the data is held. Comparing the value specifying the guarantee code based on the attribute of the data stored in the guarantee code holding means with the value specifying the guarantee code based on the attribute of the data added to the data read from the cache. Disk array system. 3. The disk array system according to claim 1, wherein said disk array checks a disk input / output means for inputting / outputting data from / to said plurality of disk devices and a value specifying a guarantee code based on a data attribute. The MPU creates a transfer list for the disk input / output means, and upon a data write request from the host, the MPU reads the transfer list referred to by the disk input / output means. Create and set a value for specifying a guarantee code based on the attribute of the data in the transfer list, and the disk input / output means follows the transfer list including a value for specifying the guarantee code based on the attribute of the data,
Data is received from the cache, and the guarantee code holding unit acquires a value specifying a guarantee code based on the attribute of the data when the data is received from the cache, and specifies the guarantee code based on the attribute of the data. The disk-side inspection unit stores a value specifying a guarantee code based on the attribute of the data stored in the guarantee code holding unit and a guarantee based on the attribute of the data added to the data read from the cache. The MPU creates a transfer list referred to by the disk input / output means when a data read request is made from the host, and a guarantee based on the data attribute is included in the transfer list. A value for specifying a code is set, and the disk input / output means specifies a guarantee code based on a data attribute. In accordance with the transfer list, including,
The data is transmitted to the cache, and the guarantee code holding unit acquires a value specifying a guarantee code based on the attribute of the data when the data is transmitted to the cache, and specifies the guarantee code based on the attribute of the data. The disk-side inspection unit stores a value specifying a guarantee code based on the attribute of the data stored in the guarantee code holding unit and a guarantee based on the attribute of the data added to the data written in the cache. A disk array system comprising comparing values specifying codes. 4. The disk array system according to claim 1, wherein said disk array includes host-side holding means for holding host transfer parameters when a data write request is made. 5. The disk array system according to claim 1, wherein said disk array includes disk-side holding means for holding a disk transfer parameter at the time of a data read request.