JP2000340447A - Capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor with a large capacity in a low inductance structure for functioning as a decoupling capacitor in a wide frequency region. SOLUTION: A plurality of electrode layers 5a, 5b, 7a, and 7b having different areas are formed on the upper and lower faces of a dielectric layer 4 in a row with prescribed intervals, and a plurality of capacity generating parts A and B having different capacities due to the upper and lower electrode layers 5a, 5b, 7a, and 7b and the dielectric layer 4 between them are formed in a row, and the adjacent electrode layers on the same face of the dielectric layer 4 are connected through conductors 9 and 10. Also, the electrode layers 5a, 5b, 7a, and 7b at the outermost part on the same face of the dielectric layer 4 are respectively provided with extraction electrode layers 11 and 12, and the leading electrode layers 11 and 12 are respectively provided with outer connecting terminals 2a, 2b, 3a, and 3b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a capacitor,
For example, the present invention relates to a large-capacity, low-inductance capacitor provided in an electric circuit that operates at high speed and used for bypassing high-frequency noise or for preventing fluctuations in power supply voltage.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, electronic components installed in the electronic devices have become smaller and thinner.
Demands for high frequency and the like are increasing.

In particular, in a high-speed digital circuit of a computer which needs to process a large amount of information at a high speed, the clock frequency in the CPU chip is 400 MHz to 1 GHz and the clock frequency of the bus between chips is also 75 MHz to 100 MHz even at the personal computer level. The speeding up is remarkable. Further, as the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to suppress power consumption. As the speed, density, and voltage of these IC circuits have increased, passive components such as capacitors have become required to exhibit excellent characteristics with respect to high-frequency or high-speed pulses in addition to increasing the size and capacity. .

In order to make a capacitor compact and high-capacity,
It is most effective to make the dielectric sandwiched between the pair of electrodes thinner and thinner. The thinning is compatible with the above-mentioned tendency of voltage drop.

On the other hand, various problems associated with the high-speed operation of the IC circuit are more serious than miniaturization of each element. Of these, in the function of removing high-frequency noise, which is the role of the capacitor, it is particularly important that the instantaneous drop of the power supply voltage that occurs when simultaneous switching of logic circuits occurs at the same time instantaneously reduces the energy stored in the capacitor. This is a function that is reduced by supplying it to a so-called decoupling capacitor.

[0006] The performance required of this decoupling capacitor lies in how quickly the current can be supplied with respect to the current fluctuation of the load section faster than the clock frequency.
Therefore, it must function reliably as a capacitor in the frequency range of 100 MHz to 1 GHz.

However, an actual capacitor element has a resistance component and an inductance component in addition to a capacitance component. The impedance of the capacitance component decreases with increasing frequency, and the inductance component increases with increasing frequency.

For this reason, as the operating frequency increases,
The inductance of the element limits the transient current to be supplied, causing an instantaneous drop in the power supply voltage on the logic circuit side or new voltage noise. As a result, an error occurs in the logic circuit. Particularly in recent LSIs, the power supply voltage has been reduced in order to suppress an increase in power consumption due to an increase in the total number of elements, and the allowable fluctuation width of the power supply voltage has been reduced. Therefore, in order to minimize the voltage fluctuation width at the time of high-speed operation, the impedance of the decoupling capacitor element itself is reduced even in a high-frequency region, and it has a performance capable of supplying the stored electric charge as a necessary current instantaneously. Very important.

The standard of impedance reduction is AJ Rain
al, "Computing Inductive Noiseof CMOS Drivers", I
EEE Trans. Comp., Packag., Manufact. Technol.-Part
B, Vol. 19, pp. 789-802 (1996), the change in current per driver is 40 mA / ns. Power supply voltage is 1.8V, voltage fluctuation tolerance is 10%
0.18 V and the number of off-chip drivers is 64, the upper limit of the inductance is 0.14 nH and 1 G
The impedance at Hz must be less than about 0.4Ω.

In order to minimize the impedance of the capacitor in the required frequency range, the capacitance component of the capacitor itself is increased and the resistance component and the inductance component are reduced, or the equivalent series inductance ESL and the capacitance C Resonance frequency f ₀ = 1 / 2π (ES
L · C) The capacitance may be reduced so that _1/2 is adjusted to the required frequency.

In the former method, first, regarding the capacitance,
As described above, it is most effective to reduce the thickness of the dielectric layer held between the electrodes. The resistance component is determined by the dielectric loss of the dielectric and the resistance of the electrode portion. The resistance of the electrode portion can be considered to be a substantially constant value except for the skin effect which becomes remarkable at several GHz or more.

There are the following three methods for reducing the inductance. The first method is to minimize the length of the current path, the second method is to make the current path a loop structure and the loop cross-sectional area is minimized, and the third method is to set the current path to n.
In this method, the effective inductance is reduced to 1 / n.

Although attempts have been made to reduce the impedance of the capacitor element by reducing the inductance of the capacitor element, the area where the impedance can be used at 0.4Ω or less is the resonance frequency determined by the capacitance and inductance of the capacitor. Only nearby. If the capacitor is used with a reduced capacity in a frequency range higher than this, the capacitor will function only in the region near the resonance frequency.

As a method for overcoming the fact that the impedance is reduced only near the resonance frequency and realizing a capacitor that functions with a low impedance in a wide frequency range, means for connecting capacitors having different capacities in parallel has been considered. For example, as disclosed in JP-A-6-77083, there is an attempt to obtain a capacitor having a large capacity and excellent high-frequency characteristics by arranging a plurality of dielectric materials having different relative dielectric constants in parallel.

In a multilayer ceramic capacitor, as described in JP-A-8-162368,
Attempts have been made to connect two capacitors having different capacities in parallel by changing the electrode area and the thickness of the dielectric layer in one chip capacitor, and to realize a noise absorbing function in a wide frequency range with a single component. The impedance can be reduced at the resonance point of two capacitor elements having different capacities.

Japanese Patent Application Laid-Open No. 9-246098 also discloses that noise can be absorbed in a wide frequency range by forming electrodes of each layer so that each capacitance is different and connecting each stage in parallel via an inductor element. Attempts have been made to develop functions.

[0017]

However, in the thin film capacitor disclosed in JP-A-6-77083, the external terminal electrodes of the capacitor element are paired, and even if the capacitor having the internal structure is divided in a plane, an equivalent circuit is obtained. Since is not different from a single capacitor element, it is considered that only the parallel effect of the dielectric properties of the materials is present and the effect on the equivalent circuit is not exhibited.

Also, in the parallel capacitor disclosed in Japanese Patent Application Laid-Open No. 8-162368, the equivalent circuit is no different from a single capacitor element because the external terminal electrodes are paired in the same manner as described above. Furthermore, in this structure, since the external terminal electrodes are paired, currents in the same direction flow simultaneously in the two capacitor elements themselves, so that the mutual inductance between the two capacitors increases, and the effect of parallel connection is expected. I can't.

Further, in Japanese Patent Application Laid-Open No. 9-246098, the inductance of the whole element increases, which goes against the reduction in impedance. An even more important problem is that there is a local maximum point of impedance due to parallel resonance between each resonance point. Unless this parallel resonance is suppressed, the impedance cannot be reduced in a wide frequency range of 100 MHz or more.

An object of the present invention is to provide a large-capacity, low-inductance capacitor that can function as a decoupling capacitor in a higher frequency range and a wider frequency range.

[0021]

According to the present invention, there is provided a capacitor comprising:
A plurality of electrode layers having different areas are formed in a row at predetermined intervals on the upper and lower surfaces of the dielectric layer, respectively, and a plurality of capacitance generating sections having different capacitances due to the upper and lower electrode layers and the dielectric layer therebetween Are formed in a line, and adjacent electrode layers on the same surface of the dielectric layer are connected by a conductor,
Further, an extraction electrode layer is provided on the outermost electrode layer on the same surface of the dielectric layer, and an external connection terminal is provided on the extraction electrode layer.

Here, it is preferable that the extraction electrode layers extend in the same direction from the upper and lower electrode layers constituting the capacitance generating portion. Further, it is desirable that the capacity of the outermost capacity generating section is smaller than the capacity of the central capacity generating section. Further, it is preferable that the capacity generating section includes a large capacity generating section and a small capacity generating section, and the capacity of the large capacity generating section is not more than 10 times the capacity of the small capacity generating section.

[0023]

In the capacitor of the present invention, a plurality of electrode layers having different areas are connected by a conductor, and a current flows from an extraction electrode layer provided on an outermost electrode layer. If this occurs, first, a current flows into the LSI from the small-capacity generation unit via the extraction electrode layer and the external connection terminal. Current will flow through the terminal. For this reason, as if 2
The two capacitors work independently, and the effect of parallel connection appears on the equivalent circuit.

Further, since the external connection terminals are respectively provided on the extraction electrodes extending from the outermost electrode layer, the external connection terminals have two or more pairs. When current flows, the current can be surely divided in two directions.

By exhibiting the effects of parallel connection and shunting, it is possible to exhibit low impedance characteristics in a wide frequency range.

Further, by extending the extraction electrode layers in the same direction from the upper and lower electrode layers constituting the capacitance generating section, the end portions of the extraction electrode layers connected to the upper and lower electrode layers constituting the capacitance generation section are formed. Can be installed next to each other, and the distance between external connection terminals of different polarities can be minimized as much as possible.
It is possible to realize low impedance.

Further, by making the capacitance of the outermost capacitance generating section smaller than that of the central capacitance generating section,
Since the capacitor is structurally symmetric, there is no need to consider the direction of connection to the LSI or the like. Further, since the capacitance of the capacitance generating portion on the side connected to the LSI or the like is small, higher frequency can be promoted.

Further, the capacitance generating section is composed of a large-capacity generating section and a small-capacity generating section. By setting the capacity of the large-capacity generating section to 10 times or less the capacity of the small-capacity generating section, low impedance characteristics can be obtained. Can be maximized, the impedance in this region can be made flat, and the frequency range used can be further expanded.

[0029]

FIG. 1 is a perspective view showing the appearance of a multilayer capacitor according to the present invention, FIG. 2 is a sectional view taken along the line xx of FIG. 1, and FIG. 3 is a plan view showing an electrode pattern. In the capacitor of the present invention, as shown in FIG. 1, external terminal electrodes 2a, 2b, 3a and 3b are formed on opposite side surfaces of the capacitor body 1.

The capacitor body 1 is, as shown in FIG.
Two electrode layers 5a and 7a are formed at predetermined intervals on the upper surface of the dielectric layer 4, and two electrode layers 5b and 7b are formed at predetermined intervals on the lower surface. The electrode layers 5a and 5b, the electrode layers 7a and 7b have the same area, and the electrode layers 5a and 5b and the electrode layers 7a and 7b have different areas. Thereby, the upper and lower electrode layers 5a, 5b
And the dielectric layer 4 between them, and also the electrode layers 7a,
Two capacitance generating portions A and B having different capacitances are formed by 7b and the dielectric layer 4 therebetween.

A protective layer 8 made of the same material as the dielectric layer 4 is formed on the upper and lower surfaces of the dielectric layer 4, thereby forming the capacitor body 1.

The electrode layer 5a and the electrode layer 7a are connected by a conductor 9 as shown in FIG.
The electrode layer 7b is connected to the electrode layer 7b by a conductor 10, as shown in FIG. The electrode layers 5a and 5b and the electrode layer 7
Extraction electrode layers 11 and 12 are respectively provided on a and 7b. External connection terminals 2b and 3b are provided on the extraction electrode layer 11, and external connection terminals 2a and 3a are provided on the extraction electrode layer 12, respectively.

The extraction electrode layers 11 and 12 are provided with capacitance generating portions A,
B extends from the upper and lower electrode layers 5a and 5b or from the electrode layers 7a and 7b in the same direction.
That is, the extraction electrode layer 11 extended from the electrode layer 5a,
The extraction electrode layer 12 extending from the electrode layer 5b is exposed on the same side surface of the capacitor body 1, and includes the extraction electrode layer 11 extending from the electrode layer 7a and the extraction electrode layer extending from the electrode layer 7b. The layer 12 is exposed on the same side of the capacitor body 1.

The capacity of the capacity generating section B is smaller than the capacity of the capacity generating section A, and the capacity of the capacity generating section A is set to 10 times or less of the capacity of the capacity generating section B. It is desirable that the capacity of the capacity generating section A is 1.5 to 4 times, more preferably 1.5 to 2.5 times the capacity of the capacity generating section B.

The external connection terminals 2a, 3a are connected to ground, and the external connection terminals 2b, 3b are connected to a power supply.
Note that the LSI is connected to the external connection terminal 3b.

In the capacitor configured as described above,
For example, when an instantaneous voltage drop occurs in the LSI, a current flows from the capacitance generating section B via the external connection terminal 3b, and after the flow of the capacitance from the capacitive element B ends, the external connection from the capacitance generating section A ends. A current flows through the terminal 3b, and a capacity flows from the capacity generating section A. Therefore, as if two capacitors act independently, the equivalent circuit
The effect of the parallel connection appears. Further, since the electrode layers 5a and 7a and the electrode layers 5b and 7b have the external connection terminals 2b and 3b and the external connection terminals 2a and 3a, the current can be surely divided in two directions. By exhibiting the effects of the above-described parallel connection and branching, low impedance characteristics can be exhibited in a wide frequency range.

An extraction electrode layer 11 extending from the electrode layer 5a and an extraction electrode layer 12 extending from the electrode layer 5b.
Are exposed on the same side surface of the capacitor body 1 and are connected to the external connection terminals 2a and 2b, and are connected to the extraction electrode layer 11 extending from the electrode layer 7a and the extraction electrode layer 12 extending from the electrode layer 7b. Is exposed on the same side of the capacitor body 1,
Since they are connected to the external connection terminals 3a and 3b, the extraction electrode layer 11 and the extraction electrode layer 12 can be close to each other on the same side surface of the capacitor body 1, and the external connection terminals 2a and 2b
b, the external connection terminals 3a and 3b can be formed close to each other, and a lower impedance can be realized.

Further, the LSI is connected to the electrode layer 7 of the capacitance generating section B.
a connected to the external connection terminal 3b connected to the
Since the capacitance of the capacitance generating portion B on the side connected to the small terminal is small, it is possible to further increase the frequency.

In the above example, on the upper and lower surfaces of the dielectric layer 4,
Although the example in which the two electrode layers 5a, 7a, 5b, and 7b are formed has been described, three or more electrode layers may be formed on the upper and lower surfaces of the dielectric layer. In this case, by making the capacitance of the capacitance generating portion on both sides (outermost) smaller than the capacitance of the central capacitance generating portion, the capacitor has symmetry, so that the direction for connecting to the LSI or the like is changed. No consideration. Further, since the capacitance of the capacitance generating portion on the side connected to the LSI or the like is small, higher frequency can be promoted. FIG.
Three or more electrode layers 15a on the upper and lower surfaces of the dielectric layer 14,
17 shows an electrode pattern of a capacitor formed with 17a, 19a and electrode layers 15b, 17b, 19b.

As shown in FIG. 5, the electrode layers 5a, 7a
a, the extraction electrode layer 21, and the electrode layers 5b, 7b to the extraction electrode layer 2.
2 may be formed.

Further, in the above example, an example in which the electrode layers are formed on the upper and lower surfaces of one dielectric layer has been described. However, the capacitor of the present invention is formed by forming the electrode layers on the upper and lower surfaces of a plurality of dielectric layers. Is also good.

FIGS. 6 and 7 show a thin-film capacitor according to the present invention. Two electrode layers 35a and 37a are formed on the upper surface of an insulating substrate 31 at a predetermined interval. A dielectric layer 38 is formed on the upper surface of 37a, and two electrode layers 35b,
37b are formed at predetermined intervals.

The electrode layer 35a and the electrode layer 37a
The electrode layer 35b and the electrode layer 37b are connected by a conductor 40, and the electrode layers 35a and 35b and the extraction electrode layers 41 and 42 are provided on the electrode layers 37a and 37b, respectively. The upper surfaces of the electrode layers 37a and 37b are covered with a protective layer 39, and the protective layers 39 where the extraction electrode layers 41 and 42 are located are open.
Extraction electrode layer 41 connected to 37a, electrode layers 35b and 37
b, the extraction electrode layer 42 connected to the electrode layer 3 is exposed.
The external connection terminal 52 is provided at the exposed portion of the extraction electrode layer 41 of FIG.
a, an external connection terminal 52b is provided in an exposed portion of the extraction electrode layer 42 of the electrode layer 35b. The electrode layer 37a
Although not shown, external connection terminals are also formed on the exposed portion of the extraction electrode layer 41 and the exposed portion of the extraction electrode layer 42 of the electrode layer 37b.

With the thin film capacitor configured as described above, the same effects as described above can be obtained.

The electrode layer material used in the capacitor of the present invention is platinum (Pt), gold (Au), silver (Ag), palladium (Pd), low-resistance copper (Cu), nickel (N
i) etc. can be suitably used, and is not particularly limited as long as the material has low reactivity with the dielectric layer.
What is necessary is just to be able to form by methods, such as sputtering.

The external connection terminals may be solder bumps formed of solder balls or solder paste, Ag,
Screen printing of paste containing Pd, Cu, and Ni as main components, dipping method by aligning with a plate called a carrier plate, Ni-solder plating, Ni-S
What is necessary is just to be able to form by well-known techniques, such as n plating.

Further, any dielectric material may be used as long as it has a high dielectric constant in a high frequency range.
g, Nb-containing perovskite-type oxide crystal and other dielectric materials such as PZT, PLZT, BaTiO ₃ , S
rTiO ₃ , Ta ₂ O _5, or compounds obtained by adding or substituting other metals to these may be used, and are not particularly limited.

In the case of the thin film type, the film thickness is desirably 0.3 μm to 1.0 μm, particularly 0.4 μm to 0.8 μm in order to ensure high capacity and insulation. In the case of the multilayer chip capacitor type, there is no particular limitation as long as the film thickness is formed from several μm to several tens μm. In the case of the thin film type, the insulator substrate used is not particularly limited and is selected from alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO ₃ single crystal, surface silicon oxide, glass, quartz and the like.

[0049]

EXAMPLE 1 First, a 10 μm-thick green sheet was formed by a doctor blade method using a slip containing barium titanate as a main component and a sintering aid, a solvent, a dispersant, and a binder mixed therein. Molded. On the other hand, a commercially available Pd paste was prepared as an internal electrode.

Then, a green sheet having an electrode pattern as shown in FIG. 3A and a green sheet having an electrode pattern as shown in FIG.
Green sheets on which no electrode patterns were formed were sequentially laminated, and a laminated molded body was obtained by thermocompression bonding.

After the obtained laminated molded body was cut into a predetermined size, it was fired in air at a temperature of 1250 ° C. for 2 hours. Thereafter, a conductive paste containing silver as a main component was applied, dried, and baked at 800 ° C. to form external connection terminals.

After that, Ni- is formed on the outermost layer of the external connection terminal.
A plating coating layer is formed by solder plating and used as a terminal electrode, and the capacity of the capacity generating section A is twice the capacity of the capacity generating section B,
A multilayer capacitor as shown in FIG. 1 to FIG.

The impedance characteristics of the produced capacitor at 1 to 1.8 GHz were measured using an impedance analyzer (HP4291A, manufactured by Hewlett-Packard) and a microwave probe (manufactured by Picoprobe).
The results are shown in FIG. 8A shows that the capacity of the capacity generating section A is twice the capacity of the capacity generating section B, FIG.
(C) is the impedance characteristic in the case of 4 times, and (d) is the impedance characteristic in the case of 10 times.

Incidentally, Japanese Unexamined Patent Publication No.
A capacitor disclosed in Japanese Patent No. 162368 is manufactured,
The same evaluation as above was performed. Note that the effective electrode areas in the capacitance generating sections A and B were the same. FIG. 9 shows the results.

FIGS. 8 and 9 show that the impedance is low in a higher frequency range and a wider frequency range.

(Example 2) A thin film capacitor was manufactured as follows. Each electrode layer was formed using a high-frequency magnetron sputtering method. First, Ar gas was introduced into the process chamber as a sputtering gas, and the pressure was maintained at 6.7 Pa by evacuation. At the time of sputtering, the substrate holder was moved to the target position of the kind of the material to be formed, and the distance between the substrate and the target was fixed at 60 mm.

Next, a high-frequency voltage of 13.56 MHz is applied between the substrate holder and the target by an external high-frequency power source, and a high-density magnetic field is generated near the target by a magnetron magnetic field formed by a permanent magnet installed on the back of the target. The target surface was sputtered by generating plasma.

In this embodiment, plasma is generated by applying only to the target closest to the substrate. The substrate holder had a heating mechanism using a heater, and was controlled so that the substrate temperature during sputter deposition was constant. Further, a metal mask having a thickness of 0.1 mm is provided on the target side of the substrate placed on the substrate holder, so that a required mask can be set on the substrate deposition surface according to the deposition pattern.

All the dielectric layers were formed by a sol-gel method.
Also, Mg acetate and Nb ethoxide were weighed at a molar ratio of 1: 2, and refluxed in 1,3-propanediol (about 12%).
(At 4 ° C. for 6 hours), and a MgNb composite alkoxide solution (Mg = 5.0 mmol, Nb 10.0 mmol, 1,
3-propanediol (100 mmol) was synthesized. Next, 15 mmol of lead acetate (trihydrate) was added to the MgNb composite alkoxide solution and dissolved at 60 ° C.
A (Mg _1/3 Nb _2/3 ) O ₃ (PMN) precursor solution was synthesized.

Then, the electrode layer (0.9) shown in FIG.
(mm × 1.0 mm) mask pattern.
A 0.3 μm thick Au electrode was formed on a 25 mm alumina substrate, and the coating solution was applied on the Au electrode by a spin coater, dried, and then heat-treated at about 400 ° C. for 1 minute. A gel film was prepared.

After the operation of coating and heat treatment of the coating solution was repeated, baking was performed at about 800 ° C. for 2 minutes (in air) to obtain a 0.7 μm-thick PMN thin film. The perovskite generation rate was calculated to be about 95% from the X-ray diffraction results of the obtained thin films. After that, the dielectric film was patterned by a photoresist process.

An Au electrode was sputter-deposited on the surface of the PMN film using the mask pattern of the electrode layer shown in FIG. After forming each element, a protective film having a via hole is formed using a photosensitive resin, and in the via hole, a solder paste is printed by screen printing of a solder paste, and then 0.1 mmφ is formed by a reflow process.
Were formed to obtain a thin film capacitor as shown in FIGS.

The impedance characteristics of the manufactured thin film capacitor at 1 MHz to 1.8 GHz were measured using an impedance analyzer (HP429, manufactured by Hewlett-Packard Company).
1A) and the results of measurement using a microwave probe (manufactured by Pico Probe) are shown in FIG. FIG. 9 shows that the thin film capacitor of the present invention has low impedance in a higher frequency range and a wide frequency range.

[0064]

According to the capacitor of the present invention, a plurality of electrode layers having different areas are connected by a conductor, and a current flows from the extraction electrode layer provided on the outermost electrode layer. When it occurs in an LSI, first, L
A current flows into the SI from the small-capacity generation unit via the extraction electrode layer and the external connection terminal. Will flow in. For this reason, as if two capacitors act independently, the effect of parallel connection appears on the equivalent circuit.

Further, since the external connection terminals are respectively provided on the extraction electrodes extending from the outermost electrode layer, the external connection terminals have two or more pairs, and the current flows into the LSI in which the current fluctuation has occurred. In this case, the current can be reliably split in two directions.

By exhibiting the effects of parallel connection and branching, it is possible to exhibit low impedance characteristics in a wide frequency range.

[Brief description of the drawings]

FIG. 1 is an external perspective view of a capacitor according to the present invention.

FIG. 2 is a cross-sectional view taken along line xx of FIG.

FIG. 3 is a plan view showing an electrode pattern of FIG. 2;

FIG. 4 is a plan view showing an electrode pattern of another example of the capacitor of the present invention.

FIG. 5 is a plan view showing an electrode pattern of the capacitor of the present invention in which the extraction direction of the extraction electrode is changed.

FIG. 6 is a sectional view of the thin film capacitor of the present invention.

FIG. 7 is a plan view showing an electrode layer pattern of FIG. 6;

FIG. 8 shows impedance characteristics of the multilayer capacitor.

FIG. 9 shows impedance characteristics of a multilayer capacitor in JP-A-8-162368.

FIG. 10 shows impedance characteristics of a thin film capacitor.

[Explanation of symbols]

 4 ... Dielectric layer 5a, 5b, 7a, 7b ... Electrode layer A, B ... Capacitance generator 9, 10 ... Conductor 11, 12 ... Extraction electrode layer 2a, 2b, 3a, 3b ... external connection terminal

Claims (4)

[Claims] A plurality of electrode layers having different areas are formed in a line at predetermined intervals on upper and lower surfaces of a dielectric layer, respectively, and have different capacitances due to upper and lower electrode layers and a dielectric layer therebetween. A plurality of capacitance generating portions are formed in a line, and adjacent electrode layers on the same surface of the dielectric layer are connected to each other by a conductor, and an extraction electrode is connected to the outermost electrode layer on the same surface of the dielectric layer. A capacitor provided with a plurality of external connection terminals on the extraction electrode layer. 2. The capacitor according to claim 1, wherein the extraction electrode layers extend in the same direction from upper and lower electrode layers constituting the capacitance generating portion. 3. The capacity of the outermost capacity generating section is smaller than the capacity of the center capacity generating section.
Or the capacitor according to 2. 4. A capacity generating section comprising a large capacity generating section and a small capacity generating section, wherein the capacity of the large capacity generating section is 10 times or less the capacity of the small capacity generating section. 1
4. The capacitor according to any one of claims 3 to 3.