JP2000338186A - Integrated circuit with frequency division test function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit capable of testing a first frequency dividing circuit and a second frequency dividing circuit respectively without adding newly a testing terminal. SOLUTION: When a reset terminal 6 is opened to input a clock pulse to a clock input terminal 1, the frequency of the clock pulse is divided by a first frequency dividing circuit 2 to be transmitted to the reset terminal 6 via a signal control circuit 5, and an operation of the first frequency dividing circuit 2 is confirmed by an output of the reset terminal 6. When a second dividing circuit 3 is tested, the clock pulse input to the clock input terminal 1 is stopped after an 'H' signal is supplied once to the reset terminal 6, then an external clock pulse is input thereafter to the reset terminal 6, a selector 9 selects thereby an input signal via the signal control circuit 5, the external clock signal from the reset terminal 6 is input to the second frequency dividing circuit 3, and the second frequency dividing terminal 3 is brought into a frequency dividing operation condition to conduct an output to a dividing output terminal 4. An operation of the second frequency dividing circuit 3 is confirmed by the output.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to an integrated circuit having a frequency division test function.

2. Description of the Related Art Conventionally, in an integrated circuit in which a fundamental frequency signal is divided by using a plurality of frequency dividers, whether the frequency divider operates normally in order to meet demands for high accuracy and reliability. It is necessary to perform a test, and an example of a device that can easily perform this test is an integrated circuit with a frequency division test function disclosed in Japanese Patent Publication No. 7-52214. This disclosed technique will be described with reference to FIG.
Is fixed to one of the power supply potentials, thereby resetting the integrated circuit having the first, second, and third frequency dividing circuits 101, 102, and 103.
By inputting an acceleration clock to the first frequency dividing circuit 10
The reset of the third frequency divider 103 is released while the reset of 1 is continuously performed, and a test is performed to determine whether the second and third frequency dividers are operating normally. The test can be performed using the reset terminal. Therefore, it has a feature that the configuration can be simplified.

However, the above-described circuit only operates the second and third frequency dividers 102 and 103 and tests the output of the third frequency divider 103 at that time. In addition, the operation of the remaining first frequency dividing circuit 101 cannot be tested. In other words, when the entire frequency dividing circuit is divided into the former stage and the latter stage, there is a disadvantage that only the latter stage can be tested. Further, if another function such as an alarm is to be provided in the same integrated circuit, a control terminal for the other function is required, which increases the chip size and leads to an increase in cost.

SUMMARY OF THE INVENTION The present invention is directed to a first embodiment of the invention.
A clock input terminal capable of inputting a first clock pulse signal, a first frequency dividing circuit for dividing the first clock pulse signal, and a reset terminal capable of externally inputting a desired signal and a second clock pulse signal Between the output terminal of the first frequency divider circuit and the reset terminal to prevent a signal input from the outside to the reset terminal from being transmitted to the output terminal side of the first frequency divider circuit A signal control circuit for outputting a signal corresponding to the output of the first frequency dividing circuit to the reset terminal side, and one of the output of the first frequency dividing circuit and the signal input to the reset terminal. Selecting means for outputting, a second frequency dividing circuit for dividing the output of the selecting means, a determining circuit for outputting a predetermined signal when the desired signal is input to the reset terminal, and a clock input terminal To And a latch circuit for holding the output state of the determination circuit at a desired level of the first clock pulse signal to be output, wherein the second frequency divider circuit receives the desired signal at the reset terminal. Reset, the selection means selects and outputs a signal to be input to the clock input terminal when the latch circuit holds the predetermined signal, and the latch circuit is different from the predetermined signal. When the signal is held, the output of the first frequency dividing circuit is selected and output. When the selecting means is selecting the signal to be input to the clock input terminal, the output of the first frequency dividing circuit is externally connected to the reset terminal. Receives the second clock pulse signal. Therefore, each of the first frequency divider circuit and the second frequency divider circuit can be tested without newly adding a test terminal, the chip area of the integrated circuit can be reduced, and the cost can be reduced. Therefore, when the entire frequency dividing circuit is divided into the former stage and the latter stage, the inconvenience that conventionally only the latter stage can be tested can be solved. A clock input terminal to which a first clock pulse signal can be inputted from the outside, and a first input terminal for dividing the frequency of the first clock pulse signal
, A first signal, a second signal, and a second
And a reset terminal capable of inputting a clock pulse signal of the first frequency divider, and an output terminal of the first frequency divider circuit and the reset terminal. A signal input from the outside to the reset terminal is the first frequency divider. A signal control circuit that inhibits transmission to the output terminal side of the circuit and outputs a signal corresponding to the output of the first frequency divider circuit to the reset terminal side; an output of the first frequency divider circuit and the reset signal Selecting means for outputting any one of the signals input to the terminal, a second frequency dividing circuit for dividing the output of the selecting means, and first and second output terminals; Outputting a third signal from the first output terminal when the first signal is input;
A determination circuit that outputs a fourth signal from the second output terminal when the second signal is input to the reset terminal; and a determination circuit that outputs a fourth signal from the second output terminal when the first clock pulse signal input to the clock input terminal has a desired level. A latch circuit for holding an output state of the first output terminal; and an operation circuit for executing a desired operation by outputting the fourth signal, wherein the second frequency divider circuit is configured to output the first signal. Is being reset while the latch circuit is being input, and the selecting means determines that the latch circuit is in the third state.
When the latch circuit holds a signal different from the third signal, it selects and outputs the signal input to the clock input terminal. When the output of the peripheral circuit is selected and output, and the selection means is selecting a signal to be input to the clock input terminal,
The second clock pulse signal is externally input to the reset terminal. Therefore, while solving the same problem as described above, even if an operation circuit performing a desired operation is added to the integrated circuit, it is not necessary to add a control terminal for the operation circuit, and the chip area of the integrated circuit can be reduced. Cost can be reduced. The signal control circuit is a series circuit of a buffer circuit and a resistor, the input side of the buffer is connected to the output terminal of the first frequency divider, one end of the resistor is connected to the output side of the buffer, Is connected to the reset terminal, so that the same problem as described above can be solved, and with a simple configuration, the output of the first frequency divider circuit can be adversely affected by the signal input state to the reset terminal. Can be prevented.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present application provides a clock input terminal to which a first clock pulse signal can be externally input, and a first frequency divider for dividing the first clock pulse signal. A reset terminal capable of externally inputting a desired signal and a second clock pulse signal; and an output terminal of the first frequency divider circuit and the reset terminal. A signal control circuit that inhibits a signal input to the first frequency divider from transmitting to the output terminal of the first frequency divider and outputs a signal corresponding to the output of the first frequency divider to the reset terminal; Selecting means for outputting one of an output of the first frequency dividing circuit and a signal input to the reset terminal; a second frequency dividing circuit for dividing the output of the selecting means; Signal is input And a latch circuit for holding an output state of the determination circuit at a desired level of the first clock pulse signal input to the clock input terminal. The circuit is reset while the desired signal is being input to the reset terminal, and the selecting means is configured to output a signal input to the clock input terminal when the latch circuit holds the predetermined signal. And when the latch circuit holds a signal different from the predetermined signal, selects and outputs the output of the first frequency dividing circuit, and the selecting means selects the clock input terminal. The second clock pulse signal is externally input to the reset terminal when a signal to be input to is selected. The invention according to claim 2 of the present application provides a clock input terminal capable of externally inputting a first clock pulse signal, a first frequency dividing circuit for dividing the frequency of the first clock pulse signal, And a reset terminal capable of inputting a second signal and a second clock pulse signal, and an output terminal of the first frequency divider circuit and the reset terminal. A signal control circuit that inhibits an input signal from being transmitted to an output terminal of the first frequency divider and outputs a signal corresponding to an output of the first frequency divider to the reset terminal; (1) selecting means for outputting one of the output of the frequency dividing circuit and the signal input to the reset terminal, a second frequency dividing circuit for dividing the output of the selecting means, and first and second outputs Terminal and the reset terminal A third signal is output from the first output terminal when the first signal is input, and a fourth signal is output from the second output terminal when the second signal is input to the reset terminal. A determination circuit for performing the determination, and the first input to the clock input terminal.
A latch circuit for holding an output state of the first output terminal at a desired level of the clock pulse signal, and an operation circuit for executing a desired operation in response to the output of the fourth signal. The circuit is reset while the first signal is being input, and the selection means selects a signal to be input to the clock input terminal when the latch circuit holds the third signal. When the latch circuit holds a signal different from the third signal, the output of the first frequency dividing circuit is selected and output, and the selecting means inputs the signal to the clock input terminal. When the signal to be selected is selected, the second clock pulse signal is externally input to the reset terminal. According to a third aspect of the present invention, in the first or second aspect, the signal control circuit comprises a series circuit of a buffer circuit and a resistor, and an input side of the buffer circuit is connected to an output terminal of the first frequency dividing circuit. One end of the resistor is connected to the output side of the buffer circuit, and the other end of the resistor is connected to the reset terminal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to an embodiment shown in the drawings. In FIG. 1, a clock input terminal 1 is capable of externally inputting a clock pulse as a first clock pulse signal, and this clock pulse is supplied from, for example, a crystal oscillation circuit or the like. First frequency divider 2 and second frequency divider 2
The third frequency dividing circuit 3 operates at the falling edge of the input pulse, and the second frequency dividing circuit 3 generates an output at the frequency dividing output terminal 4. Note that the frequency division ratios of the first frequency divider 2 and the second frequency divider 3 can be changed as appropriate, and may operate at the rising edges of the respective input pulses. The signal control circuit 5 includes a series circuit of a buffer circuit 51 and a resistor 52 having a sufficiently large resistance value.
One input side is connected to the output terminal F1 of the first frequency dividing circuit 2, one end of the resistor 52 is connected to the output side of the buffer circuit 51, and the other end of the resistor 52 is connected to the reset terminal 6.
Therefore, the output of the first frequency dividing circuit 2 is supplied to the reset terminal 6 as the output of the buffer circuit 51.
A signal corresponding to the output of the first frequency dividing circuit 2 is output to the signal control circuit 5
From the buffer circuit 51
Prevents the input to the reset terminal 6 from being transmitted to the output terminal side of the first frequency divider 2. Therefore, with a simple configuration, the input signal to the reset terminal 6 is the first signal.
Adversely affecting the output of the frequency dividing circuit 2 can be prevented. Also, by making the resistance of the resistor 52 sufficiently large,
As will be described later, the input of “H” or “L” supplied to the reset terminal 6 through a connection line having a sufficiently small resistance value is input to the first terminal.
Can be supplied to the determination circuit 7 in preference to the output of the frequency dividing circuit 2. Therefore, by sufficiently increasing the resistance value of the resistor 52, the input signal to the reset terminal 6 can be reliably transmitted to the determination circuit 7, and the determination accuracy of the determination circuit 7 can be improved. The determination circuit 7 detects the state of the reset terminal 6 based on the state of a signal input from the signal control circuit 5. In this example, the first signal and “H” as a desired signal are applied to the reset terminal 6 for a desired time (in this example, a time longer than the pulse width of the pulse output from the first frequency dividing circuit 2).
A signal that continues (hereinafter, referred to as “first signal”) is input, or a signal in which “L” as the second signal continues for the desired time (hereinafter, “second signal”) is input. Is determined, and while it is determined that the first signal is being input to the reset terminal 6, the first output terminal 7
1 outputs “H” as a third signal, and while determining that the second signal is being input to the reset terminal 6, outputs “H” as a fourth signal to the second output terminal 72. Is output. Therefore, when neither the first nor the second signal is input to the reset terminal 6, "L" is output without outputting "H" to either of the first and second output terminals.
Therefore, a circuit for determining a ternary input as to whether the first signal is input, whether the second signal is input, or whether neither the first nor the second signal is input is used as the determination circuit 7. May be used. The latch circuit 8 holds the output state of the first output terminal 71 of the determination circuit 7 during a desired level of the input signal from the clock input terminal 1 (in this example, at the time of “L”). Note that the period during which the output state of the output terminal 71 is held may be the time when the input signal from the clock input terminal 1 is “H”. Based on the output of the latch circuit 8, the selector 9 selects one of the input from the first frequency dividing circuit 2 and the input from the reset terminal 6 and outputs the selected signal. The alarm circuit 10 as an operation circuit includes a judgment circuit 7
The operation starts in response to the output from the second output terminal 72, and generates an alarm output at the alarm output terminal 11 using the outputs of the first and second frequency divider circuits 2 and 3. Note that the alarm circuit 10 may not use the outputs of the first and second frequency dividing circuits 2 and 3. Note that the clock input terminal 1,
First frequency dividing circuit 2, second frequency dividing circuit 3, frequency dividing output terminal 4, signal control circuit 5, reset terminal 6, determination circuit 7, latch circuit 8, selector 9, alarm circuit 10, alarm output terminal 11. Are configured as one integrated circuit.
Next, the operation will be described with reference to FIGS. First, a normal operation will be described with reference to FIG. In FIG. 1, CK, F1, R, RH, SEL, F2, and O correspond to those in FIG.
3 shows voltage waveforms at terminals CK, F1, R, RH, SEL, F2, and O of FIG. Normally, a clock pulse is input to the clock input terminal 1 as shown in FIG. 2CK, which is frequency-divided by the first frequency dividing circuit 2, and an output as shown in FIG. 2F1 is generated at the terminal F1. At this time, the reset terminal 6
, The output of the first frequency dividing circuit 2 is transmitted to the reset terminal 6 via the signal control circuit 5, and the output of the first frequency dividing circuit 2 is output from the reset terminal 6 as shown in FIG. 2R. Produces an output similar to Therefore, by examining the output of the reset terminal 6, the operation of the first frequency dividing circuit 2 can be confirmed at normal times. At this time, since the reset terminal 6 is open, the input to the determination circuit 7 is the output of the buffer circuit 51. Since this is the same as the output of the first frequency divider 2, the output terminals 71 and 72 are It is maintained at “L” (see FIG. 2 RH, RL). Therefore, the output of the latch circuit 8 is maintained at "L" (FIG. 2).
SEL), the selector 9 selects and outputs the output of the first frequency divider 2 by this “L” (see FIG. 2F2), and the second frequency divider 3 outputs the output of the first frequency divider 2. Is divided, and a frequency-divided output terminal 4 generates a frequency-divided output. As described above, in a normal state in which the clock pulse is input to the clock input terminal 1 and the reset terminal 6 is open, the operation of the first frequency dividing circuit 2 can be confirmed by the output from the reset terminal 6. Further, a frequency-divided output of the clock pulse input to the clock input terminal 1 by the first frequency dividing circuit 2 and the second frequency dividing circuit 3 is obtained from the frequency dividing output terminal 4. Therefore, a divided output is obtained from the divided output terminal 4 in normal times. Next, the reset operation will be described with reference to FIG. In this case,
A first signal ("H") is externally applied to the reset terminal 6, and the reset terminal 6 is fixed at "H" as shown in FIG. 3R. This fixed time is longer than the pulse width of the clock pulse input to the clock input terminal 1. Note that when an “H” signal is externally applied to the reset terminal 6, the signal is supplied via a connection line having a sufficiently small resistance value. Also, as described above, the resistance 52 in the signal control circuit 5
Are sufficiently large. Which of the two signals input to the signal control circuit 5, that is, the signal from the reset terminal 6 and the signal from the first frequency divider 2 is input to the determination circuit 7 preferentially depends on whether each signal is In the case of this example, the reset terminal 6 is connected to the reset terminal 6 via a connection line having a sufficiently small resistance since the resistance is determined according to the magnitude relation of the resistance of the passing resistor.
Is given priority and is supplied to the determination circuit 7. By this input, the judgment circuit 7 generates "H" at the output terminal 71. The latch circuit 8 holds “H” of the output terminal 71 while the clock pulse input from the clock input terminal 1 is “L” (see SEL in FIG. 3). When the output of the latch circuit 8 becomes “H”, the selector 9 selects “H” input through the signal control circuit 5 and supplies it to the second frequency dividing circuit 3. Further, “H” of the output terminal 71
As a result, the second frequency dividing circuit 3 is reset. As described above, while the first signal (“H”) is being supplied to the reset terminal 6 from the outside, the second frequency dividing circuit 3 is reset, so that the output from the frequency dividing output terminal 4 is “L”. "Is held. To release the reset, reset terminal 6
Is stopped. by this,
“H” at the output terminal 71 of the determination circuit 7 changes to “L” and the reset of the second frequency divider 3 is released.
The same operation as in normal operation is performed. Next, the test operation of the second frequency divider 3 will be described with reference to FIG. In this case, once "H" is applied to the reset terminal 6 from the outside as described above to bring the reset terminal 6 into the reset state as described above,
The supply of the signal to the clock input terminal 1 is fixed at "L". Thereafter, when an external clock pulse as a second clock pulse is input to the reset terminal 6, the determination circuit 7 stops “H” to the output terminal 71 and changes the state of the output terminal 71 to “L”. As a result, the reset of the second frequency dividing circuit 3 is released. At this time, since the input of the clock pulse to the clock input terminal 1 is stopped, the latch circuit 8 holds “H”, and the selector 9 continues to select the signal to be input via the signal control circuit 5. Therefore, the second
The external clock signal input to the reset terminal 6 is supplied to the frequency dividing circuit 3, and the second frequency dividing circuit 3 operates by this external clock pulse to divide the frequency divided output to the frequency divided output terminal 4.
Output to Therefore, the operation of the second frequency divider 3 can be confirmed by testing the output of the second frequency divider 3 at this time. In addition, the reset terminal 6 keeps “L” for longer than the pulse width of the clock pulse input to the clock input terminal 1.
Is supplied to the judgment circuit 7, the judgment circuit 7 generates "H" at the output terminal 72 by this input, the alarm circuit 10 operates according to this output, and outputs the alarm output to the alarm output terminal 11. appear. Thus, the first
Since the frequency dividing circuit composed of the frequency dividing circuit 2 and the second frequency dividing circuit 3 can be completely divided into the first half and the second half of the test, the inspection time can be shortened and the cost for the inspection can be reduced. Further, since the alarm function can be controlled without increasing the number of control terminals, the size of the configuration can be reduced. In the above description, the reset is performed in a state where the reset terminal 6 is fixed at “H”.
The alarm output is generated in a state where the alarm output is fixed at “L”. However, the alarm output may be changed in the opposite manner or may be changed as appropriate. In the above description, the alarm circuit is used as the operation circuit, but the present invention is not limited to this and can be changed as appropriate.
For example, a circuit or the like that changes the frequency, duty, or the like of the frequency division output output from the frequency division output terminal 4 during normal operation may be used.

According to the present invention, there are provided a clock input terminal to which a first clock pulse signal can be externally inputted, a first frequency dividing circuit for dividing the first clock pulse signal, and a desired signal from the outside. And a reset terminal capable of inputting a second clock pulse signal, and an output terminal of the first frequency divider circuit and the reset terminal. A signal input from the outside to the reset terminal is the first terminal. A signal control circuit for inhibiting transmission to the output terminal side of the frequency divider circuit and outputting a signal corresponding to the output of the first frequency divider circuit to the reset terminal side; and an output of the first frequency divider circuit. Selecting means for outputting one of the signals input to the reset terminal, a second frequency dividing circuit for dividing the output of the selecting means,
A determination circuit that outputs a predetermined signal when the desired signal is input to the reset terminal, and holds an output state of the determination circuit when a desired level of the first clock pulse signal that is input to the clock input terminal A latch circuit, wherein the second frequency dividing circuit is reset while the desired signal is being input to the reset terminal, and the selecting means is configured such that the latch circuit holds the predetermined signal. In this case, a signal input to the clock input terminal is selected and output, and when the latch circuit holds a signal different from the predetermined signal, an output of the first frequency dividing circuit is selected. And outputting the second clock pulse signal from the outside to the reset terminal when the selection means selects a signal to be input to the clock input terminal. Therefore, each of the first frequency divider circuit and the second frequency divider circuit can be tested without newly adding a test terminal, the chip area of the integrated circuit can be reduced, and the cost can be reduced. Therefore, when the entire frequency dividing circuit is divided into the former stage and the latter stage, the inconvenience that conventionally only the latter stage can be tested can be solved. A clock input terminal to which a first clock pulse signal can be externally input;
A first frequency divider for dividing the frequency of the clock pulse signal, a reset terminal capable of externally inputting a first signal, a second signal, and a second clock pulse signal; An output terminal provided between the output terminal and the reset terminal, for preventing a signal input from the outside to the reset terminal from being transmitted to the output terminal side of the first frequency divider; A signal control circuit that outputs a signal corresponding to an output to the reset terminal side; a selection unit that outputs one of an output of the first frequency divider circuit and a signal that is input to the reset terminal; A second frequency divider for dividing the output; and a first and a second output terminal, wherein the first signal is input to the reset terminal when the first signal is input to the reset terminal.
A determination circuit that outputs a third signal from an output terminal of the first input terminal and outputs a fourth signal from the second output terminal when the second signal is input to the reset terminal; A latch circuit for holding an output state of the first output terminal at a desired level of the first clock pulse signal, and an operation circuit for executing a desired operation in response to the output of the fourth signal. The frequency dividing circuit is reset while the first signal is being input, and the selecting means is input to the clock input terminal when the latch circuit holds the third signal. Selecting and outputting a signal, and when the latch circuit holds a signal different from the third signal, selects and outputs the output of the first frequency dividing circuit; Select the signal to be input to the input terminal. When you are, the second clock pulse signal from the outside to the reset terminal is input.
Therefore, while solving the same problem as described above, even if an operation circuit performing a desired operation is added to the integrated circuit, it is not necessary to add a control terminal for the operation circuit, and the chip area of the integrated circuit can be reduced. Cost can be reduced. The signal control circuit is a series circuit of a buffer circuit and a resistor, the input side of the buffer is connected to the output terminal of the first frequency divider, one end of the resistor is connected to the output side of the buffer, Is connected to the reset terminal, so as to solve the same problems as above,
With a simple configuration, it is possible to prevent the output of the first frequency divider circuit from being adversely affected by the signal input state to the reset terminal.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of FIG. 1;

FIG. 4 is a block circuit diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 1 clock input terminal 2 first frequency divider 3 second frequency divider 5 signal control circuit 51 buffer circuit 52 resistor 6 reset terminal 7 determination circuit 71 first output terminal 72 second output terminal 8 latch circuit 9 selection Means 10 Operating circuit

Claims (3)

[Claims] A clock input terminal to which a first clock pulse signal can be externally inputted; a first frequency dividing circuit for dividing the first clock pulse signal; A reset terminal to which a clock pulse signal can be input; and a reset terminal provided between an output terminal of the first frequency divider and the reset terminal, wherein a signal externally input to the reset terminal is the first frequency divider. A signal control circuit for prohibiting transmission to the output terminal side and outputting a signal corresponding to the output of the first frequency dividing circuit to the reset terminal side; an output of the first frequency dividing circuit and the reset terminal Selecting means for outputting any one of the signals input to the second circuit, a second frequency dividing circuit for dividing the output of the selecting means, and outputting a predetermined signal when the desired signal is input to the reset terminal Judgment times And a latch circuit for holding an output state of the determination circuit at a desired level of the first clock pulse signal input to the clock input terminal. The second frequency dividing circuit includes Reset is performed while a desired signal is being input. When the latch circuit holds the predetermined signal, the selection means selects and outputs a signal to be input to the clock input terminal, and outputs the latch signal. When the circuit holds a signal different from the predetermined signal, the output of the first frequency divider is selected and output, and the selector selects a signal to be input to the clock input terminal. Wherein the second clock pulse signal is externally input to the reset terminal. 2. A clock input terminal capable of externally inputting a first clock pulse signal, a first frequency dividing circuit for dividing the first clock pulse signal, an external first signal and a second signal. And a reset terminal to which a second clock pulse signal can be input, and an output terminal of the first frequency divider circuit and the reset terminal, and a signal externally input to the reset terminal is A signal control circuit that inhibits transmission to the output terminal of the first frequency divider and outputs a signal corresponding to the output of the first frequency divider to the reset terminal; and the first frequency divider. Selecting means for outputting one of the output of the resetting terminal and a signal input to the reset terminal, a second frequency dividing circuit for dividing the output of the selecting means, and first and second output terminals, The first signal is applied to the reset terminal. A determination circuit that outputs a third signal from the first output terminal when input, and outputs a fourth signal from the second output terminal when the second signal is input to the reset terminal; A latch circuit for holding an output state of the first output terminal at a desired level of the first clock pulse signal input to the clock input terminal; and an operation of executing a desired operation by outputting the fourth signal The second divider circuit is reset while the first signal is being input, and the selecting means is configured to output the signal when the latch circuit holds the third signal. A signal input to the clock input terminal is selected and output. When the latch circuit holds a signal different from the third signal, the output of the first frequency divider is selected and output. The selection means is the clock When you select a signal to be inputted to the force terminal, dividing the test function with integrated circuits, characterized in that the externally to the reset terminal second clock pulse signal is inputted. 3. The signal control circuit according to claim 1, wherein the signal control circuit comprises a series circuit of a buffer circuit and a resistor, wherein an input side of the buffer circuit is connected to an output terminal of the first frequency divider circuit, An end of the resistor is connected to the output side of the buffer circuit, and the other end of the resistor is connected to the reset terminal.