JP2000332718A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit a signal suitable to a control system among circuit blocks by transmitting many signals with a small wiring number and a narrow wiring area, without constraining timings. SOLUTION: A multiplexer circuit 2 in a 1st circuit block 9 multiplexes control signals fed from an input terminal 1 on a transmission signal and transmits the multiplexed signal to a demultiplexer circuit 5 a 2nd circuit block 10. In this case, a coding circuit 4 encodes an enable signal at an enable terminal 3 of the 2nd circuit block 10 into a selection signal denoting a selection pattern of the multiplexer circuit 2 and gives the coded signal to the multiplexer circuit 2 of the 1st circuit block 9 to control the selection of the multiplexer circuit 2. Furthermore, the enable signal at the enable terminal 3 is also given to a demultiplexer circuit 5 of the 2nd circuit block 10 to control the demultiplexer circuit 5 in relation to the selection of the multiplexer circuit 2, to allow the demultiplexer circuit 5 demultiplex the multiplexed transmission signal received via a transmission signal line 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit composed of a plurality of circuit blocks, and more particularly to a semiconductor integrated circuit having improved signal transmission between circuit blocks.

[0002]

2. Description of the Related Art In recent years, the number of internal wirings in an integrated circuit has increased due to the miniaturization and large scale of the configuration of the integrated circuit, and the area of the wiring region in the layout has tended to increase. In particular, the number of signals of the control system between the circuit blocks becomes enormous.

Conventionally, in a semiconductor integrated circuit composed of a plurality of circuit blocks, when signals are transmitted between circuit blocks, the circuit blocks are simply connected by a number of signal lines corresponding to the required number of signals. Signal transmission. That is, conventionally, as shown in FIG. 4, when 16 signals, for example, 16 bits, are transmitted from the first circuit block 101 to the second circuit block 102, 16 signal lines 103 are provided between the circuit blocks. It was necessary to provide.

Further, when address information is transferred in a semiconductor memory device, the number of address information (for example, the number of bits),
Conventionally, address information is transferred using a smaller number of bus lines. An example of a conventional configuration for reducing the number of bus lines by simply transferring address information in a time-division manner is disclosed in, for example, Japanese Patent Application Laid-Open No. 60-109094.

A conventional technique disclosed in Japanese Patent Application Laid-Open No. 60-109094 will be described with reference to FIG. FIG. 5 shows an example in which an address signal is supplied from the address transmission unit 1 on the access circuit side for reading / writing the storage circuit to the address reception unit 2 on the storage circuit side. The clock signal CLK input to the clock input terminal 208 is counted in the counter circuit 220, and the counter circuit 220
Are output to the first and second decoder circuits 218 and 219 via the control bus line 206. The first decoder circuit 218 decodes the count output and outputs the first to fourth switch circuits 210 to 210 via the switch control signal 204 based on the decoding result.
213 is controlled. First to fourth switch circuits 210 to 210
Reference numeral 213 performs connection / disconnection, that is, connection / disconnection between the address bus 203 and the address input terminal 203, that is, the address inputs A0 to A15.

At this time, the first switch circuit 210
The address inputs A0 to A3 of the address input terminal 203 are connected to and separated from the address bus line 205. The second switch circuit 211 connects / disconnects between address inputs A4 to A7 of the address input terminal 203 and the address bus line 205. The third switch circuit 212 connects / disconnects between address inputs A8 to A11 of the address input terminal 203 and the address bus line 205. Then, the fourth switch circuit 213 connects / disconnects between the address inputs A12 to A15 of the address input terminal 203 and the address bus line 205. That is, the first decoder circuit 218 selectively controls the first to fourth switch circuits 210 to 213 in accordance with the count output of the counter circuit 220, and connects the address inputs A0 to A15 of the address input terminal 203 with the address inputs. The connection to and separation from the bus line 205 is performed.

[0007] The second decoder circuit 219 decodes the count output of the counter circuit 220 and outputs the first output via the data holding control signal line 207 based on the decoding result.
To the fourth data holding circuits 214 to 217. The first to fourth data holding circuits 214 to 217 selectively take in an address signal transferred via the address bus line 205 and hold the data. At this time, the first
The fourth to fourth data holding circuits 214 to 217 respond to a data holding control signal selectively applied from the second decoder circuit 219 via the data holding control signal line 207, and operate on the address bus line 205. Data is taken in and held, and output to the address signal output terminal 209.

That is, the first and second decoder circuits 218 and 219 operate based on the count output from the counter circuit 220 in the first to fourth switch circuits 210 and 219.
To 213 and first to fourth data holding circuits 214 to 2
17 are selectively operated to cyclically select address signals and hold data. FIG. 6 shows an operation waveform in an example of this operation.

For example, when a predetermined count value (for example, an initial value) signal is output from the counter circuit 220, the first and second decoder circuits 218 and 219
The first switch circuit 210 and the first data holding circuit 214 are selected, and the data of the address inputs A0 to A3 are taken into the first data holding circuit 14 via the address bus line 205. Next, the clock signal CLK is input to the clock input terminal 208 of the counter circuit 220, and the counter circuit 220 counts, so that the second switch circuit 211 and the second data holding circuit 215
Is selected, and the data of the address inputs A4 to A7 are transferred via the address bus line 5 and taken into the second data holding circuit 215. At this time, the first data holding circuit 14 holds the previously taken address data of the address inputs A0 to A3. Thereafter, the same operation is performed by the address inputs A8 to A11, the third switch circuit 212 and the third data holding circuit 216, and the address inputs A12 to A15, the fourth switch circuit 213 and the fourth
For the data holding circuit 217. As a result, the signals of the address inputs A0 to A15 are held in the first to fourth data holding circuits 214 to 217, and four address bus lines 205 and two control bus lines 206, that is, a total of six bus lines And 16 address signals A0 to A
15 can be obtained by the address receiving unit 202 on the storage circuit side.

In the above description, the first switch circuit 210 and the first data holding circuit 214 are selected first, that is, the addresses of the address inputs A0 to A3 are transferred first. The selection order of the first to fourth switch circuits 210 to 213 and the first to fourth data holding circuits 214 to 217 is as follows.
Can be arbitrarily set by the decoder circuits 218 and 219. Also, the control bus line 206 shown in FIG.
Is driven by the counter circuit 220, but the control bus line 206 may be directly driven from outside the semiconductor memory device.

[0011]

As described above, the number of internal wirings in an integrated circuit has increased due to the miniaturization and large scale of the integrated circuit, and the area of the wiring region in the layout has increased. The number of signals in the control system between blocks becomes enormous. If the number of wirings is reduced by simply transferring signals in a time-division manner as disclosed in Japanese Patent Application Laid-Open No. 60-109094, the transmission timing is fixedly determined. For this reason, there has been a problem that the technique of reducing the number of wirings by time division cannot be adopted for a signal of a control system with random timing.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and enables transmission of many signals in a small number of wirings and a narrow wiring area without restricting timing, thereby enabling control between circuit blocks. It is an object of the present invention to provide a semiconductor integrated circuit suitable for transmission of a system signal.

[0013]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention comprises a plurality of circuit blocks and transmits signals between the circuit blocks. A multiplexing circuit that is provided in the first circuit block on the transmission side of the transmission signal of the blocks and selectively switches and multiplexes the transmission signal; and a multiplexing circuit on the reception side of the transmission signal of the plurality of circuit blocks. And a coding circuit provided in the second circuit block for controlling the selection of the transmission signal of the multiplexing circuit, and a transmission signal provided in the second circuit block and corresponding to the selection of the transmission signal of the multiplexing circuit. And a separation circuit for separating and taking out.

The multiplexing circuit includes a plurality of registers for temporarily holding the transmission signal, and a selector for selectively switching and outputting the outputs of the plurality of registers in response to the output of the encoding circuit. You may go out.

[0015] The separation circuit may include a plurality of registers for selectively receiving and holding a transmission signal in response to an output of the encoding circuit.

In the semiconductor integrated circuit of the present invention, a multiplexing circuit for selectively switching a signal is provided on a side for transmitting a transmission signal between circuit blocks for transmitting a signal, and the multiplexing circuit is provided on a side for receiving a transmission signal. An encoding circuit for controlling the switching operation of the circuit and a separating circuit for selectively separating and holding the multiplexed signal are provided, and the multiplexing circuit on the transmitting side is controlled by the encoding circuit on the receiving side to be multiplexed. The transmitted transmission signal is transmitted between blocks and separated by a separation circuit on the receiving side. Therefore, the number of signals for transmitting control signals and the like between the circuit blocks can be reduced, and the area of the wiring region of the semiconductor integrated circuit can be reduced. Moreover, since the transmission timing is not restricted, the present invention can be applied to transmission of a control signal in which signal transmission occurs at random timing.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

The semiconductor integrated circuit shown in FIG. 1 has a control signal input terminal 1, a multiplexing circuit 2, an enable terminal 3, an encoding circuit 4, a separating circuit 5, a control signal output terminal 6, and a transmission signal line 7.
And a selection signal line 8. Control signal input terminal 1
And the multiplexing circuit 2 includes a first circuit block 9 on the transmitting side.
The enable terminal 3, the encoding circuit 4, the separation circuit 5, and the control signal output terminal 6 are provided in the second circuit block 10 on the receiving side. The transmission signal line 7 and the selection signal line 8 form a signal line between the first and second circuit blocks 9 and 10. The semiconductor integrated circuit shown in FIG. 1 transmits a control signal from, for example, a first circuit block 9 to a second circuit block 10.

The multiplexing circuit 2 selects a plurality of control signals supplied to the control signal input terminal 1 in response to a selection signal provided from the encoding circuit 4, and selects a smaller number of signals than the original control signal. Output to the road. The encoding circuit 4 encodes the enable signal supplied to the enable terminal 3 and generates a selection signal to be supplied to the multiplexing circuit 2. Separation circuit 5
Separates the signal transmitted from the multiplexing circuit 2 in response to the enable signal to obtain a control signal at the control signal output terminal 6.

A control signal generated in the first circuit block 9 is input to the multiplexing circuit 2 via the control signal input terminal 1. Note that the control signal may be generated in another circuit block or the like outside the first circuit block 9 and input to the control signal input terminal 1 of the first circuit block 9. The output of the multiplexing circuit 2 is input to the separation circuit 5 in the second circuit block 10 via the transmission signal line 7. The output of the separation circuit 5 is taken out from the control signal output terminal 6 and is used in the second circuit block 10 or transferred to another circuit block. An enable signal indicating transfer permission is generated in the second circuit block 10 and is input to the separation circuit 5 and the encoding circuit 4 via the enable terminal 3. The enable signal may be generated in another circuit block or the like outside the second circuit block 10 and input to the enable terminal 3 of the second circuit block 10. The encoded output of the encoding circuit 4 is sent to the multiplexing circuit 2 instead of the first circuit block 9 via a selection signal line 8 between the first circuit block 9 and the second circuit block 10. Input as a signal.

Next, the operation of the semiconductor integrated circuit configured as shown in FIG. 1 will be described.

The control signal supplied from the control signal input terminal 1 in the first circuit block 9 is multiplexed by the multiplexing circuit 2 and transmitted to the separation circuit 5 in the second circuit block 10. At this time, the encoding circuit 4 encodes the enable signal at the enable terminal 3 of the second circuit block 10 into a selection signal indicating a selection pattern of the multiplexing circuit 2, and the multiplexing circuit 2 of the first circuit block 9 To control the selection operation of the multiplexing circuit 2. The enable signal at the enable terminal 3 is also input to the separation circuit 5 of the second circuit block 10 and controls the separation circuit 5 in connection with the selection operation of the multiplexing circuit 2 so that the transmission signal line 7
To separate the multiplexed transmission signal received via

That is, the circuit block 9 for transmitting a signal
A multiplexing circuit 2 for selectively switching a signal is provided on a side for transmitting a transmission signal between the multiplexing circuit 4 and a coding circuit 4 for controlling the multiplexing circuit 2 on a side for receiving a transmission signal. A multiplexing circuit 2 on the transmission side is controlled by the encoding circuit 4 on the reception side to transmit the multiplexed transmission signal between the blocks. The separation circuit 5 on the side separates the signals.

By using such a circuit configuration, it is possible to reduce the number of signal lines when transmitting control signals and the like between circuit blocks of the semiconductor integrated circuit, and to reduce the area of the wiring region of the semiconductor integrated circuit. Becomes possible. In the case of time-division transmission as disclosed in Japanese Patent Laid-Open No. 60-109094, the timing of signal transmission is fixedly determined. However, in the configuration shown in FIG. Is determined, so that the present invention can be applied to transmission of a control signal generated at irregular timing.

FIG. 2 shows a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

The semiconductor integrated circuit shown in FIG. 2 includes a first circuit block 21 on the transmitting side and a second circuit block 22 on the receiving side. The first and second circuit blocks 21 and 22 include first to eighth registers 31 to 38,
First to fourth enable terminals 39 to 42, encoding circuit 4
3, selector 44, transmission signal line 45, selection signal line 46,
A control signal input terminal 47 and a control signal output terminal 48 are provided. The first to fourth registers 31 to 34, the selector 44, and the control signal input terminal 47 constitute a multiplexing circuit 49, and the multiplexing circuit 49 is provided in the first circuit block 21. . Fifth to eighth registers 3
5 to 38 and the control signal output terminal 48
And the separation circuit 50 and the first to the above-described first to fifth embodiments.
Fourth enable terminals 39 to 42 and encoding circuit 43
Is provided in the second circuit block 22. The transmission signal line 45 and the selection signal line 46 form a signal line between the first and second circuit blocks 21 and 22. The semiconductor integrated circuit of FIG. 2 transmits a control signal from the first circuit block 21 to the second circuit block 22, for example.

Each of the first to eighth registers 31 to 38 is, for example, a 4-bit register. Each of the first to fourth registers 31 to 34 is provided with four
A control signal for each bit is input, and a control signal for each 4 bits is output to the control signal output terminal 48 from the fifth to eighth registers 35 to 38. Each bit of the 4-bit enable signal is input to each of the first to fourth enable terminals 39 to 42.

Selector 44 constituting multiplexing circuit 49
Are responsive to a selection signal provided from the encoding circuit 43 via the selection signal line 46 to the first to fourth registers 31 to
One of the outputs 34 is selected and output to the transmission signal line 45 as a 4-bit transmission signal. Encoding circuit 4
3 is a 2-bit selection signal for selecting any of the first to fourth registers 31 to 34 according to a 4-bit enable signal supplied to the first to fourth enable terminals 39 to 42. Is generated and supplied to the selector 44. The selector 44 selects one of the outputs of the first to fourth registers 31 to 34 in response to the selection signal and makes the output valid (active), and uses the 4-bit output of the register as a transmission signal. The signal is transmitted to the transmission signal line 45.
Fifth to eighth registers 35 to 3 constituting separation circuit 50
8, one of the registers based on the 4-bit enable signal supplied to the first to fourth enable terminals 39 to 42 fetches and updates the signal transmitted from the transmission signal line 45, and thereafter updates Hold until updated. Therefore, the number of signal lines is four for the transmission signal line 45 and two for the selection signal line 46.

Each 4-bit output of the first to fourth registers 31 to 34 in the multiplexing circuit 49 of the first circuit block 21 is input to the selector 44. The selector 44 includes
One of the four registers 31-34 selects and outputs the 4-bit output. The output of the selector 44 is supplied to the separation circuit 50 of the second circuit block 22 through the transmission signal line 45.
Are input to the fifth to eighth registers 35 to 38 of 4 bits. The 4-bit enable signals at the first to fourth enable terminals 39 to 42 of the second circuit block 22 are input to the fifth to eighth registers 35 to 38 and also to the encoding circuit 43. . Encoding circuit 43
Is output to the first circuit block 2 via the selection signal line 46.
1 multiplexing circuit 44.

Next, the operation of the semiconductor integrated circuit configured as shown in FIG. 2 will be described with reference to a time chart shown in FIG.

As shown in FIG. 3, the 4-bit output control signals of the first to fourth registers 31 to 34 are respectively set to D0.
To D3. When the control signal D0 is transmitted from the first circuit block 21 to the second circuit block 22, for example, the enable signals of the enable terminals 39 to 42 are set to '0111' and the fifth to eighth registers 35 are set.
Only the fifth register 35 of .about.38 is activated (by giving '0'). At this time, the selection signal 46 between the blocks becomes 0 ('00') and controls the selector 44.
1 output D0 is selected and output. Therefore, the transmission signal 15 between the blocks becomes the control signal D0 output from the first register 31. This control signal D0 is the fifth to eighth control signals.
As described above, since only the fifth register 35 is activated by the enable signal, the control signal D0 is taken into the fifth register 35, and the sixth to 8 registers 36-38
Retains the previous value.

Thereafter, similarly, the control signals D1 to D3, which are the respective outputs of the second to fourth registers 32 to 34, sequentially change any one of the enable signals of the enable terminals 39 to 42 to ' By setting it to 0 ', the second to fourth
In registers 36 to 38.

With such a circuit configuration, the number of signal lines for transmitting control signals and the like between circuit blocks of the semiconductor integrated circuit can be reduced, and the area of the wiring region of the semiconductor integrated circuit can be reduced. . In FIG. 2, while the total number of control signals is 16, the number of selection signal lines 46 from the encoding circuit 43 to the selector 44 is only two, and the number of transmission signal lines 45 is four. Therefore, transmission can be performed by a total of six signal lines. Also in this case, since the enable signals of the enable terminals 39 to 42 determine the signal transmission timing, the present invention can be applied to transmission of a control signal generated at irregular timing.

[0035]

As described above, according to the present invention,
It is possible to transmit a large number of signals in a small number of wirings and a narrow wiring area without restricting the timing, and to provide a semiconductor integrated circuit suitable for transmitting a control system signal between circuit blocks.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a time chart for explaining an operation of the semiconductor integrated circuit of FIG. 2;

FIG. 4 is a block diagram showing a configuration of an example of a conventional semiconductor integrated circuit.

FIG. 5 is a block diagram showing a configuration of another example of a conventional semiconductor integrated circuit.

FIG. 6 is a time chart for explaining the operation of the semiconductor integrated circuit of FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 control signal input terminal 2 multiplexing circuit 3 enable terminal 4 encoding circuit 5 separation circuit 6 control signal output terminal 7 transmission signal line 8 selection signal line 9 first circuit block 10 second circuit block 21 first circuit Block 22 Second circuit block 31 to 38 Register (4 bits) 39 to 42 Enable terminal 43 Encoding circuit 44 Selector 45 Transmission signal line 46 Selection signal line 47 Control signal input terminal 48 Control signal output terminal 49 Multiplexing circuit 50 Separation circuit

Claims (3)

[Claims] 1. A semiconductor integrated circuit comprising a plurality of circuit blocks and performing signal transmission between the circuit blocks, wherein the semiconductor integrated circuit is provided in a first circuit block on a transmission signal transmission side of the plurality of circuit blocks, and A multiplexing circuit for selectively switching and multiplexing a signal; and a multiplexing circuit provided in a second circuit block on the receiving side of the transmission signal among the plurality of circuit blocks, for controlling selection of a transmission signal of the multiplexing circuit. A semiconductor integrated circuit, comprising: an encoding circuit; and a separation circuit provided in the second circuit block and separating and extracting a transmission signal in accordance with selection of a transmission signal of the multiplexing circuit. . 2. The multiplexing circuit includes: a plurality of registers for temporarily holding the transmission signal; a selector for selectively switching and outputting the outputs of the plurality of registers in response to an output of the encoding circuit; 2. The semiconductor integrated circuit according to claim 1, comprising: 3. The apparatus according to claim 1, wherein said separation circuit includes a plurality of registers for selectively taking in and holding a transmission signal in response to an output of said encoding circuit. Semiconductor integrated circuit.