JP2000322377A - Data transfer controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control time from a transfer request until transfer is started by interrupting the transfer when the transfer is performed with the maximum value of a transfer period surpassed and also another function requests transfer and starting the transfer of the function requesting transfer. SOLUTION: An internal request controlling part 12 receives a request of a master 1 function 14, and a bus I/F controlling part 11 requests a system bus 1 for transfer and starts the transfer of the function 14. Next, a master 2 function 15 sends a transfer request to the part 12. When the transfer of the master 1 function is not finished even after a period set to a maximum continuous 1 register 16 passes, the request controlling part 12 instructs the I/F controlling part 11 to interrupt the transfer of the function 15. The part 11 finishes the transfer of the function 14 as early as possible and starts to transfer the function 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data transfer via a bus, and more particularly to a data transfer control device suitable for maintaining real-time data transfer.

[0002]

2. Description of the Related Art In recent years, with the advance of multimedia technology, a demand for efficiently transferring a large amount of data, such as moving image data, inside information equipment has become increasingly important. The operation when data is retransmitted by the conventional technique will be described. When data is transferred via a bus, generally, the master requesting the data transfer determines the type of data transfer (memory space or I / O).
Command, such as space or the like, and the direction of data transfer (read or write), and output address information to specify the target of the transfer partner. As a result of decoding these, the device that determines that it is the transfer partner performs data transfer with the master as a target. When performing data transfer between the master and the target, the target may not be able to temporarily transfer data to the command and address specified by the master. For example, DR
In a system using AM, data transfer cannot be performed when a memory cell is refreshed. In such a case, the master waits (inserts a wait cycle) until the target can perform data transfer, and performs data transfer when data transfer becomes possible. However, when a wait cycle is inserted, data transfer is not performed during that time, so that the data transfer rate is reduced. Therefore, when the target cannot temporarily perform the data transfer, this is notified to the master side, and the transfer operation (transaction) of the bus is temporarily stopped so that the data transfer of another master can be performed. Then, after a certain time has elapsed, the master again requests the target to transfer data. By doing so, the bus can be used efficiently. As described above, as a bus from which a bus transaction can be completed from the target side, the “PCI bus overview, interface 19
March 1997 issue, CQ Publishing Company, P.S. 100-116 ", PCI BUS (Peripheral C
component interconnect BUS)
There is.

Next, a case where a plurality of master functions transfer data will be described with reference to FIG. For example, when the master 1 function 14 transfers a plurality of data via the system bus 1, a request for data transfer is made to the bus I / F control unit 11, and the bus I / F control unit 11 Acquire the bus right and perform the actual data transfer. At this time, when the master 2 function also requests the data transfer, the normal bus I / F control unit 11 firstly completes the transfer of the plurality of data of the master 1 function 14 and then transfers the data of the master 2 function. I do. If the master 1 function 14
If the target function temporarily does not accept data transfer, data retransmission may occur, or the master 1 function 14 requests a large amount of data transfer on a bus capable of infinite length burst transfer, such as PCI Bus. In this case, the transfer requested by the master 2 function 15 may actually be performed much later even if no re-transfer occurs.

[0004]

When data is to be transferred by a bus device having a plurality of master functions by the conventional method, the data is transferred from the request for transfer as described above until the transfer is actually started. It can take quite a while,
For example, in the case where the master 2 function 15 in FIG. 2 is real-time data such as moving image data, a buffer or the like of the master 2 function 15 causes an overflow or the like to prevent data loss or overflow. Requires at least a buffer to store the data generated at that time from estimating the maximum time from issuing a request to actually starting the transfer.
However, estimating the maximum time requires detailed information of the target device and requires investigation, so a rather large buffer is usually used. In addition, the types of data to be handled are usually different depending on each master function, and there is a case where the data transfer can be performed more efficiently by freely changing the priority when performing the data transfer.

A first object of the present invention is to provide a data transfer control device capable of controlling the time from a transfer request to the start of actual transfer in data transfer on a bus. A second object of the present invention is to provide a data transfer control device capable of changing the priority of a master function for transferring data according to the type of data to be transferred.

[0006]

In order to achieve the first object, the data transfer control device of the present invention is provided with the following means. Means for inputting and outputting data connected to a bus for transferring data, a plurality of functions capable of inputting or outputting data connected to the means for inputting and outputting data, and transfer periods corresponding to each of the functions Means for holding the maximum value of the transfer, and interrupting the transfer during the transfer and requesting the transfer when the transfer is performed exceeding the maximum value of the transfer period and another function requires the transfer. Means for initiating the transfer of the function. In order to achieve the second object, the means for holding the maximum value of the transfer period corresponding to each of the above functions is made rewritable.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. Hereinafter, the first embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, reference numeral 20 denotes a bus device having a plurality of master functions according to the present invention, reference numeral 11 denotes a bus I / F control unit connected to the system bus 1, and reference numeral 12 denotes an internal request control for controlling the length of a transaction. 14 is a master 1 function for realizing a master function, 15 is a master 2 function for realizing another master function, 15 is a maximum continuation 1 register that can set a period during which the master 1 function can continue a transaction, and 16 Is a maximum continuation 2 register that can set a period during which the master 2 function can continue a transaction. Next, the operation will be described using these symbols. First, if the master 1 function 14 requests a transfer, the master 2 function 15 has not requested the transfer yet, so the internal request controller 12 receives the request of the master 1 function 14 and accepts the bus I / F.
It instructs the control unit 11 to accept the transfer request of the master 1 function 14.

[0008] Then, the bus I / F control unit 11 requests the system bus 1 for a transfer.
The transfer of the function 14 is started. Next, the master 2 function 15 also sends a transfer request to the internal request control unit 12. Therefore, if the transfer of the master 1 function has not been completed even after the period set in the maximum continuation 1 register 16 has been reached, the internal request control unit 12 sends the master 1 function to the bus I / F control unit 11 once. 14 is instructed to interrupt the transfer, and the master 2 function 15
To accept the transfer request. The bus I / F control unit 11 finishes the transfer of the master 1 function 14 performed on the system bus 1 as soon as possible, and
Start transfer. When such an operation becomes possible, for example, when a plurality of data transfers are performed by one request, the period set in the maximum continuation register is set even when the target device is temporarily in the busy state and the transfer cannot be performed. After that, the transfer by another master can be performed, so that the system bus can be used effectively. If there is no other device on the system bus, if the value set in the maximum continuation register of each master is known, the time from when a transfer request is issued to when the request is accepted can be easily known, so especially real-time data Suitable for transferring.

Also, in FIG.
By changing the value set to 6 and the maximum continuation 2 register 17, the priority can be given to the data transfer. That is, when the master 1 function 14 transfers data that requires real-time properties such as moving images, and the master 2 function 15 transfers data that does not require much real-time properties, the value of the maximum continuation 1 register 16 is changed. The value is set to be larger than the value of the maximum continuation 2 register 17 to extend the period in which the transaction can be continued. In this way, even if the data transfer of the master 2 function 15 is performed, when the master 1 function 14 makes a transfer request, the actual transfer can be started in a shorter period than the master 1 function 14 can continue. One function 14 can perform data transfer preferentially. At this time, if the value of the maximum continuation 2 register is kept to a minimum, the transfer of the master 1 function is executed immediately, so that the real-time property is easily maintained, and the time from when the request is issued until the request is accepted. The time is short and the buffer capacity is small. As described above, the priority can be set by changing the value of the maximum continuation register. Therefore, if the values of the maximum continuation 1 register 16 and the maximum continuation 2 register are made rewritable, the master 2 function 15 can be reversed in the above description.
The user can easily give priority to the master 1 function 14 and various settings such as temporarily changing the priority are convenient.

Next, an example of the internal request control unit which is a feature of the present invention will be described in detail with reference to FIG. In FIG. 3, reference numeral 31 denotes a counter which counts up when the transfer of the master 1 function is performed, and is in a reset state otherwise, 32 denotes a comparator for comparing the counter 31 with the maximum continuation 1 register, and 33 denotes a comparator. A priority 1 register indicating priority, 34, 35 and 37 are AND circuits, 36 is an OR circuit, 38 holds "1" when the SET terminal becomes "1", and the RST terminal becomes "1". Holds '0' when it becomes F.
F. A (flip-flop) circuit 41 is a counter which counts up when the transfer of the master 2 function is performed and is in a reset state otherwise.
And 43, a priority 2 register indicating priority, and 44, 45, and 47 are ANs.
D circuit, 46 is OR circuit, 38 is SET terminal
F. Hold '1' when it becomes '1' and hold '0' when the RST terminal becomes '1' F. (flip flop)
Circuit. Next, the operation will be described using these symbols. First, a value is set in advance so that the priority 1 register 33 and the priority 2 register 43 are exclusive. That is, when "1" is set in the priority 1 register 33, "0" is set in the priority 2 register. When there is a request from the master 2 function and no request from the master 1 function, the AN
The output of the D circuit 45 becomes "1", the output of the OR circuit 46 becomes "1", and the master 2 function request signal 56 is activated.

When the transfer is started by the bus I / F control unit in response to this signal, the master 2 function transfer signal 54 becomes active, and the counter 41 counts up. If the value of the counter 41 is smaller than the value of the maximum continuation 2 register 17, the output of the comparator 42 is inactive. F. The circuit 48 holds “1” because the AND circuit 45 is once active, and the transfer can be continued while the master 2 function request signal 56 remains active. When the value of the counter 41 becomes larger than the value of the maximum continuation 2 register 17, the output of the comparator 42 becomes active. At this time, F. F. The circuit 48 holds "0" because the RST terminal becomes inactive. If there is no transfer request from the master 1 function, the transfer can be continued because the AND circuit 45 remains active, but if there is a transfer request from the master 1 function, the output of the AND circuit 45 becomes inactive. The priority 1 register 33 stores the master 2
When the function request signal 56 becomes active, “1” is set, and when the master 1 function request signal 53 becomes active, “0” is set. Similarly, the priority 2 register 43 stores the master 1 function request signal 53 Is set to '1' when is activated, and '0' is set when the master 2 function request signal 56 is activated. Then, the priority 1 register is '1'
, The output of the AND circuit 34 becomes active. F. The circuit 38 becomes "1", the master 1 function request signal 53 becomes active, and the transfer of the master 1 function starts. In this way, each master function can continue the transfer for the period set by the value of the maximum continuation register.If there is a request from multiple master functions, the transfer is temporarily interrupted and another master function can be transferred. When there is a request from only one master function, the transfer can be further continued. Further, since the priority of the master function that has performed the transfer becomes lower, the transfer of each master can be performed efficiently without transferring only the specific master function.

Next, a second embodiment will be described with reference to FIGS. In the first embodiment, only a case where there are a plurality of master functions has been described. However, a case where a target function is added as shown in FIG. 4 will be described. In FIG.
Is a target function for realizing a transfer function from another device, and 18 is a maximum continuation 3 register for setting a period during which the target function 13 can continue a transaction.
Is a CPU, and 4 is a bus bridge connecting the CPU bus and the system bus 1. Next, the operation will be described focusing on the target function. For example, when the CPU 3 is transferring data to the target function 13 in the bus device 20 connected to the system bus 1 via the bus bridge 2, the arbiter that arbitrates the master right of the system bus 1 Depending on the construction, the system bus 1 may be occupied for a long time. In such a case, the master 1 function 14 and the master 2
When the function 15 requests the data transfer, the real-time property of the data may be lost. Therefore, the transfer to the target function 13 is performed for the period set in the maximum continuation 3 register 18 and at least one master function is performed. When a transfer request is issued from the
It requests a transfer interruption via the F control unit 11.

By doing so, once the system bus 1
And requesting the arbitration of the bus right may allow the request of the master function. If the system bus 1 has only the bus device 20 and the bus bridge 2, there is a very high possibility that the request for the master function is permitted and the real-time data can be maintained in some cases. Next, an internal request control unit according to the second embodiment will be described with reference to FIG.
In FIG. 5, reference numeral 61 denotes a counter which counts up when the target function is being transferred, and is in a reset state otherwise. Reference numeral 62 denotes a comparator which compares the counter 61 with a maximum continuous 3 register, and 63 denotes an OR. A circuit 64 is an AND circuit. If the target function 13 is transferring data from the target transfer signal 65, the counter 61 counts up, and the comparator 62 compares the value and the size of the maximum continuous 3 register, and the counter 61 is larger and
When there is a transfer request from the master 1 function or the master 2 function, the target transfer interruption signal 66 is activated to request the interruption of the transfer from the target function. In this way, the transfer of the master function can be performed by temporarily suspending the transfer of the target.

Next, a third embodiment will be described with reference to FIGS. In the above description, the case of connection to the system bus has been described. However, as shown in FIG. 6, a local bus device is connected to the bus device by an expansion board such as a personal computer via the memory 102 of FIG. 6 or the local bus 111 of FIG. 112 may be connected, but also when the memory 101 of FIG. 6 or the local bus 111 of FIG. 7 has a master function of a plurality of memories, the maximum period that can continue to transfer data is set. Possible memory maximum continuation 1 register 107 and memory maximum continuation 2 register 108 in FIG. 6 and local bus maximum continuation 1 register 11 in FIG.
7, the local bus maximum continuation 2 register 118. The memory request shown in FIG. 6 which can perform a transfer after the maximum period that can be continued and temporarily interrupt the transfer and change the priority when another device requests the transfer. It is easily understood that the control unit 106 and the local bus request control unit 116 shown in FIG. 7 can perform the same control as the bus device connected to the system bus.

Further, since the number of master functions to be connected is specified in an expansion board or the like, the maximum delay time from when a request is issued to when transfer can be performed can be calculated. Is preferred.

[0016]

As described above, according to one embodiment of the present invention, it is possible to set a limit on the number of times of data retransfer, and when the limit is exceeded, the fact is also imposed on the CPU. Can notify. Further, according to the embodiment of the present invention, the interval of data retransmission can be set, so that the rate of occupying the system bus can be reduced even when the target is slow.

With the addition of such a small amount of hardware, recovery from a failure can be performed even if a failure occurs in the target and data transfer cannot be performed. Even when a low-speed target is accessed, data transfer to other masters is affected. And the bus can be used efficiently even when transferring real-time data such as moving images and audio.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration for performing conventional data transfer.

FIG. 3 is a block diagram showing a first internal request control unit.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing a second internal request control unit.

FIG. 6 is a block diagram showing a third embodiment of the present invention having a local memory.

FIG. 7 is a block diagram showing a third embodiment of the present invention having a local bus.

[Explanation of symbols]

1 ... system bus, 2 ... bus bridge, 3 ...
CPU, 11: bus I / F control unit, 12: internal request control unit, 13: target function, 14: master 1 function,
15: Master 2 function, 16: Maximum continuation 1 register, 17
... 2 maximum continuation registers, 18 ... 3 maximum continuation registers, 2
0: Bus device, 31: Counter, 32
... Comparator, 33 ... Priority 1 register, 34 ... AND circuit, 35 ... AND circuit, 36 ... OR circuit,
37 ... AND circuit, 38 ... F. F. Circuit, 39 ...
OR circuit, 41 counter, 42 comparator, 43 priority 2 register, 44 AND circuit,
45 AND circuit, 46 OR circuit, 4
7 ... AND circuit, 48 ... F. F. Circuit, 49… OR
Circuit, 51: master 1 function transfer signal, 52:
Master 1 function transfer interrupt signal 53: Master 1 function transfer request signal 54: Master 2 function transfer signal 55:
Master 2 function transfer interruption signal, 56: Master 2 function transfer request signal, 61: Counter, 62: Comparator, 63: OR
Circuit: 64 AND circuit; 65: target function transfer signal; 66: target function transfer interrupt signal; 101: memory;
... Memory Master 1 function, 104 ... Memory Master 2 function,
105: memory I / F control unit, 106: memory request control unit, 107: memory maximum continuation 1 register, 108: memory maximum continuation 1 register, 111: local bus, 112: local bus device, 113
... local bus master 1 function, 114 ... local bus master 2 function, 115 ... local bus I / F control unit, 11
6 local bus request control unit 117 local bus maximum continuation 1 register 118 local bus maximum continuation 1 register

Continued on the front page (72) Inventor Morino Tokai 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside the Hitachi, Ltd.System Development Laboratory (72) Inventor Satoshi Kakizaki 5-2-1, Josuihoncho, Kodaira-shi, Tokyo (72) Inventor Ryuichi Agawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in Hitachi Image Information Systems, Ltd. 5B061 AA00 BA01 BB13 FF01 GG02 RR02

Claims (5)

[Claims] 1. A plurality of master functions connected to a bus for transferring data and for inputting and outputting the data, and a plurality of master functions connected to the means for inputting and outputting data and capable of issuing a request for inputting or outputting data. Means for holding a maximum value of a transfer period corresponding to each of the plurality of master functions, and performing transfer beyond the maximum value of the transfer period, and requesting a transfer by another function. A data transfer control device having means for interrupting the transfer when the transfer is present and starting the transfer of the function requesting the transfer. 2. The data transfer control device according to claim 1, wherein the means for holding the maximum value of the transfer period corresponding to each of the plurality of functions is rewritable. 3. The data transfer control device according to claim 1, wherein at least one target function that issues a request other than input or output of the data, and a transfer period for each of the target functions. Means for holding a maximum value period; and means for interrupting the transfer when the target function has performed the transfer beyond the maximum value of the transfer period and another master function has requested the transfer. A data transfer control device, characterized in that: 4. A data input / output unit for inputting / outputting data, a data holding unit connected to the data input / output unit and capable of rewriting the data, and connected to the data holding unit and the data input / output unit. A plurality of master functions capable of issuing a request for input or output of data, a means for holding a maximum value of a transfer period corresponding to each of the plurality of master functions, A data transfer control device comprising means for interrupting transfer when another function is requesting transfer and for starting transfer of the function requesting transfer. . 5. An expansion board for an information processing apparatus, comprising: a means connected to a bus for transferring data and inputting / outputting data; and a data bus connected to a closed local bus without the expansion board separate from the bus. A plurality of master functions capable of issuing a request for data input or output connected to the local bus and connected to the data input / output means, respectively corresponding to the plurality of master functions. Means for holding the maximum value of the transfer period that has been transferred, and interrupting the transfer during transfer when the transfer is performed beyond the maximum value of the transfer period and other functions require the transfer. An expansion board for an information processing apparatus, comprising: means for starting transfer of a requested function.