JP2000322284A - Pseudo multiple fault generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a pseudo multiple fault generator which supposes the occurrence of faults in plural unit at the same timing, foresees such occurrence and generates the pseudo fault. SOLUTION: This generator is provided with plural units (processors 10a and 10b, an input/output control processor 12, and a memory 16) which generate a pseudo fault, a maintenance and diagnosis processor 30 which performs fault processing for a unit where a fault has occurred, a fault condition setting register 28 which sets conditions of faults which would be simultaneously generated in at least two units, and a control means (an error attention control part 22, a mask register 24, and an artificial fault monitor part 26) which monitors whether a fault has occurred in units or not and reports the occurrence of a fault to the maintenance and diagnosis processor 30 only in the case that all the faults set in the fault condition setting register 28 have occurred.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo multi-fault generator, and more particularly to a pseudo multi-fault generator used for facilitating verification of a fault handling function when a fault occurs in a plurality of units at the same time.

[0002]

2. Description of the Related Art Conventionally, in order to verify a fault handling function in an information processing apparatus, an error register existing in hardware in a processor or a memory in which a fault occurs is manipulated in a pseudo manner. Had caused a failure. Hereinafter, a conventional pseudo-multiple-failure generator will be described.

FIG. 3 is a block diagram showing an example of a conventional pseudo-multiple-failure generating apparatus. In FIG. 3, 50a, 5
0b is a processor for which a fault is simulated. In the device shown in FIG. 3, the processors 50a, 50
b is duplicated. 52 is a processor 50a, 5
An input / output control processor connected to the input / output device 0b controls the input / output device 54. 56 is a processor 50a,
This is a memory for temporarily storing data processed in 50b. Reference numeral 60 denotes a diagnostic processor, and the maintenance terminal 6
Based on the diagnostic command output from the processor 2, the processor 50a, 50b, the input / output processor 52, and the error register of the memory 56 are operated. This maintenance terminal 62
Is connected to the maintenance diagnosis processor 60 by a communication line such as a telephone line.

When performing maintenance, first, a diagnostic command is issued from the maintenance terminal 62 to a processor in which a failure occurs. When the maintenance diagnosis processor 60 receives this diagnosis command, it outputs a control instruction for operating the processor to be generated via a diagnosis interface connected to the maintenance diagnosis processor 60. When this control instruction is input to the processors 50a and 50b or the input / output control processor 52, the contents of the error register of each processor are changed, and a pseudo failure occurs at the timing of receiving the diagnostic control command.

When a pseudo fault occurs, the unit in which the pseudo fault occurs issues an error attention on a diagnostic interface. When receiving the error attention, the maintenance diagnosis processor 60 starts a failure process. In this way, conventionally, a fault was artificially generated and maintenance work was performed.

[0006]

By the way, for example, assuming that a maintenance work is performed when a failure occurs at the same timing in two units of the processor 10a and the memory 56, the processor 10a and the memory 56 are simultaneously simulated. Failure must occur. in this case,
The pseudo-failure is generated by using the diagnostic control command for the processor 50a and the memory 56.
Since the diagnostic control command is manually input to each unit sequentially from the maintenance terminal 62, it is difficult to cause a pseudo failure in both units at the same timing. There has been a problem that maintenance work in the event of a failure cannot be performed assuming in advance.

The present invention has been made in view of the above circumstances. Assuming that a failure has occurred at the same timing in a plurality of units, a failure is simulated in advance in anticipation of such a case. It is an object of the present invention to provide a pseudo-multiple-failure generating device capable of performing the above-mentioned operations.

[0008]

In order to solve the above-mentioned problems, the present invention provides a plurality of units that simulate a fault, and a maintenance diagnosis unit that performs a fault process on the faulty unit. A fault condition setting means for setting a fault condition to be simultaneously generated for at least two of the units, and monitoring whether a fault has occurred in the units;
Only when all of the faults set in the fault condition setting means have occurred, control means for notifying the maintenance diagnostic means that a fault has occurred is provided.
Further, the present invention is characterized in that the control unit includes a mask unit that does not notify the maintenance diagnosis unit of the occurrence of a failure generated from the unit set by the failure condition setting unit. Further, the present invention is characterized in that a fault condition set in the fault condition setting means is set in advance from a maintenance terminal connected to the maintenance diagnosis means.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a pseudo multiple failure generating apparatus according to an embodiment of the present invention. FIG. 1 is a block diagram showing a configuration example of a pseudo multiple failure generating apparatus according to an embodiment of the present invention. In FIG. 1, reference numerals 10a and 10b denote processors for which a failure is simulated. In the device shown in FIG. 1, the processors 10a and 10b are duplicated. Reference numeral 12 denotes an input / output control processor connected to the processors 10a and 10b, and controls the input / output device 14. Reference numeral 16 denotes a memory for temporarily storing data processed by the processors 10a and 10b.

Reference numeral 20 denotes a pseudo-failure occurrence timing control circuit which controls suspension / release of error attention notification received by the maintenance diagnosis processor 30. The diagnostic processor 30 operates error registers such as the processors 50a and 50b, the input / output processor 52, and the memory 16 based on a diagnostic command output from the maintenance terminal 62. The maintenance terminal 62 is connected to the maintenance diagnosis processor 60 by a communication line such as a telephone line.
These units such as the processors 10a and 10b, the entry / exit travel control processor 12, and the memory 16 are connected to a diagnostic interface. As each of these units connected to the diagnostic interface fails, each unit reports an error attention on the diagnostic interface. When recognizing the error attention, the maintenance diagnosis processor 30 performs a failure process such as collecting failure information and recovering the failed unit.

Next, the pseudo fault occurrence timing control circuit 2
0 will be described. The fault condition setting register is 28
When an error attention condition such as an attention suspension is set from the maintenance terminal 32 connected to the maintenance diagnosis processor 30, the set value is stored. The pseudo failure monitoring unit 26 reads the contents of the failure condition setting register 28 and performs setting / monitoring / control of error attention reception according to the condition. Further, when the setting according to the contents of the fault condition setting register 28 is performed, the pseudo fault monitoring unit 26 sets the mask in the mask register 24 so as not to issue the error attention to the maintenance diagnosis processor 30 even if the corresponding error attention is notified. do. The mask register 24 controls whether or not to notify the maintenance diagnostic processor 30 by masking the error attention.

When an error attention occurs, the error attention control unit 22 suspends the error attention in response to an instruction from the pseudo failure monitoring unit 26 that monitors the error attention notification, or receives all of the set notifications. At this point, the hold is released and whether or not all error attentions are issued to the maintenance diagnosis processor 30 is controlled.

Next, the setting contents of the fault condition setting register 28 will be described. FIG. 2 shows the fault condition setting register 2
FIG. 8 is a diagram showing the contents set to 8; The fault condition setting register 28 stores the setting contents in a table format.
The contents of the table are registered in advance from the maintenance terminal 30. This table includes a faulty unit ID indicating a unit that causes a fault, an error type code for identifying the cause of the fault, and a mask setting for determining validity / invalidity of the fault.
Set for each fault that you want to generate at the same time.

Next, the operation of the pseudo-multiple-failure generating apparatus according to an embodiment of the present invention having the above configuration will be described. In order to verify fault processing by simultaneously generating faults in a plurality of units, it is necessary to determine in advance the details of faults to be generated and set them in the information processing apparatus.

The contents to be set are set for each fault in accordance with the format shown in FIG. The setting is input from the maintenance terminal 32 connected to the maintenance diagnosis processor 30 shown in FIG. When the setting content is output from the maintenance terminal 32, the setting content is stored in the fault condition setting register 28 inside the pseudo fault occurrence timing control circuit 20 via the maintenance diagnosis processor 30. Fault condition setting register 28
Are held until the next setting is performed. Also, a mask setting shown in FIG. 2 is provided so that the validity / invalidity of the set contents can be easily switched.

The simulated fault monitor 26 reads out the fault contents set in the fault condition setting register 28, and performs management such as suspending or releasing the error attention to be notified to the maintenance diagnosis processor 30 according to the contents. Here, the management is to monitor whether or not the notified error attention corresponds to the contents set in the fault condition setting register 28, and until all the set error attention contents occur. Is to suspend the notified error attention and to notify the maintenance diagnostic processor 30 of the error attention when all the error attentions have been generated.

The control of actually holding the error attention on the hardware is performed by the error attention control unit 22 in accordance with an instruction from the pseudo failure monitoring unit 26, and from the setting of the error attention until the occurrence of all the error attentions. The function of masking the error attention to the maintenance diagnosis processor 30 during the
6 is performed by the mask register 24 in accordance with the instruction from 6. The mask is set for each unit. If a failure occurs in a unit that is not set, the error attention is notified to the maintenance diagnosis processor 30.

After performing the above settings, this information processing apparatus waits for the occurrence of a pseudo failure. The method of notifying the pseudo-failure is that the error attention notification from the unit connected to the diagnostic interface is transmitted to the maintenance diagnostic processor 3.
This is performed by recognizing 0. In FIG. 1, the processors 10a and 10b, the input / output control processor 12, and the memory 16 correspond to this unit.

As an example, the processor 10a and the memory 1
It is assumed that the setting is made in such a manner that a pseudo failure is expected to occur at the same time with the setting of No. In this case, whichever of the processor 10a and the memory 16 may fail first. If a pseudo failure occurs in the memory 16 first, the error attention in the memory 16 is sent from the error attention control unit 22 to the pseudo failure monitoring unit 26 via the diagnostic interface.

When the error attention is sent, the pseudo fault monitoring unit 26 determines whether or not the fault matches the condition set in the fault condition setting register 28. In the example under consideration, since these conditions match, the pseudo failure monitoring unit 26 determines that the conditions match, and issues a hold instruction to the error attention control unit 2.
2 and the error attention is suspended.

The memory 16 is stored in the mask register 24.
Is set so as not to notify the maintenance diagnostic processor 30 of the error attention of the user, and is not notified at this time. Next, when a pseudo fault occurs in the processor 10a, the error attention of the processor 10a is sent from the error attention control unit 22 to the pseudo fault monitoring unit 2.
Sent to 6. The pseudo fault monitoring unit 26 determines that the fault matches the condition set in the fault condition setting register 28, further determines that all the set conditions have been generated, and suspends the error attention control unit 22. By canceling all the error attentions that have been performed and clearing all the mask conditions set in the mask register 24, all the held error attentions are simultaneously notified to the maintenance diagnosis processor 30.

As described above, in the present embodiment, the timing of reporting error attentions from a plurality of units to the maintenance diagnosis processor is collectively managed by masking the error attention at the time of failure and controlling the hold or release of the hold. As a result, it is possible to control multiple units as if they had occurred at the same timing, and as a result, it is possible to verify the failure diagnosis function of the maintenance diagnostic processor and the failed unit when multiple failures occur This has the effect.

[0023]

As described above, according to the present invention, the timing at which error attentions from a plurality of units are reported to the maintenance diagnosis means is collectively managed, so that a failure of a plurality of units occurs at the same timing. As a result, it is possible to verify the fault handling function of the maintenance diagnosis unit when a plurality of faults occur.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a pseudo multiple failure generating apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing contents set in a fault condition setting register 28;

FIG. 3 is a block diagram illustrating an example of a conventional pseudo-multiple-failure generating apparatus.

[Explanation of symbols]

10a, 10b Processor (unit) 12 Input / output control processor (unit) 16 Memory (unit) 22 Error attention control unit (control unit) 24 Mask register (mask unit, control unit) 26 Pseudo failure monitoring unit (control unit) 28 Failure Condition setting register (fault condition setting means) 30 Maintenance diagnosis processor (maintenance diagnosis means) 32 Maintenance terminal

Claims (3)

[Claims] 1. A plurality of units that simulate a failure, a maintenance diagnosis unit that performs a failure process on the failed unit, and a condition of a failure that occurs simultaneously on at least two of the units. Fault condition setting means to be set, monitoring whether or not a fault has occurred in the unit, and only when all faults set in the fault condition setting means have occurred,
Control means for notifying the maintenance diagnosis means that a failure has occurred. 2. The pseudo-controller according to claim 1, wherein the control unit includes a mask unit that does not notify the maintenance diagnosis unit of the occurrence of a failure that has occurred from the unit set by the failure condition setting unit. Multiple failure generator. 3. The pseudo multiple fault according to claim 1, wherein the fault condition set in the fault condition setting means is set in advance from a maintenance terminal connected to the maintenance diagnosis means. Generator.