JP2000315819A - Manufacture of semiconductor light emitting element - Google Patents
Manufacture of semiconductor light emitting elementInfo
- Publication number
- JP2000315819A JP2000315819A JP12440999A JP12440999A JP2000315819A JP 2000315819 A JP2000315819 A JP 2000315819A JP 12440999 A JP12440999 A JP 12440999A JP 12440999 A JP12440999 A JP 12440999A JP 2000315819 A JP2000315819 A JP 2000315819A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- transparent electrode
- film
- layer
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はウェハ状の基板上
に、ｐ形層およびｎ形層を含む半導体層を積層した後
に、ｐ形層およびｎ形層にそれぞれパッド電極を形成す
る半導体発光素子の製法に関する。さらに詳しくは、パ
ッド電極の形成時に光の取出し面を汚すことなく、ま
た、ワイヤボンディング時などに剥れなどが生じにくい
ような厚いパッド電極を形成することができる半導体発
光素子の製法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device in which a semiconductor layer including a p-type layer and an n-type layer is laminated on a wafer-like substrate, and then pad electrodes are formed on the p-type layer and the n-type layer, respectively. Related to the production method. More specifically, the present invention relates to a method for manufacturing a semiconductor light emitting element capable of forming a thick pad electrode without polluting a light extraction surface at the time of forming the pad electrode and preventing peeling during wire bonding or the like.
【０００２】[0002]
【従来の技術】従来、青色系の光を発光する半導体発光
素子のチップ（以下、ＬＥＤチップという）の製法は、
つぎのように行われる。すなわち、図４に示されるよう
に、サファイア基板２１上にたとえばｎ形のＧａＮから
なるｎ形層（クラッド層）２３と、バンドギャップエネ
ルギーがクラッド層のそれよりも小さく発光波長を定め
る材料、たとえばＩｎＧａＮ系（ＩｎとＧａの比率が種
々変わり得ることを意味する、以下同じ）化合物半導体
からなる活性層（発光層）２４と、ｐ形のＧａＮからな
るｐ形層（クラッド層）２５とを順次エピタキシャル成
長し、その表面にＩＴＯなどからなる透明電極２６を介
してｐ側パッド電極２８を設け、積層された半導体層の
一部をエッチングして露出するｎ形層２３の表面にｎ側
パッド電極２９を設ける。そして、電極２８、２９が露
出するように、たとえばＳｉＯ2 などのパシベーション
膜２７を表面に設けてからダイシングをしてチップ化す
る。2. Description of the Related Art Conventionally, a semiconductor light emitting element chip (hereinafter, referred to as an LED chip) that emits blue light is manufactured by the following method.
It is performed as follows. That is, as shown in FIG. 4, an n-type layer (cladding layer) 23 made of, for example, n-type GaN on a sapphire substrate 21 and a material whose band gap energy is smaller than that of the cladding layer and determines the emission wavelength, for example, An active layer (light-emitting layer) 24 made of an InGaN-based (which means that the ratio of In to Ga can be variously changed, the same applies hereinafter) compound semiconductor and a p-type layer (cladding layer) 25 made of p-type GaN are sequentially formed. After epitaxial growth, a p-side pad electrode 28 is provided on the surface of the n-type layer 23 via a transparent electrode 26 made of ITO or the like, and a part of the stacked semiconductor layer is etched and exposed. Is provided. Then, a passivation film 27 of, for example, SiO 2 is provided on the surface so that the electrodes 28 and 29 are exposed, and then dicing is performed to form a chip.
【０００３】[0003]
【発明が解決しようとする課題】前述のように、両パッ
ド電極を設けた後に、そのパッド電極が露出するように
ＬＥＤチップの表面の全面にパシベーション膜が設けら
れている。このように最終的にパシベーション膜が設け
られることにより、ＬＥＤチップ表面のほぼ全面をパシ
ベーション膜により被覆するため、その後の取扱などに
より表面を汚すことなく発光ランプなどに組み込まれる
ため好ましい。As described above, after both pad electrodes are provided, a passivation film is provided on the entire surface of the LED chip so that the pad electrodes are exposed. Since the passivation film is finally provided, almost the entire surface of the LED chip is covered with the passivation film, and the LED chip is incorporated into a light-emitting lamp or the like without being stained by subsequent handling.
【０００４】しかし、パッド電極を形成する際、リフト
オフ法によるためレジスト膜を塗布したり、レジスト膜
を剥離する処理が必要となる。この際、ＩＴＯまたはＮ
ｉ-Ａｕ合金、Ｃｏ-Ａｕ合金などの薄膜金属などからな
る透明電極の表面に異物が付着しやすく、透明電極の表
面が汚れると透明電極を透過する光を減衰させ、発光効
率を低下させるという問題がある。とくに、ｐ側パッド
電極を形成する場合、ＩＴＯなどの透明電極上に形成す
るため、パターニングをすることができず、リフトオフ
法などにより形成しなければならず、汚れが顕著とな
る。さらに、汚れた表面にそのままＳｉＯ2 などの保護
膜を設けると、保護膜のクラックや剥れなどが生じやす
いという問題もある。However, when the pad electrode is formed, since a lift-off method is used, a process of applying a resist film or removing the resist film is required. At this time, ITO or N
It is said that foreign matter easily adheres to the surface of a transparent electrode made of a thin film metal such as an i-Au alloy or a Co-Au alloy. If the surface of the transparent electrode becomes dirty, light passing through the transparent electrode is attenuated, thereby lowering luminous efficiency. There's a problem. In particular, when the p-side pad electrode is formed, since it is formed on a transparent electrode such as ITO, patterning cannot be performed, and the p-side pad electrode must be formed by a lift-off method or the like. Furthermore, if a protective film such as SiO 2 is provided on a dirty surface as it is, there is a problem that cracks and peeling of the protective film are likely to occur.
【０００５】また、従来はパッド電極もスパッタリング
または真空蒸着法により設けられているため、厚く形成
することが困難で、１μｍ程度の厚さに形成されてい
る。そのため、ワイヤボンディングなどの際に力が加わ
ると、パッド電極の接着面などにクラックが入ったりし
てパッド電極の剥れなどが生じるという問題がある。Conventionally, pad electrodes are also provided by sputtering or vacuum evaporation, so that it is difficult to form them thickly, and they are formed to a thickness of about 1 μm. Therefore, when a force is applied during wire bonding or the like, there is a problem that cracks may be formed on the bonding surface of the pad electrode or the like, and the pad electrode may peel off.
【０００６】本発明はこのような問題を解決するために
なされたもので、ｐ側パッド電極を形成する際にレジス
ト膜などにより透明電極が汚れないようにパッド電極を
形成することができる半導体発光素子の製法を提供する
ことにある。The present invention has been made in order to solve such a problem, and a semiconductor light emitting device capable of forming a pad electrode such that a transparent electrode is not stained by a resist film when forming a p-side pad electrode. An object of the present invention is to provide a method for manufacturing an element.
【０００７】本発明の他の目的は、パッド電極を簡単な
方法で厚く形成し、ワイヤボンディングなどの信頼性を
向上することができる半導体発光素子の製法を提供する
ことにある。Another object of the present invention is to provide a method of manufacturing a semiconductor light emitting device in which a pad electrode can be formed thick by a simple method to improve reliability such as wire bonding.
【０００８】[0008]
【課題を解決するための手段】本発明による半導体発光
素子の製法は、（ａ）ウェハ状の基板上に第１導電形半
導体層および第２導電形半導体層を含み発光層を形成す
る半導体層を積層し、（ｂ）前記積層される半導体層の
表面側の第２導電形半導体層上に透明電極を形成すると
共に、前記積層される半導体層の一部を除去して露出す
る第１導電形半導体層上に第１の電極用金属膜を設け、
（ｃ）前記透明電極および第１の電極用金属膜が設けら
れたウェハの表面にパシベーション膜を設け、（ｄ）該
パシベーション膜の前記第１の電極用金属膜の部分およ
び前記透明電極上のパッド電極の形成場所を開口し、
（ｅ）前記開口されて露出する第１の電極用金属膜の部
分および透明電極上にそれぞれパッド電極を形成するこ
とを特徴とする。According to the present invention, there is provided a method for manufacturing a semiconductor light emitting device, comprising the steps of: (a) forming a light emitting layer including a first conductive type semiconductor layer and a second conductive type semiconductor layer on a wafer-like substrate; And (b) forming a transparent electrode on the second conductivity type semiconductor layer on the surface side of the semiconductor layer to be stacked, and removing a part of the stacked semiconductor layer to expose the first conductive layer. Providing a first metal film for an electrode on the semiconductor layer,
(C) providing a passivation film on the surface of the wafer on which the transparent electrode and the first electrode metal film are provided; and (d) providing a portion of the passivation film on the first electrode metal film and on the transparent electrode. Open the pad electrode formation location,
(E) A pad electrode is formed on each of the portion of the first electrode metal film that is opened and exposed and the transparent electrode.
【０００９】ここにパッド電極とは、ワイヤボンディン
グをしたり、直接またはバンプなどを介してリードなど
の電極端子と接続する電極部分を意味する。Here, the pad electrode means an electrode portion connected to an electrode terminal such as a lead by wire bonding or directly or via a bump or the like.
【００１０】この方法で行うことにより、透明電極上に
設けるパッド電極を、透明電極上にパシベーション膜が
設けられた状態で形成することができるため、透明電極
を汚すことなく形成することができる。しかも、清浄な
透明電極上にパシベーション膜が設けられているため、
その密着力もよく、パシベーション膜の信頼性も向上す
る。According to this method, the pad electrode provided on the transparent electrode can be formed in a state where the passivation film is provided on the transparent electrode, so that the transparent electrode can be formed without being stained. Moreover, since the passivation film is provided on the clean transparent electrode,
The adhesion is good, and the reliability of the passivation film is also improved.
【００１１】前記（ｅ）工程で、ウェハを電気メッキ液
に浸漬し、電気メッキ液と前記積層された半導体層との
間に電圧を印加することにより、前記パッド電極を電気
メッキ法により形成すれば、パシベーション膜から露出
する部分のみに金属膜が堆積され、材料の無駄がなく、
効率よくパッド電極を厚く形成することができる。その
結果、ワイヤボンディングなどの信頼性が非常に向上す
る。In the step (e), the pad electrode is formed by electroplating by immersing the wafer in an electroplating solution and applying a voltage between the electroplating solution and the stacked semiconductor layers. For example, the metal film is deposited only on the portion exposed from the passivation film,
A thick pad electrode can be formed efficiently. As a result, reliability such as wire bonding is greatly improved.
【００１２】前記第１の電極をＴｉ-Ａｌ合金とＴｉ／
Ａｕ積層体との積層により形成することにより、Ｔｉ-
Ａｌ合金層の表面の酸化防止という利点がある。The first electrode is made of a Ti—Al alloy and Ti /
By forming by lamination with the Au laminated body, Ti-
There is an advantage that oxidation of the surface of the Al alloy layer is prevented.
【００１３】[0013]
【発明の実施の形態】つぎに、図面を参照しながら本発
明の半導体発光素子の製法について説明をする。図１に
は、青色系の発光に適したチッ化ガリウム系化合物半導
体層をウェハ状のサファイア基板上に積層し、電極を設
ける製造工程が１チップ分で示されている。ここにチッ
化ガリウム系化合物半導体とは、III 族元素のＧａとＶ
族元素のＮとの化合物またはIII 族元素のＧａの一部ま
たは全部がＡｌ、Ｉｎなどの他のIII 族元素と置換した
ものおよび／またはＶ族元素のＮの一部がＰ、Ａｓなど
の他のＶ族元素と置換した化合物からなる半導体をい
う。Next, a method for manufacturing a semiconductor light emitting device of the present invention will be described with reference to the drawings. FIG. 1 shows a manufacturing process for one chip in which a gallium nitride compound semiconductor layer suitable for blue light emission is laminated on a wafer-like sapphire substrate and electrodes are provided. Here, the gallium nitride-based compound semiconductor refers to a group III element Ga and V
A compound of group III element with N or a part or whole of Ga of group III element substituted with another group III element such as Al and In and / or a part of N of group V element such as P, As, etc. A semiconductor made of a compound substituted with another group V element.
【００１４】まず、図１（ａ）に示されるように、ウェ
ハ状の基板１上に第１導電形半導体層（ｎ形層３）およ
び第２導電形半導体層（ｐ形層５）を含み発光層を形成
する半導体層を積層する。そして、積層される半導体層
の表面側のｐ形層５上にＩＴＯまたはＮｉ-Ａｕ合金、
Ｃｏ-Ａｕ合金などの薄膜金属などからなる透明電極６
を形成すると共に、積層される半導体層の一部を除去し
て露出するｎ形層３上に第１の電極用金属膜（ｎ側電
極）９ａを設ける。First, as shown in FIG. 1A, a first conductive type semiconductor layer (n-type layer 3) and a second conductive type semiconductor layer (p-type layer 5) are included on a wafer-like substrate 1. A semiconductor layer for forming a light emitting layer is stacked. And, on the p-type layer 5 on the surface side of the semiconductor layer to be laminated, ITO or Ni-Au alloy,
Transparent electrode 6 made of thin film metal such as Co-Au alloy
And a first metal film for an electrode (n-side electrode) 9a is provided on the n-type layer 3 exposed by removing a part of the semiconductor layer to be laminated.
【００１５】具体的に説明すると、半導体層を積層する
ため、たとえば有機金属化学気相成長法（ＭＯＣＶＤ
法）により反応ガスおよび必要なドーパントガスを導入
して、サファイア（Ａｌ2 Ｏ3 単結晶）などからなる基
板１の表面に図示しないＧａＮからなる低温バッファ層
と、クラッド層となるｎ形のＧａＮおよび／またはＡｌ
ＧａＮ系（ＡｌとＧａの比率が種々変わり得ることを意
味する、以下同じ）の積層構造からなるｎ形層３を１〜
５μｍ程度堆積し、さらに、バンドギャップエネルギー
がクラッド層のそれよりも小さくなる材料、たとえばＩ
ｎＧａＮ系化合物半導体層からなる活性層４を０.００
２〜０.３μｍ程度、ｐ形のＡｌＧａＮ系化合物半導体
層および／またはＧａＮ層からなるｐ形層（クラッド
層）５を０.０２〜０.５μｍ程度、それぞれ順次積層す
る。なお、積層後にｐ形層５の活性化のため、アニール
処理を行うこともある。ついで、その表面に、たとえば
Ｎｉ-Ａｕ膜またはＣｏ-Ａｕ膜またはＩＴＯ膜を０.０
１〜０.０５μｍ程度成膜し、エッチングまたはリフト
オフ法により透明電極６を形成する。More specifically, for stacking semiconductor layers, for example, metal organic chemical vapor deposition (MOCVD) is used.
), A low-temperature buffer layer (not shown) made of GaN (not shown) and an n-type GaN (cladding layer) are formed on the surface of a substrate 1 made of sapphire (Al 2 O 3 single crystal) or the like. And / or Al
The n-type layer 3 having a GaN-based (meaning that the ratio of Al to Ga can be varied in various ways, the same applies hereinafter) a 1 to
A material having a band gap energy smaller than that of the cladding layer, for example, I
The active layer 4 made of an nGaN-based compound semiconductor layer is
A p-type layer (cladding layer) 5 composed of a p-type AlGaN-based compound semiconductor layer and / or a GaN layer having a thickness of about 2 to 0.3 μm is sequentially laminated to a thickness of about 0.02 to 0.5 μm. Note that annealing may be performed after the lamination to activate the p-type layer 5. Then, a Ni—Au film, a Co—Au film, or an ITO film, for example, is formed on the surface at a thickness of 0.0.
A film having a thickness of about 1 to 0.05 μm is formed, and a transparent electrode 6 is formed by etching or a lift-off method.
【００１６】ついで、ｎ側電極用金属膜（ｎ側電極）９
ａを形成するため、積層される半導体層の一部を除去し
てｎ形層３を露出させる。すなわち、積層された半導体
層の表面にレジスト膜などを設けてパターニングをし、
積層された半導体層３〜５の一部をエッチングしてｎ形
層３を露出させる。この際、各チップに分割する境界部
の近傍の半導体層もエッチングすることがあるが、エッ
チングしなくてもよい。そして、図２にパシベーション
膜を省略した状態の１チップの平面説明図が示されるよ
うに、ｎ形層３を露出させる。このエッチングは、塩素
ガスなどによる反応性イオンエッチングにより行うこと
ができ、ＳｉＯ2 、ＳｉＮ、Ｔｉ、Ｎｉなどをマスクと
して用いることにより、エッチングをすることができ
る。そして、ｎ形層３の露出面に、ＴｉおよびＡｌをそ
れぞれ０.１μｍ程度と０.３μｍ程度づつ真空蒸着など
により成膜してシンターすることにより合金化してｎ側
電極９ａを形成する。この電極９ａの形状は、リフトオ
フ法または全面に成膜してからパターニングする方法に
より、形成される。この合金からなる電極により、優れ
たオーミックコンタクトが得られるが、さらにこの上に
Ｔｉ／Ａｕの積層膜をそれぞれ０.１μｍ程度と０.４μ
ｍ程度づつ真空蒸着などにより成膜することが、電極表
面の酸化防止のため好ましい。Next, a metal film for an n-side electrode (n-side electrode) 9
To form a, a part of the semiconductor layer to be laminated is removed to expose the n-type layer 3. That is, a resist film or the like is provided on the surface of the stacked semiconductor layers and patterned,
The n-type layer 3 is exposed by etching a part of the stacked semiconductor layers 3 to 5. At this time, the semiconductor layer near the boundary portion to be divided into each chip may be etched, but may not be etched. Then, the n-type layer 3 is exposed as shown in a plan view of one chip in a state where the passivation film is omitted in FIG. This etching can be performed by reactive ion etching using a chlorine gas or the like, and can be performed by using SiO 2 , SiN, Ti, Ni, or the like as a mask. Then, on the exposed surface of the n-type layer 3, Ti and Al are formed by vacuum evaporation or the like by about 0.1 μm and about 0.3 μm, respectively, and are alloyed by sintering to form the n-side electrode 9a. The shape of the electrode 9a is formed by a lift-off method or a method of patterning after forming a film on the entire surface. An excellent ohmic contact can be obtained by the electrode made of this alloy, and a Ti / Au laminated film is further formed thereon by about 0.1 μm and 0.4 μm, respectively.
It is preferable to form a film by vacuum evaporation every m steps to prevent oxidation of the electrode surface.
【００１７】つぎに、図１（ｂ）に示されるように、透
明電極６およびｎ側電極９ａが設けられたウェハの表面
に、ＳｉＯ2 などからなるパシベーション膜７を設け
る。具体的には、たとえばＣＶＤ法により、ウェハ表面
の全面にＳｉＯ2 膜を０.５μｍ程度の厚さに成膜す
る。Next, as shown in FIG. 1B, a passivation film 7 made of SiO 2 or the like is provided on the surface of the wafer provided with the transparent electrode 6 and the n-side electrode 9a. Specifically, an SiO 2 film is formed to a thickness of about 0.5 μm over the entire surface of the wafer by, for example, a CVD method.
【００１８】つぎに、図１（ｃ）に示されるように、パ
シベーション膜７のｎ側電極９ａの部分および透明電極
６上のパッド電極の形成場所を開口し、開口部７ａ、７
ｂを形成する。この開口部７ａ、７ｂは、半導体装置の
製造工程のコンタクト孔を開口するのと同様に、開口す
る部分のみを除いたレジスト膜（図示せず）などのマス
クを形成して、反応性イオンエッチング（ＲＩＥ）法に
より、またはフッ酸によるウェットエッチング法により
パシベーション膜７をエッチングすることにより形成さ
れ、透明電極６およびｎ側電極９ａが部分的に露出す
る。Next, as shown in FIG. 1C, the portion of the passivation film 7 where the n-side electrode 9a is formed and the place where the pad electrode is formed on the transparent electrode 6 are opened.
b is formed. The openings 7a and 7b are formed by forming a mask such as a resist film (not shown) excluding only the opening in the same manner as the opening of the contact hole in the manufacturing process of the semiconductor device, and by reactive ion etching. The transparent electrode 6 and the n-side electrode 9a are partially exposed by etching the passivation film 7 by an (RIE) method or a wet etching method using hydrofluoric acid.
【００１９】つぎに、図１（ｄ）に示されるように、た
とえば電解メッキ法により、パシベーション膜７の開口
部７ｂ、７ａから露出する透明電極６およびｎ側電極９
ａの上に、Ａｕを成膜してｐ側およびｎ側のパッド電極
８、９をそれぞれ形成する。このパッド電極８、９は、
それぞれ１〜７.５μｍ程度の厚さ、さらに好ましくは
３〜５μｍ程度、たとえば３μｍ程度の厚さに形成され
る。従来の厚さに比べると３倍程度の厚さになるが、真
空蒸着法などのように余計なところには付着しないで必
要な場所のみに析出するため、短時間で効率よくパッド
電極８、９を形成することができる。Next, as shown in FIG. 1D, the transparent electrode 6 and the n-side electrode 9 exposed from the openings 7b and 7a of the passivation film 7 by, for example, electrolytic plating.
A film of Au is formed on “a” to form p-side and n-side pad electrodes 8 and 9, respectively. These pad electrodes 8 and 9 are
Each is formed to a thickness of about 1 to 7.5 μm, more preferably about 3 to 5 μm, for example, about 3 μm. Although it is about three times thicker than the conventional thickness, it is deposited only at a necessary place without adhering to unnecessary places such as a vacuum evaporation method, so that the pad electrode 8 can be efficiently formed in a short time. 9 can be formed.
【００２０】電気メッキ法により電極を形成するには、
図３にメッキ液に浸漬した説明図および半導体ウェハの
一部の断面説明図が示されるように、ウェハ１３の端部
のｎ形層３にオーミック接触させた電極１４を形成して
おき、その部分にリード１５を接続してメッキ液１６中
に浸漬してリード１５を負電極１７と接続し、正の電極
１８との間に電流を流すことにより、パシベーション膜
７から露出した透明電極６およびｎ側電極９ａ上にＡｕ
を析出させることができる。この場合、ｐ形層５は各チ
ップごとに分離されているが、ｎ形層３から積層された
半導体層を介してメッキ用の電流が流れる。なお、図３
で１３ａは各チップを指す。In order to form electrodes by electroplating,
As shown in FIG. 3 showing an explanatory view immersed in a plating solution and a partial explanatory view of a semiconductor wafer, an electrode 14 is formed in ohmic contact with the n-type layer 3 at the end of the wafer 13. A lead 15 is connected to the portion, and the lead 15 is immersed in a plating solution 16 to connect the lead 15 to the negative electrode 17 and a current flows between the positive electrode 18 and the transparent electrode 6 exposed from the passivation film 7. Au is placed on the n-side electrode 9a.
Can be precipitated. In this case, the p-type layer 5 is separated for each chip, but a plating current flows from the n-type layer 3 through the stacked semiconductor layers. Note that FIG.
And 13a indicates each chip.
【００２１】この例では、パッド電極８、９を電気メッ
キ法により設けたが、電気メッキ法によれば短時間で厚
く電極膜を形成することができると共に、無駄なところ
には金属が付着しないで効率的に設けることができる。
しかし、真空蒸着法やスパッタリング法などの他の方法
で設けても、時間は掛かるものの、ｐ側パッド電極８を
形成する部分以外の透明電極６はパシベーション膜によ
り被覆されているため、透明電極上の汚れの問題は発生
せず、発光効率を向上させることができる。In this example, the pad electrodes 8 and 9 are provided by the electroplating method. However, according to the electroplating method, a thick electrode film can be formed in a short time, and metal does not adhere to useless places. Can be provided efficiently.
However, even if it is provided by another method such as a vacuum deposition method or a sputtering method, although it takes time, since the transparent electrode 6 other than the portion where the p-side pad electrode 8 is formed is covered with the passivation film, The problem of contamination does not occur, and the luminous efficiency can be improved.
【００２２】さらに、前述の例では、透明電極を設けて
から、ｎ側電極を設けるためのエッチングおよびｎ側電
極の形成を行ったが、ｎ側電極を設けた後に透明電極を
形成し、その上にパシベーション膜を設けてもよく、順
序は別に問わない。Further, in the above-described example, the etching for forming the n-side electrode and the formation of the n-side electrode were performed after the provision of the transparent electrode, but the transparent electrode was formed after the formation of the n-side electrode. A passivation film may be provided thereon, and the order does not matter.
【００２３】チッ化ガリウム系化合物半導体を用いた半
導体発光素子では、とくに透明電極上の一部にパッド電
極を形成する際に、透明電極が汚れて透過する光が低下
し、外部微分量子効率が低下しやすいという問題がある
が、本発明によれば、パッド電極を形成する前に透明電
極の表面にパシベーション膜が形成されているため、全
然汚れの問題がなく、しかもパシベーション膜の異物に
よる剥れや割れなどの発生がなくなり、信頼性が大幅に
向上する。In a semiconductor light emitting device using a gallium nitride-based compound semiconductor, particularly when a pad electrode is formed on a part of the transparent electrode, the transparent electrode is contaminated, the transmitted light is reduced, and the external differential quantum efficiency is reduced. According to the present invention, since the passivation film is formed on the surface of the transparent electrode before the pad electrode is formed, there is no problem of contamination at all, and the passivation film is peeled off by foreign matter. The occurrence of cracks and cracks is eliminated, and the reliability is greatly improved.
【００２４】さらに、パッド電極を電気メッキ法により
形成することにより、短時間で材料の無駄なく厚く形成
することができる。その結果、パッド電極などの衝撃が
加わりやすい電極でもその強度が向上し、ボンディング
の信頼性が非常に向上する。また、従来ワイヤボンディ
ングなどの衝撃に耐えやすくするため、Ａｕの下にＴｉ
などを成膜していたが、本発明によれば、充分に厚く形
成することができるため、Ｔｉなどの固い金属を途中に
介在させる必要がなく、金属膜の形成工程を簡略化する
こともできる。Further, by forming the pad electrode by the electroplating method, the pad electrode can be formed thick in a short time without wasting material. As a result, the strength of an electrode, such as a pad electrode, to which an impact is likely to be applied is improved, and bonding reliability is greatly improved. In addition, in order to easily withstand the impact of conventional wire bonding and the like, Ti
However, according to the present invention, the metal film can be formed sufficiently thick, so that it is not necessary to interpose a hard metal such as Ti in the middle, and the process of forming the metal film can be simplified. it can.
【００２５】[0025]
【発明の効果】本発明によれば、透明電極の汚れを抑制
することができるため、外部微分量子効率が向上すると
共に、パシベーション膜の被膜の信頼性が大幅に向上す
る。さらに、電気メッキ法によりパッド電極を形成する
ことにより、材料の無駄がなく短時間で厚いパッド電極
を形成することができるため、コストの削減を図ること
ができると共に、ワイヤボンディング時の歩留り向上お
よび信頼性の向上を図ることができる。According to the present invention, since the contamination of the transparent electrode can be suppressed, the external differential quantum efficiency is improved and the reliability of the passivation film is greatly improved. Further, by forming the pad electrode by the electroplating method, a thick pad electrode can be formed in a short time without wasting the material, so that the cost can be reduced, and the yield at the time of wire bonding can be improved. Reliability can be improved.
【図１】本発明の製法の一実施形態の工程断面説明図で
ある。FIG. 1 is a process sectional explanatory view of one embodiment of a production method of the present invention.
【図２】図１の発光素子チップを上から見た平面説明図
である。FIG. 2 is an explanatory plan view of the light emitting element chip of FIG. 1 as viewed from above.
【図３】電気メッキをするときのメッキ液への浸漬およ
びウェハの一部の断面説明図である。FIG. 3 is an explanatory cross-sectional view of a part of a wafer immersed in a plating solution when performing electroplating.
【図４】従来の半導体発光素子の製法を説明する断面説
明図である。FIG. 4 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor light emitting device.
１ 基板 ３ ｎ形層 ５ ｐ形層 ６ 透明電極 ７ パシベーション膜 ８ ｐ側パッド電極 ９ ｎ側パッド電極 Reference Signs List 1 substrate 3 n-type layer 5 p-type layer 6 transparent electrode 7 passivation film 8 p-side pad electrode 9 n-side pad electrode
Claims (3)
導体層および第２導電形半導体層を含み発光層を形成す
る半導体層を積層し、（ｂ）前記積層される半導体層の
表面側の第２導電形半導体層上に透明電極を形成すると
共に、前記積層される半導体層の一部を除去して露出す
る第１導電形半導体層上に第１の電極用金属膜を設け、
（ｃ）前記透明電極および第１の電極用金属膜が設けら
れたウェハの表面にパシベーション膜を設け、（ｄ）該
パシベーション膜の前記第１の電極用金属膜の部分およ
び前記透明電極上のパッド電極の形成場所を開口し、
（ｅ）前記開口されて露出する第１の電極用金属膜の部
分および透明電極上にそれぞれパッド電極を形成するこ
とを特徴とする半導体発光素子の製法。(A) laminating a semiconductor layer including a first conductive type semiconductor layer and a second conductive type semiconductor layer to form a light emitting layer on a wafer-shaped substrate; A transparent electrode is formed on the second conductive type semiconductor layer on the front side, and a first electrode metal film is provided on the first conductive type semiconductor layer which is exposed by removing a part of the stacked semiconductor layers. ,
(C) providing a passivation film on the surface of the wafer on which the transparent electrode and the first electrode metal film are provided; and (d) providing a portion of the passivation film on the first electrode metal film and on the transparent electrode. Open the pad electrode formation location,
(E) A method of manufacturing a semiconductor light emitting device, wherein a pad electrode is formed on each of the portion of the first electrode metal film that is opened and exposed and the transparent electrode.
液に浸漬し、電気メッキ液と前記積層された半導体層と
の間に電圧を印加することにより、前記パッド電極を電
気メッキ法により形成する請求項１記載の製法。2. In the step (e), the wafer is immersed in an electroplating solution, and a voltage is applied between the electroplating solution and the stacked semiconductor layers, so that the pad electrodes are formed by electroplating. 2. The method according to claim 1, wherein said method is formed.
／Ａｕ積層体との積層により形成する請求項１または２
記載の製法。3. The first electrode is made of a Ti—Al alloy and Ti
3. The method according to claim 1, wherein the first and second layers are formed by laminating with a Au laminate.
The manufacturing method described.
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| JP12440999A JP3881473B2 (en) | 1999-04-30 | 1999-04-30 | Manufacturing method of semiconductor light emitting device |
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