JP2000307643A - Device and method for analyzing data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute packet analysis in real time by simple constitution by writing positional information of matching data in a packet when data of the packet stored in a second storing means match the bit pattern of a prescribed parameter. SOLUTION: This device is provided with a pattern collating means which collates data of a packet stored in a second storing means with the bit pattern of a prescribed parameter and which writes the positional information of matching data when they match. In this device, the searching part 60 of a data analyzing part 20 searches the pay load of a TS block stored in a TS[] memory 32 by using a previously stored search pattern in accordance with a search command by an operation program to execute pattern matching. Then, in the case of detecting a bit string being matched with the search pattern, the end address of the bit string is written in the local header of the TS block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data analysis device and a data analysis method, and is suitable for application to, for example, a data analysis device for analyzing packetized data to obtain data written in the packet. .

[0002]

2. Description of the Related Art Conventionally, MPEG (Moving Picture Experts) has been used as a method for reducing the amount of information of video and accompanying audio.
Group) 2 system is used. In the MPEG2 system, a PES packet is generated by packetizing an elementary stream obtained by compressing and encoding video data. At the head of the PES packet, a PES header in which various kinds of information in the encoding process are written is added.

This PES packet has a payload of 1
It is divided every 84 [bytes], and by adding a 4 [byte] TS header to the beginning of the data, 188 [b] as a whole is obtained.
yte], TS (Transport Strea
m) Generate a packet.

In the MPEG2 system, TS packets of a plurality of programs (elementary streams) are time-division multiplexed to generate a transport stream, and by broadcasting this, a plurality of programs can be broadcast on one line. ing. The TS header contains a PID (Packet Ide
ntification), so that a desired program can be separated from the multiplexed transport stream.

[0005]

By the way, a multiplexed transport stream is received by a relay station, and for example, advertising video data (so-called CM) is added to video data of a predetermined program in the transport stream. It is conceivable to insert the local weather forecast into the weather forecast portion in the news program.

[0006] In order to perform such processing, first video data and second video data are switched and connected to generate final video data. Such a video editing operation is called a splicing process.

If the first and second video data are baseband video data that have not been compression-encoded, the splicing process can be easily performed by synchronizing and switching the frame timing between the first and second video data. It can be performed.

[0008] However, when the first and second video data are compression-encoded, the generated code amount differs for each picture, so that the splicing process cannot be performed simply by switching the data. Therefore, it is necessary to analyze a TS packet to be spliced, read out a parameter such as a generated code amount written in the PES packet, and perform a splicing process based on the parameter.

As a method for reading such parameters,
A method of extracting a payload from a TS packet to reproduce a PES packet and obtaining a parameter using the PES packet can be considered. However, in this case, it takes time to reproduce the PES packet and it is difficult to perform analysis in real time. Have.

The present invention has been made in view of the above points, and it is an object of the present invention to propose a data analysis device and a data analysis method capable of performing real-time packet analysis with a simple configuration.

[0011]

In order to solve the above-mentioned problems, according to the present invention, a transport stream composed of a series of predetermined packets is analyzed, and codes which are divided and assigned to payloads of the respective packets. In a data analysis device for obtaining parameters written in coded data, a first storage means for storing a transport stream, a second storage means for storing one packet, and a packet including predetermined data to be read are stored. Read from the first storage means and stored in the second storage means,
Control means for a storage means for reading and outputting the data to be read from the second storage means; calculating means for calculating the data to be read to obtain a parameter; data for the packet stored in the second storage means; Pattern matching means for comparing the bit pattern of the packet with the bit pattern of the parameter, and when the data of the packet matches the bit pattern, writing the position information of the matched data in the packet.

Since the means for collating the bit pattern is provided separately from the arithmetic means, the parameter can be extracted at a high speed.

The data at the end of the packet stored in the second storage means is stored in the pattern matching means, and the bit pattern of the packet next to the packet stored in the second storage means is checked. Sometimes, the last data is added to the beginning of the next packet to check the bit pattern.

By storing the data at the end and adding it to the head of the next packet and collating the bit pattern, a bit pattern over two packets can be detected.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) Overall Configuration of Splicing Device In FIG. 1, reference numeral 1 denotes a splicing device as a whole, and an input processing unit 3, a data processing unit 4, an output processing unit 5, and a CPU (Central Processing Unit) as position information adding means.
nit) 6, data bus 7, command bus 8, SDRAM
(Synchronous Dynamic Random Access Memory) as an external memory 9, an interface unit 10, and a data analysis unit 20 as first storage means.

The splicing apparatus 1 performs splicing processing on transport streams S1 and S2 obtained by multiplexing a plurality of video data based on control information supplied from a host computer 2, and outputs an output transport stream Sout. Is generated and output to the outside.

The CPU 6 is provided with a RISC (Reduced Instructio).
n Set Computer: A microprocessor having a reduced instruction set computer configuration, and controls each circuit block (input processing unit 3, data processing unit 4, output processing unit 5, external memory 9, and data analysis unit 20) of the splicing device. Is what you do. That is, the CPU 7 receives the splicing command supplied from the host computer 2 via the interface unit 10 and the command bus 8, and based on the splicing command, the splicing device 1
By generating an operation instruction for each of the circuit blocks and supplying the operation instruction to each of the circuit blocks, a splicing process instructed by the host computer 2 is executed. The CPU 6 operates based on an operation program stored in the external memory 9 to control the operation of each of these circuit blocks. Incidentally, the operation program is externally downloaded to the external memory 9 via the host computer.

In the splicing apparatus 1, each circuit block (input processing unit 3, data processing unit 4,
The output processing unit 5, the CPU 6, and the data analysis unit 20) are connected to the external memory 9 via the data bus 7, and each of the circuit blocks can write desired data to the external memory 9 and, at the same time, write data to the external memory 9. The desired data can be read out from the. The data bus 7 is provided with an arbitration function, and arbitration of the right to use the data bus 7 by this arbitration function prevents access to the external memory 9 from colliding.

The input processing unit 3 receives the transport streams S1 and S2, and converts the TS packets constituting the transport streams S1 and S2 into the same PID (Packet Identification: packet identification information) as shown in FIG. It arranges for every TS packet which it has. Then, as shown in FIG. 3, the input processing unit 3
A local header (64 [byte] length) as an area for writing information on the TS packet is added to the beginning of the 8 [byte] length, and a reserve (4 [byte] as a reserved area) is added at the end of the TS packet. In addition, a TS block having a length of 256 [bytes] is generated as a whole by adding the “length”, and the TS block is sequentially written to the external memory 9.

As shown in FIG. 4, the TS packet is a PES (Packetized Element), which is a basic unit of video coding in the MPEG (Moving Picture Experts Group) 2 system.
al Stream) Generated by adding a TS header to a payload obtained by dividing a packet. The input processing unit 3 uses the same PI
D, the leading address of the payload of the TS block counted from the beginning of the payload data of the TS block (that is, the beginning of the PES packet) is denoted by “ab”.
s sum bgn ", the end address of the payload of the TS block is written in" abs sum end ", and the pointer information indicating the head of the payload of the TS block is written in" payload ptr ". Further, the input processing unit 3 writes the information of the adaptation field of the TS block in “Else header”.

The data analysis unit 20 stores TS blocks of video data to be spliced in the external memory 9.
And analyzes the data based on the local header, writes the data of the analysis result in the local header of the TS block, writes the TS block back to the external memory 9, and adds various data added at the time of compression encoding and packetization. The parameters are taken out and stored in the external memory 9.

The data to be written in the local header are "PES pyld ptr", "PES pcktlngt ptr", "PES
hdr lngt ptr "," PTS ptr "," DTS ptr "and" A
U ptr ”. “PES pyld ptr” is pointer information indicating the head of the payload of the PES packet. If the head of the payload of the PES packet does not exist in the TS block, “0xff” is entered. “PES pckt lngt ptr” is a pointer indicating the head of the packet length information of the PES packet. If the packet length information does not exist in the TS block, “0xff” is entered. "PES hdr lngt ptr" is PE
This is a pointer indicating the head of the header length information of the S packet. If the header length information does not exist in the corresponding TS block, “0x
ff ”is entered.

[PTS ptr] is pointer information indicating the head of the display time information PTS of the video data. If the head of the PTS does not exist in the TS block, "0xff" is entered. “DTS ptr” is pointer information indicating the head of the display time information DTS of the video data.
If it is not in the S block, “0xff” is entered. "AU p
“tr” is pointer information indicating the head of the access unit. If the head of the access unit does not exist in the TS block, “0xff” is entered.

The parameters extracted from the TS block include PT, which is display time information of encoded data.
S (Presentation Time Stamp), DTS (Decoding Time Stamp) as decoding time information of encoded data, PE
S packet length, PES header length, bit rate, VBV
(Video Buffer Verifier: virtual buffer for controlling the amount of generated code) Size, bit rate extension, VBV size extension, closed GO
The parameters at the time of compression encoding and packetization, such as P, temporary reference coding type, VBV delay, and the like.

Here, when the input transport stream is a multi-program, TS packets of different programs are mixed in the transport stream. Therefore, complicated operations are required to extract these parameters. However, in the splicing apparatus 1, since the transport stream is sorted by the input processing unit 3 for each TS packet having the same PID and stored in the external memory 9, these parameters can be easily extracted. Since the splicing process is performed on at least two or more pieces of video data, the data analysis unit 20 is configured to analyze a plurality of video data streams in parallel by time division processing.

The CPU 6 determines a connection point for determining the splicing process based on the parameters obtained by the analysis of the data analysis unit 20, and determines whether it is better to insert blanking data or stuffing data at the connection point. Is sent to the data processing unit 4 as a data combination command.

The data processing section 4 receives the data combination command and executes splicing processing on the video data to be spliced. That is, the data processing unit 4 reads a plurality of pieces of video data to be spliced from the external memory 9 in response to the data combining command, inserts blanking data and stuffing data if necessary, and links the plurality of pieces of video data. As a result, the connected video data is generated and stored in the external memory 9 again.

The output processing unit 5 multiplexes the concatenated video data and other video data obtained by the splicing process among the video data stored in the external memory 9 to generate and output an output transport stream Sout. I do.

(2) Configuration of Data Analysis Unit FIG. 5 shows a data analysis unit 20 according to an embodiment of the present invention as a whole, and the CPU 6 (FIG. 1) transmits an operation program of the data analysis unit 20 from the external memory 9. The entire data analysis unit 20 is controlled by downloading the program to the program memory 25 and executing the program. The capacity of the program memory 25 is 24 [bit] × 1024 [word], and the address of the program memory 25 is specified by the program counter 24. The program decoder 26 decodes the command code of the operation program specified by the program counter 24 and outputs the decoding result to each module of the data analysis unit 20.

The jump destination determining section 23 updates the counter value by incrementing the counter value of the program counter 24 or adding a relative jump value to the counter value in accordance with the operation program. The updating of the counter value is performed at the end of one command code.

The data analyzer 20 has a TS [] memory 32, a G
It has three internal memories, an M [] memory 42 and an RM [] memory 52. The writing and reading of each internal memory are controlled by the TS memory control unit 31, the GM memory control unit 41, and the RM memory control unit 51, respectively. Is done. The capacity of each of these three internal memories is 8 [bit] × 256.
[word] and the data length of the TS block (256 [byt
e]).

The TS [] memory 32 is a memory for storing the TS blocks read from the external memory 9, and the computing unit 22 accesses the TS [] memory 32 to load the TS blocks (ie, the PES packets). Read the desired data from within. The GM [] memory 42 is used as a general-purpose memory, and is used for saving register values in an operation program.

The TS [] memory 32 and the GM [] memory 42
Are indirectly addressed by the TS memory register 33 and the GM memory register 43, respectively. For example,
TS [RegA0] indicates the value of the RegA0 address in the TS [] memory 32.

The register RegA + of the TS memory register 33
Is a register with an increment function.
It indicates the address from the beginning of the ES packet, and the PES packet (that is, the payload of the TS block) can be continuously accessed by using the register RegA +.

The SEG register 34 is a register with an increment function, and specifies the position (order) of the TS block in the TS block sequence counted from the head of the TS block sequence arranged by the same PID. The TS memory control unit 31 stores the SEG register 34
Is read from the external memory 9. Further, the TS memory control unit 31 outputs “abs sum bgn” and “abs su
mend ”and the register RegA +, the SEG register 34 is incremented (+1 or −
1) Yes.

The RM [] memory 52 is a memory for storing the results of the analysis performed by the computing unit 22. When the RM [] memory 52 becomes full, the analysis results are written to the external memory 9.

The first arithmetic unit input selector 27A inputs its input to the TS memory control unit 31 in accordance with the operation program.
GM memory control unit 41, RM memory control unit 51, TS memory register 33, GM memory register 43, and SEG
Select from the register 34, and output it to the first
To the input end of the Similarly, the second arithmetic unit input selector 27B selects its input from the TS memory control unit 31, the GM memory control unit 41, the RM memory control unit 51, the TS memory register 33, the GM memory register 43, and the SEG register 34, The output is supplied to a second input terminal of the arithmetic unit 22.

The operation unit 22 as an operation means adds, shifts, and performs a logical operation (AND) on the data supplied from the first operation unit input selector 27A and the second operation unit input selector 27B according to the operation program. , OR), inversion, constant loading, and the like, and stores the calculation result in a module (TS memory register 3
3, SEG register 34, GM memory register 43, R
M memory register 53, TS memory control unit 31, GM memory control unit 41, and RM memory control unit 51).

The write pulse generator 28 includes the data analyzer 2
0 modules (TS memory register 33, GM memory register 43, RM memory register 53, SEG register 34, TS memory control unit 31, GM memory control unit 4)
1 and the RM memory controller 51).

The registers and memories of the data analysis unit 20 are all address-mapped, and the CPU 6
(FIG. 1) and the state saving unit 56 can be accessed via an input selector 58 and an output selector 59. Then, the data analysis unit 20 includes the state saving unit 56
By saving and reading the internal state (register and memory) of the data analysis unit 20 to and from the external memory 9 via the external memory 9, a plurality of video data streams can be time-divisionally processed.

FIG. 6 shows a use area of the data analysis unit 20 in the external memory 9 when time-division processing is performed on four streams, a program area of the data analysis unit, and an RM ring for storing data from the RM [] memory 52. It has an area and a register save area for saving the internal state of the data analysis unit 20, and the RM ring area and the register save area are divided into four. The RM ring area is used in a ring configuration that returns to the head of the memory area when the memory area reaches the turn-back position.

Next, reading of a TS block by the TS memory control unit 31 will be described. On the external memory 9, the PES packet exists discontinuously as the payload of the TS block. T as control means of storage means
The S memory control unit 31 reads the TS block from the external memory 9 according to the operation program and
, And by reading only the payload (ie, PES packet) from the TS block, the payload can be continuously accessed.

That is, when a payload read command is issued by the operation program, the TS memory control unit 3
1 corresponds to the TS designated by the SEG register 34.
The block is read from the external memory 9 and stored in the TS [] memory 32. The data to be read in such a read instruction is expressed by “TS [R
egA +] ”.

At this time, the TS memory control unit 31 sets “abs sum bg” written in the local header of the TS block.
n ”,“ abs sum end ”and the register RegA +, the data to be read (TS [RegA +]) is
It is determined whether or not the data to be read exists in the TS block stored in the memory 32. If the data to be read is not in the TS block, the TS including the data to be read is incremented by the SEG register 34.
The block is read from the external memory 9 and the TS [] memory 3
2 is stored.

FIG. 7 shows the TS memory control unit 31 as a whole, and the first adder 62A converts the register value RegA + to “ab”
s sum end ”and subtracts the result into the first determination unit 63A.
Output to The first determination unit 63A outputs “0” to the third adder 62C if the subtraction result is negative, and outputs “1” otherwise. Similarly, the second adder 62B subtracts “abs sum bgn” from the register value RegA +, and outputs the result to the second determination unit 63B. Second determination unit 63
B outputs “−1” to the third adder 62C when the subtraction result is negative, and outputs “0” otherwise. Third
Adder 62C adds the outputs of the first determination unit 63A and the second determination unit 63B, and outputs the result to the fourth adder 62D as a calculation result S62C.

The operation result S62C indicates that TS [RegA +] indicates the inside of the TS block currently stored in the TS [] memory 32 (that is, abs sum bgn ≦ RegA + ≦ abs su
mend), it becomes “0”, and TS [RegA +] is T
S [] indicates a TS block before the TS block stored in the memory 32 (that is, RegA + <ab
s sum bgn) becomes “−1”, and TS [RegA +] indicates a TS block after the TS block currently stored in the TS [] memory 32 (ie, abs)
It becomes "1" when sum end <RegA +).

The fourth adder 62D is provided in the SEG register 3
The calculation result S62C is added to the register value of No. 4 and the result is supplied to the first comparator 64A as the calculation result S62D.
The first comparator 64A supplies the operation result S62D to the SEG register 34 and rewrites the SEG register 34 in response to the write command from the operation unit 22.

As a result, the SEG register 34 stores TS [R
If egA +] indicates the inside of the TS block currently stored in the TS [] memory 32, no change occurs, and TS [RegA +] is the TS block preceding the TS block currently stored in the TS [] memory 32. If it indicates a block, it is decremented by one, and if TS [RegA +] indicates a TS block subsequent to the TS block currently stored in the TS [] memory 32, it is incremented by one.

The value of the SEG register 34 can be rewritten directly from the arithmetic unit 22.

The read control unit 65 reads the TS block specified by the SEG register 34 (that is, the TS block including the data to be read (TS [RegA +])) from the external memory 9 and stores it in the TS [] memory 32. Store.
The rewriting (increment) of the SEG register 34 and the reading of the TS block are performed by the adders 62A-62.
D, hardware processing by the determination units 62A and 62B and the comparator 64A, the processing is executed at high speed.

TS [RegA +] in the TS [] memory 32
Is obtained by RegA + −abs sum bgn + paylode ptr. The fifth adder 62E adds the paylode ptr to the output (RegA + −abs sum bgn) of the second adder 62B, and supplies the result to the TS [] memory 32 via the comparator 64B as the operation result S62E. . The TS [] memory 32
TS [RegA +] is read by reading the data of the TS block using the operation result S62E as a read address,
This is supplied to the arithmetic unit 22 (FIG. 5).

Thus, when a read command of the payload is generated, the TS memory control unit 31 reads the TS block including TS [RegA +] from the external memory 9 and stores it in the TS [] memory 32, and stores TS [RegA +] in the TS [RegA +]. [] Read from the memory 32 and output to the arithmetic unit 22. TS [RegA +] can be read from the outside of the TS memory control unit 31 without being aware of which TS block contains TS [RegA +], whereby the PES packet is divided as a payload. The PES packet can be continuously accessed without being aware of the PES packet.

The arithmetic unit 22 (FIG. 5) calculates and analyzes the payload thus read out based on the operation program, thereby obtaining the PTS, DTS, PES packet length, and PTS written in the PES packet. The parameters such as the PES header length, bit rate, VBV size, bit rate extension, VBV size extension, closed GOP, temporary reference coding type, VBV delay, etc. are extracted, and these are extracted from the RM via the RM memory control unit 51. [] Write to the memory 52.

The RM memory register 53 is a register with an increment function, and is incremented every time data is written to the RM [] memory 52 by 1 [byte]. The RM memory control unit 51 monitors the register RegC + of the RM memory register 53, and when the value of the register RegC + has become an integral multiple of 256 (that is, the RM [] memory 52 (capacity 256 [byte]) is full). ), The RM [] memory 52 is read and written to the external memory 9 (FIG. 1).

The arithmetic unit 22 analyzes the read payload and reads “PES pyld” written in the PES packet.
ptr "," PES pckt lngt ptr "," PES hdr lngt pt "
The parameters "r", "PTS ptr", "DTS ptr" and "AU ptr" are extracted, and these are entered in the local header shown in FIG.

Here, the data to be analyzed (PES
The payload does not always start from the beginning of the PES packet, and it is meaningless to read and analyze the TS blocks one by one from the beginning of the TS block sequence. For this reason, the operation program uses the “payl
The TS block is skipped by incrementing the SEG register 34 until the "oad unit start indicator" is detected.

On the other hand, a search section 6 as a pattern matching means
0 is set according to the search command by the operation program.
Using the search pattern specified in advance, the TS [] memory 3
When the pattern matching is performed by searching the payload of the TS block stored in No. 2 and a bit string that matches the search pattern is detected, the end address of the bit string is set to “Matc” in the local header of the TS block.
h ptr 0-Match ptr7 ”.

The search pattern specified here includes a sequence start code, a group start code, a picture start code, a slice start code, and the like written in the PES payload of the PES packet. These pieces of information are used in subsequent processing.

At this time, the search unit 60 stores the last 3 [bytes] of the searched payload in consideration of the case where the bit string targeted for the search pattern exists across the TS blocks, When the search is performed, the search including the stored 3 [bytes] is performed.

The search unit 60 is provided with the TS memory control unit 3
1 and at the same time as reading the TS block,
Pattern matching is performed in advance from the position indicated by r (that is, the beginning of the PES payload), and the result at this time (the end address of the bit string that matches the search pattern)
Save. Such processing is called pre-search. If the TS block in the TS [] memory 32 is found to be composed of only the PES payload by searching the TS block, the result of the pre-search is entered in the local header and the search is terminated.

FIG. 8 shows a state transition of the search unit 60,
“Pause” represented by 0 is a state in which the search unit 60 is not operating.

The “pre-search” represented by 3d1 is the TS
A transition is made when a block is read from the external memory 9 to the TS [] memory 32, and a pattern search is performed for the payload in the TS [] memory 32 with "payload ptr" as the head of the search.

The "determine presence / absence of PES header" represented by 3d2 determines the presence / absence of a PES header based on "PES pyld ptr".

The “search using PES pyld ptr” represented by 3d3 is performed by using “PES pyld ptr” as the head of the search.
This is a state in which a pattern search is performed for the payload in the TS [] memory 32.

The "pattern match presence / absence determination" represented by 3d4 and 3d5 is a state in which the CPU 9 determines whether or not the pattern designated by the CPU 9 is within the search range.

The “matched address transfer” represented by 3d6 indicates the position of the pattern-matched data from the beginning of the TS block using Match ptr 0 to Ma in the local header.
This is the state to transfer to tchptr 7.

The "payload 3byte at the end" represented by 3d7
“Save” is a state in which the last 3 [bytes] of the payload are saved in order to process data spanning the TS block in the next search.

The state requiring the longest processing time among the above states is "search using PES pyld ptr" represented by 3d3, and requires about 60 clocks at the maximum. Also 3d
The “pre-search” represented by 1 is performed in parallel with the reading of the TS block, and is not added to the processing time. Other states are executed by condition determination or byte copying, and therefore require about 1 to 2 clocks.

In these states, transitions occur in the following three patterns in descending order of occurrence probability. First, when the payloads of the TS packets are all PES payloads, transition pattern 1 is 3d0 → 3d1 → 3d0 → 3d2 → 3d4 → (3d6 →)
Transition is made in the order of 3d7 → 3d0. Here, (3d6 →) occurs when the search pattern matches, and the result of the pre-search is used. In this case, the processing time is about 8 clocks.

When the payload of the TS packet is only the TS adaptation field or the PES header, the transition pattern 2 transits in the order of 3d0 → 3d1 → 3d0 → 3d2 → 3d0. In this case, no search is performed, and the processing time is about two clocks.

When the payload of the TS packet is only the PES header and the PES payload, the transition pattern 3 is 3d0 → 3d1 → 3d0 → 3d2 → 3d3 → (3d6 →) 3d7 →
Transition in order of 3d0. Here, (3d6 →) occurs when the search pattern matches. In this case, the processing time is a maximum of 68 clocks.

Most TS packets have transition pattern 1
(When the payload of the TS packet is all PES payloads). In transition pattern 1, the result of the pre-search can be used, and "PE
Since it is not necessary to execute “search using Spyld ptr” (3d3), the time required for the search can be significantly reduced.

When the local header of the TS block is rewritten by the analysis and the search, the TS memory control unit 31 rewrites the TS block from the TS [] memory 32 to the external memory 9. This write back is stored in the external memory 9
This is performed immediately before reading of a TS block from.

FIG. 9 shows the state transition of the soft code processing of the operation program, and the processing unit is represented by function.

"Register initialization" represented by h00
Is initialization processing of general-purpose registers used in the soft code.

"PES start confirmation" represented by h01
Confirms the head of the PES by detecting the payload unit start indicator of the TS header.

In the "increment of SEG" represented by h02, 1 is added to the SEG register 34. Since the SEG register 34 points to the TS packet, it means that by adding 1, it moves to the next TS packet.

The “Initialization of RegA +” represented by h03 is
Load "abs sum bgn" into register RegA +. Thus, RegA + indicates the head of the TS packet.

"PES header start" represented by h04
Detects “payload unit start indicator” again and confirms whether or not it is the head of PES.

"PES header length analysis" represented by h05
Reads “PES packet length”, “PTS DTS flag”, etc.

The “PTS analysis” represented by h06
Read and save S.

The “DTS analysis” represented by h07 is
Read and save S.

"PES pyld ptr calculation" represented by h08
Is the pointer "PES pyld ptr
Is calculated from the PES header length.

The "search execution" represented by h10 executes a search described later.

The "SEG register check" represented by h11 confirms whether or not the increment of the SEG register 34 has occurred by RegA +.

"Match ptr check" represented by h12
Checks the "Match ptr" to see if there is a pattern match by the search command.

"Sequence layer analysis" represented by h13
Is the analysis of the sequence header portion when the SHC (Sequence Header Code) is found (Bit Rate Value, VBV Bu
ffer Size Value).

The “sequence extension layer analysis” represented by h14 is an ESC (Extension Start Code)
Analysis of the sequence header part when
e Extension, VBV Buffer Size Extension, etc.).

The “GOP layer analysis” represented by h15
The GOP layer is analyzed when an SC (Group Start Code) is found.

The "picture layer analysis" represented by h16 is
The picture layer is analyzed when a PSC (Picture Start Code) is found.

The "sequence end" represented by h17
“Calculation of picture size” is based on SEC (Sequence end Code
) Is a process of calculating the generated code amount by subtracting the PES header length from RegA +.

Thus, the data analyzer 20 analyzes the payload (ie, PES packet) of the TS block, writes the result in the local header of the TS block, and outputs the result to the external memory 9.

FIG. 10 shows a state transition of the entire data analysis unit 20. The "pause" indicated by 5h00 is a state in which all operations in the module are stopped. Begin. In this state, the CPU 6 sets various registers and issues commands. The register setting includes setting of an area of a TS packet, a start position, an end position, a work area of an external memory (a program position, a state save position, a storage position of an analysis result), a pattern to be searched by a search command, and the like.

"Program read" represented by 5h01
Loads a program from the external memory 9 in response to a command from the CPU 6.

“TS [] read” represented by 5h02 is
The TS packet indicated by the SEG register is loaded from the external memory 9 according to a command from the CPU 6.

"Program execution" represented by 5h10 is
The program is executed from the position indicated by the program counter in response to a start command from the CPU 6. The program is executed until “5h00” reaches the end position of the preset TS packet, “5h13”, “5h12”, “5h14”, “5h
17 ”is repeated. The state transits to “5h00” when the end position of the TS packet is reached or in response to a stop command from the CPU 6.

"Automatic TS [] export" represented by 5h13
Writes the contents of the TS [] memory 32 back to the external memory 9 when a header or the like is written in the TS [] memory 32 by the program code. This state occurs immediately before reading the automatic TS [].

"Automatic TS [] read" represented by 5h12
Is a case where the program code accesses the TS [] memory 32, and there are the following two cases.

That is, TS [RegA0 to RegA5] is accessed after the SEG register is rewritten as the first case, and TS [Reg + 0] indicates the next TS packet as the second case. If (in the local header, abs su
m bgn, abs sum end and RegA + are compared). After reading into the TS [] memory 32, “5h1
"0".

"Automatic RM [] writing" represented by 5h14
When the RM [] memory 52 is full, that is, when the register RegC + has become an integral multiple of 256 (equal to the size of the RM [] memory 52), the data in the RM [] memory 52 is stored in the external memory. Write to memory 9.

The "pattern search" represented by 5h17 is
The transition is made when a search command is generated in the program code. When the CPU 6 detects a search pattern that matches a preset search pattern, the CPU 6 detects a pattern at a predetermined position (match ptr0 to match ptr7) in the local header of the TS block. After writing the end address, `` 5h1
"0".

“RM [] write” represented by 5h04 is
The data in the RM [] memory 52 is written to the external memory 9 according to a command from the CPU 6.

The “status saving” represented by 5h08 is executed by the CPU
6, the internal state of each module of the data analysis unit 20 is saved in the external memory 9. This state is used when a plurality of PID streams are subjected to time division processing.

[0105] "Evacuation reading" represented by 5h07
"5h08" (status save) by command from PU6
Is read back from the external memory 9 to each module of the data analysis unit 20. Thus, the processing can be restarted from the state saved at “5h08”.

Each of the above-mentioned states transits under the following conditions.

5h00 → 5h01, 5h00 → 5h02, 5h00 → 5h03, 5h
00 → 5h04、5h00 → 5h07、5h00 → 5h08: All are CPU6
Automatically transitions to 5h00 after the end of status.

5h00 → 5h10: Transition is made by a start command from the CPU 6.

5h00 → 5h12: There is no writing in the TS block, and after the program code rewrites the SEG register 34, TS [C] and TS [RegA0 to RegA5] are designated as “input” (see machine code described later). Or TS [Reg
A +] is specified as “input” and TS including TS [RegA +]
Transition is made when the packet is in the external memory 9.

5h10 → 5h13 → 5h12: T under the condition of 5h10 → 5h12
If there is a write in the S block, after the 5h13 state ends,
Be sure to transit to 5h12 state.

5h10 → 5h14: RM [RegC +] is designated as “output”, and transition is made when the RM [] memory 52 is full.

5h10 → 5h17: When a search command is used in the program code, after the search processing is completed, the state automatically transitions to the 5h10 state and the program processing is restarted.

These transitions are (5h00 → 5h01 →) (5h00
→ 5h08 →) 5h00 → 5h07 → 5h00 → 5h02 → 5h00 → 5h10 → (5h1
7 → 5h10, 5h13 → 5h12 → 5h10, 5h12 → 5h10, 5h14 → 5h1
0) → 5h00 → 5h14 → 5h00 → 5h08 → 5h00.

Here, (5h00 → 5h01 →) occurs only when the system is started. (5h00 → 5h08 →) is repeated as many times as the number of PID streams to be subjected to time division processing, and the initial state is stored. (5h17 → 5h10, 5h13 → 5h12 → 5h10, 5h
12 → 5h10, 5h14 → 5h10) occur repeatedly in any order.

FIGS. 11 to 18 show examples of the machine language code of the operation program.

In the above configuration, the search section 60 of the data analysis section 20 uses the search pattern specified in advance by using TS [] according to the search command by the operation program.
When the pattern matching is performed by searching the payload of the TS block stored in the memory 32 and detecting a bit string that matches the search pattern, the end address of the bit string is set to “Match ptr 0 to” in the local header of the TS block. Fill in Match ptr 7 ". At this time, the search unit 60 stores the last 3 [bytes] of the searched payload in consideration of the case where the bit string targeted for the search pattern exists across the TS blocks, and stores the last 3 bytes in the next search. Search is performed including the stored 3 [bytes].

The search section 60 performs a pre-search simultaneously with reading of the TS block from the TS [] memory 32,
Pattern matching is performed in advance from the payload ptr indicating the beginning of the PES payload, and the result at this time is stored. If the TS block in the TS [] memory 32 is found to be composed of only the PES payload by searching the TS block, the result of the pre-search is entered in the local header and the search is terminated.

According to the above configuration, the payload of the TS block stored in the TS [] memory 32 is searched, the result is written in the local header, and the pre-search is performed simultaneously with the reading of the TS block. When the result is stored and it is determined that the TS block is composed of only the PES payload, the search can be performed at high speed by writing the result of the pre-search in the local header.

[0119]

As described above, according to the present invention, the packet data stored in the second storage means is compared with a predetermined bit pattern by the pattern matching means, and the result is written in the packet. When the packet is written in the second storage means, the bit pattern is collated from the beginning of the encoded data in advance and the collation result is stored, and if the payload of the packet is the encoded data only, The analysis can be performed at high speed by writing the collation result in the packet.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a splicing device.

FIG. 2 is a schematic diagram showing a state of organizing TS packets by PID.

FIG. 3 is a schematic diagram illustrating a data format of a TS block.

FIG. 4 is a schematic diagram illustrating a divided state of a PES packet.

FIG. 5 is a block diagram showing a configuration of a data analysis unit according to one embodiment of the present invention.

FIG. 6 is a schematic diagram illustrating a use area of an external memory.

FIG. 7 is a block diagram illustrating a configuration of a TS memory control unit.

FIG. 8 is a schematic diagram illustrating a state transition of a search unit.

FIG. 9 is a schematic diagram illustrating a state transition of a program code.

FIG. 10 is a schematic diagram illustrating a state transition of a data analysis unit.

FIG. 11 is a table showing machine language codes of jump instructions.

FIG. 12 is a table showing a machine language code for constant load.

FIG. 13 is a table showing a machine language code for constant load.

FIG. 14 is a table showing machine language codes of operation register-register.

FIG. 15 is a table showing machine language codes of operation register-register.

FIG. 16 is a table showing machine language codes of operation register-register.

FIG. 17 is a table showing machine language codes of operation register-immediate;

FIG. 18 is a table showing machine language codes of operation register-immediate;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Splicing apparatus, 2 ... Host computer, 3 ... Input processing part, 4 ... Data processing part, 5 ... Output processing part, 6 ... CPU, 7 ... Data bus, 8 ... Host bus, 9 external memory, 10 interface unit, 20 data analysis unit, 22 arithmetic unit, 23
... jump destination determination unit, 24 ... program counter, 2
5 Program memory, 26 Program decoder, 27A, 27B Computing unit input selector, 28
Write pulse generator, 31 ... TS memory controller, 32 ...
... TS [] memory, 33 ... register A, 34 ... SEG
Register, 41 ... GM memory control unit, 42 ... GM []
Memory, 43: Register B, 41: RM memory control unit, 42: RM [] memory, 53: Register C, 56
…… State saving unit, 57 …… External memory control unit, 58 ……
Input selector, 59 ... Output selector, 60 ... Search section.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H04N 7/24 (72) Inventor Takuya Kitamura 7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation F-term (reference) 5C059 KK39 MA00 RB02 RB10 RB16 RC01 RE01 SS02 UA38 5C063 AB03 AB07 AC01 AC10 CA23 CA34 5D110 BB20 CA05 CA14 CA17 CA50 CB06 CD16 CF11 CJ14 CK02 CM12 CM16 5K028 AA06 EE03 KK03 H01 GA07

Claims (4)

[Claims] 1. A data analysis apparatus for analyzing a transport stream composed of a series of predetermined packets and obtaining parameters written in encoded data divided and assigned to payloads of the respective packets. A first storage unit that stores the transport stream; a second storage unit that stores one packet of the packet; and a second storage unit that reads out the packet including predetermined read target data from the first storage unit. Control means for a storage means for storing the read target data from the second storage means and outputting the read target data; calculating means for calculating the read target data to obtain the parameter; The packet data stored in the storage means is compared with the bit pattern of a predetermined parameter, and the packet If Doo data and the bit pattern is matched, the data analysis device characterized by comprising a location information of the matching data, and a pattern matching unit to fill out the packet. 2. The pattern matching means stores the data at the end of the packet stored in the second storage means, and stores a packet next to the packet stored in the second storage means. 2. A bit pattern extending over two packets is detected by adding the end data to the beginning of the next packet and checking the bit pattern when the bit pattern is compared. Data analysis device as described. 3. The pattern matching means, when the packet is read from the first storage means to the second storage means, detects a leading position of the encoded data, and pre-determines the encoded data from the leading position. The bit pattern is collated and the result is stored, and when the payload of the packet read into the second storage means is composed of only the encoded data, the stored collation result is written in the packet. The data analysis apparatus according to claim 1, wherein the data analysis is performed. 4. A data analysis method for analyzing a transport stream composed of a series of predetermined packets and obtaining parameters written in encoded data divided and assigned to payloads of the respective packets. The transport stream is stored in a first storage unit, the packet including predetermined read target data is read out from the first storage unit and stored in a second storage unit, and stored in the second storage unit. Comparing the data of the packet with the bit pattern of a predetermined parameter, and, when the data of the packet matches the bit pattern, writing position information of the matched data in the packet. analysis method.