JP2000305061A - Matrix type liquid crystal device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a liquid crystal panel from being applied with an abnormal voltage caused by a residual voltage of a scanning voltage generating means, and also prevent a scanning voltage driving means from being damaged, when an external power source is switched off in a matrix type liquid crystal display device. SOLUTION: The control circuit 50 of this matrix type liquid crystal display device controls a scanning electrode driving circuit 70 so that the scanning electrode driving circuit 70 selects elimination voltages from plural voltages of a scanning voltage forming part 31 when a power source monitoring circuit 40 detects that an external power source 20 has been switched off. Associated with this, this scanning electrode scanning circuit 70 sequentially applies the elimination voltages to each scanning electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a matrix type liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, this type of matrix type liquid crystal display device is composed of a liquid crystal panel and a drive control device for driving and controlling the liquid crystal panel. Here, the drive control device includes a scan electrode drive circuit and a signal electrode drive circuit that drive the liquid crystal panel, a control circuit that controls the scan electrode drive circuit and the signal electrode drive circuit with a control signal, the scan electrode drive circuit, A voltage forming circuit for forming various voltages to be supplied to the signal electrode driving circuit and the control circuit.

Here, the voltage forming circuit includes a scanning voltage forming section, a luminance voltage forming section, and a logic voltage forming section. The scanning voltage forming section receives a power supply voltage from an external power supply and generates a plurality of voltages. It is formed and output to a scan electrode drive circuit as a scan voltage. The luminance voltage forming unit receives a power supply voltage from an external power supply, forms a plurality of voltages, and outputs the plurality of voltages to the signal electrode driving circuit as a luminance voltage. The logic voltage forming unit receives a power supply voltage from an external power supply, forms a logic voltage, and outputs the logic voltage to a control circuit, an interface circuit, a signal electrode drive circuit, and a scan electrode drive circuit. And this control circuit receives the logic voltage,
The control signal is output to the scan electrode drive circuit and the signal electrode drive circuit.

[0004]

In the above-described drive control device, at least the circuit configuration of at least the scanning voltage forming section of the voltage forming circuit usually has a capacitance type circuit configuration. In addition, the scanning voltage formed by the scanning voltage forming unit usually includes a high voltage. For this reason, even if the scanning voltage forming circuit is cut off from the external power supply, the voltage already generated in the scanning voltage forming unit does not immediately discharge due to the capacitance of the above-mentioned capacitance type circuit configuration, but remains. It remains transiently as a voltage.

Accordingly, when the voltage forming circuit is cut off from the external power supply, for example, if the discharge of the scanning voltage forming unit is delayed more than the discharging of the logic voltage forming unit, the scanning voltage is controlled with the control signal of the control circuit stopped. The residual voltage remains. For this reason, the scanning voltage driving circuit
The control circuit loses control, malfunctions due to the residual voltage, applies an abnormal voltage to the liquid crystal panel,
There is a problem that the liquid crystal panel is adversely affected.
In addition, there is a disadvantage that the scanning voltage driving circuit is damaged due to the residual voltage. This is particularly remarkable when the scanning voltage driving circuit is formed of an IC circuit.

[0006] Regarding the above, for example, Japanese Unexamined Patent Publication No.
As disclosed in Japanese Unexamined Patent Publication No. 220508, when the disconnection of the voltage forming circuit from the external power supply is detected, the scanning voltage forming section is immediately disconnected from the external power supply, and then the logic voltage forming section is connected to the external power supply. It can be considered that the residual voltage is forcibly eliminated by controlling so as to cut off from the residual voltage.

However, according to the above publication, it is necessary to maintain the supply of the logic voltage from the logic voltage forming unit until the scanning voltage forming unit is cut off from the external power supply.
Such maintenance cannot be easily realized because the external power supply has already been cut off. As a result, the above-mentioned problem is difficult to solve. In view of the above, the present invention has been made to address the above-described problems, and in a matrix type liquid crystal display device, when an external power supply is cut off, the application of an abnormal voltage to a liquid crystal panel due to a residual voltage of a scanning voltage forming unit is prevented. An object of the present invention is to prevent the scanning voltage driving means from being damaged.

[0008]

In order to solve the above-mentioned problems, according to the first aspect of the present invention, a matrix type liquid crystal display device comprises m scanning electrodes (X1 to Xm) and a liquid crystal provided on these scanning electrodes. A liquid crystal panel (P) including n signal electrodes (Y1 to Ym) positioned so as to intersect and form a plurality of pixels in a matrix, and an image data signal for outputting image data as an image data signal Output means (60), voltage forming means (31) supplied with a power supply voltage from an external power supply (20) to form a plurality of voltages and generate the plurality of voltages as a scanning voltage, and a scanning voltage from the voltage forming means. While scanning the m scanning electrodes, writing the image data to the pixels on the scanned scanning electrodes, and operating to erase the written image data. 0) and signal electrode driving means (32, 80, 90) operating to input a signal voltage to n signal electrodes in accordance with the image data signal in synchronization with scanning by the scanning electrode driving means; Control means (50) for controlling the scan electrode driving means so that the scan electrode driving means selects the scanning voltage of the voltage forming means from a plurality of voltages in synchronization with the synchronization signal; A matrix display is performed by a plurality of pixels according to the operation of the signal voltage driving unit.

The matrix type liquid crystal display device has power supply monitoring means (4) for monitoring whether or not the external power supply is shut off.
0), the control means causes the scan electrode driving means to select a voltage within the range of the power supply voltage as a fixed voltage when the monitoring state of the power supply monitoring means is in a state corresponding to the interruption of the external power supply. And the scanning electrode driving means applies the fixed voltage to each scanning electrode.

Accordingly, when the monitoring state of the power supply monitoring means becomes a state corresponding to the interruption of the external power supply, the voltage of each scan electrode is fixed to a voltage within the range of the power supply voltage.
It does not cause application of an abnormal voltage to the liquid crystal panel or destruction of the scanning electrode driving means. Here, as in the second aspect of the present invention, in the matrix type liquid crystal display device according to the first aspect, the control unit determines that the monitoring state of the power supply monitoring unit becomes a state corresponding to the interruption of the external power supply. Alternatively, control may be performed such that the scan electrode driving unit selects any one of the plurality of voltages of the voltage forming unit as the fixed voltage.

According to a third aspect of the present invention, in the matrix type liquid crystal display device according to the first or second aspect, the control means scans a voltage close to a central value among the plurality of voltages as the fixed voltage. Control may be performed so that the electrode driving means is selected. As a result, the operation and effect of the invention described in claim 1 or 2 can be achieved, and also, the destruction due to the formation of the short circuit in the scan electrode driving means does not occur.

According to a fourth aspect of the present invention, in the matrix type liquid crystal display device according to any one of the first to third aspects, the scanning electrode driving means scans the m scanning electrodes. Is performed by line-sequential scanning, the control means generates a control signal and a clock in synchronization with a synchronization signal, and the scanning electrode driving means captures the control signal in synchronization with the clock, and A voltage is sequentially applied to the scanning electrodes that have been line-sequentially scanned.

Thus, the current flowing through the scanning electrode driving means is very small as compared with the case where a fixed voltage is applied to all the scanning electrodes at the same time, and the load on the liquid crystal panel can be reduced. The operation and effect of the invention described in the first aspect can be achieved. According to the fifth aspect of the present invention, in the matrix type liquid crystal display device according to the fourth aspect, the control unit is configured to control when the monitoring state of the power supply monitoring unit becomes a state corresponding to the interruption of the external power supply. There is provided frequency changing means (53) for changing the frequency of the clock so as to be higher than the frequency before the monitoring state of the power supply monitoring means becomes a state corresponding to the interruption of the external power supply. Further, the scan electrode driving means sequentially applies the fixed voltage to the scan electrodes which have been line-sequentially scanned in synchronization with the clock at the frequency changed by the frequency changing means.

Thus, the time required to apply a fixed voltage to all the scan electrodes when the external power supply is cut off is greatly reduced as compared with the time required to scan all the scan electrodes before the external power supply is cut off. Can be reliably achieved before the logic voltage is stopped even after the interruption and the control by the control means is lost.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a matrix type liquid crystal display device according to the present invention will be described below with reference to FIGS. FIG. 1 shows a schematic overall configuration of the liquid crystal display device. This liquid crystal display device includes a liquid crystal panel P and a drive control device D.

The liquid crystal panel P is formed by sealing an antiferroelectric liquid crystal between the two electrode substrates 10. Both electrode substrate 1
0 has m scanning electrodes X1 to Xm built therein, and the other electrode substrate 10 has n signal electrodes Y1 to Ym.
n. Here, m scanning electrodes X1 to X
m is located crossing n signal electrodes Y1 to Yn and constitutes a plurality of matrix-shaped pixels.

The drive control device D includes a voltage forming circuit 30 supplied with a power supply voltage from an external power supply 20 and a power supply monitoring circuit 4.
0 is provided. In the present embodiment, the power supply voltage of the external power supply 20 is 13V. The voltage forming circuit 30 includes a scanning voltage forming unit 31, a luminance voltage forming unit 32, and a logic voltage forming unit 33. The scan voltage forming unit 31 receives a power supply voltage from the external power supply 20, forms a plurality of scan voltages, and outputs the plurality of scan voltages to the scan electrode drive circuit 70. Brightness voltage forming unit 3
2 is supplied with a power supply voltage from the external power supply 20, forms a plurality of voltages, and applies them to both signal electrode drive circuits 80 and 90.
The logic voltage forming unit 33 forms a plurality of logic voltages, and controls the control circuit 50 and the interface circuit 6.
0, scanning electrode driving circuit 70 and both signal electrode driving circuit 8
0 and 90 are output. In the present embodiment, the scanning voltage forming unit 31, the luminance voltage forming unit 32, and the logic voltage forming unit 33
Have a capacitive circuit configuration.

As shown in FIG. 2, the power supply monitoring circuit 40 includes a voltage detection circuit 40a and a transistor 40b. The voltage detection circuit 40a includes resistors 41 and 42 and a Zener diode 43 connected in series to each other. The Zener diode 43 is grounded at its anode through the resistor 42 and the resistor 41.

The voltage detection circuit 40a divides the power supply voltage of the external power supply 20 by means of a resistor 41 and a series circuit of a resistor 42 and a Zener diode 43.
A detection voltage is generated from the common terminal of Here, when the power supply voltage of the external power supply 20 is higher than 10 V, the detection voltage turns on the transistor 40b. External power supply 2
When the power supply voltage of 0 is 10 V or less, the Zener diode 43 cuts off the inflow current, the detection voltage decreases, and the transistor 40b is turned off. The Zener voltage of the Zener diode 43 is set to 10V.

The transistor 40b is turned on,
A first switching signal is output, and when the signal is turned off, a second switching signal is output. This means that the power supply monitoring circuit 40 monitors the power supply voltage of the external power supply 20 and transmits the state of the power supply voltage to the control circuit 50 by turning on and off the transistor 40b. The control circuit 50 receives a vertical synchronizing signal and a horizontal synchronizing signal as a synchronizing signal from an external circuit, and forms control signals for controlling the interface circuit 60, the scan electrode driving circuit 70, and both signal electrode driving circuits 80 and 90. Output to the circuit.

More specifically, the control circuit 50 includes a PLL circuit 51, a fixed frequency divider 52, and a variable frequency divider 53, as shown in FIG. The PLL circuit 51 receives a horizontal synchronization signal from an external circuit and sequentially generates a dot clock. The fixed frequency divider 52 receives each dot clock from the PLL circuit 51, divides the frequency of the dot clock by (1 / M), and outputs a fixed frequency divided signal at this frequency.

The variable frequency divider 53 includes a power supply monitoring circuit 4
In accordance with the first switching signal from the 0 transistor 40b, the frequency of the fixed frequency-divided signal from the fixed frequency divider 52 is divided by (1 / N), and scanning in the normal display mode is performed at the frequency. The clock CLK for the electrode drive circuit 70 is output to the scan electrode drive circuit 70, and the power supply monitoring circuit 4
In accordance with the second switching signal from the 0 transistor 40b, the frequency of the fixed frequency-divided signal from the fixed frequency divider 52 is divided by (1 / L), and the scanning in the power cutoff mode is performed at the divided frequency. The electrode driving circuit clock CLK is output to the scan electrode driving circuit 70. Here, in the present embodiment, N / L = 5 is set.

The control circuit 50 controls the control signals SI01, SI02 and DP in synchronization with the synchronization signal.
Is output to the scan electrode drive circuit 70, and an A / D conversion clock is output to the interface circuit 60 in synchronization with the synchronization signal. Here, the control signal SI01,
SI02 is for determining the state of the scanning voltage in the selection period, the holding period, and the erasing period. Control signal SI
01 and SI02 respectively correspond to a selection period when they are at a low level and a high level, a holding period when they are at a high level and a low level, and an erasing period when they are both at a low level.
Further, the control signal DP is for determining the polarity of the scanning voltage.

The interface circuit 60 digitally converts an image signal (consisting of R, G, and B image data) from an external circuit based on an A / D conversion clock from the control circuit 50, and converts the image signal into an image data signal. Output to the electrode driving circuits 80 and 90. Scan electrode drive circuit 70
Includes a data latch 71 of 3 × m bits, m level shifters L1 to Lm, and analog switch circuits S1 to Sm, as shown in FIG.

The data latch 71 is connected to the control circuit 5
0 to SI01 signal, SI02 signal, DP signal, CL
The K signal is input and m pieces of 3-bit data are output to the level shifters L1 to Lm. Each of the level shifters L1 to Lm outputs 3-bit data from the data latch 71 to each of the analog switch circuits S1 to Sm.

Each of the analog switch circuits S1 to Sm is composed of five analog switches. Each of the analog switch circuits S1 to Sm is connected to five analog switches based on the output of each level shifter L1 to Lm. The analog switch to be turned on is selected and turned on, whereby one of the plurality of voltages is output as a scan voltage from the scan voltage forming unit 31 of the voltage forming circuit 30 and line-sequentially applied to the scan electrodes X1 to Xm. Apply to scan.

Thus, the scan electrode driving circuit 70 controls the control signals SI01 and SI0 from the control circuit 50.
2. Based on the DP, image data is written to the scan electrodes with a scan voltage having a voltage waveform as shown in FIG. 5 during a selection period, and the write data is held by a hold voltage during a hold period. Erasing is performed by the erasing voltage during the erasing period.

In the normal display mode, the scan electrode drive circuit 70 takes in the SI01 signal and the SI02 signal from the control circuit 50 in synchronization with the normal display mode clock CLK from the control circuit 50.
A selection voltage based on the scanning voltage from the scanning voltage forming unit 31,
A holding voltage and an erasing voltage are sequentially applied to the scanning electrodes. In the power cutoff mode, scan electrode drive circuit 70 supplies power cutoff mode clock C from control circuit 50.
In synchronization with LK, the SI from the control circuit 50 is
The erasing voltage is sequentially applied to each scanning electrode by taking in the 01 signal and the SI02 signal. At this time, since the frequency of the clock CLK is higher than the frequency in the normal display mode as described above, the time required for applying the erase voltage to all the scan electrodes is longer than the time required for scanning all the scan electrodes in the normal display mode. Is also greatly reduced.

The signal electrode driving circuits 80 and 90 apply the voltage from the luminance voltage forming section 32 of the voltage forming circuit 30 under the control of the control circuit 50 in synchronization with the line sequential scanning of the scanning electrode driving circuit 70. The signal is output to each of the signal electrodes Y1 to Yn. Next, the operation of the present embodiment thus configured will be described with reference to FIG. First, the normal display mode will be described.

When the external power supply 20 generates a power supply voltage, the power supply voltage is applied to the voltage forming circuit 30 and the power supply monitoring circuit 40. Here, if the power supply voltage is higher than 10 V, the voltage detection circuit 40a in the power supply monitoring circuit 40 turns on the transistor 40b based on the detected voltage.
Therefore, the transistor 40b generates a first switching signal and outputs the first switching signal to the variable frequency divider 53 of the control circuit 50.

In the voltage forming circuit 30, the scanning voltage forming section 31 forms a plurality of voltages based on the power supply voltage and outputs the plurality of voltages to the scan electrode driving circuit 70, and the luminance voltage forming section 32 controls the power supply voltage. The logic voltage forming section 33 forms a plurality of logic voltages based on the power supply voltage and forms a plurality of logic voltages based on the power supply voltage. It outputs to the electrode drive circuit 70 and both signal electrode drive circuits 80 and 90.

Then, the control circuit 50 outputs an AD conversion clock to the interface circuit 60,
A control signal is output to scan electrode drive circuit 70. Further, in the control circuit 50, the PLL circuit 51 sequentially generates a dot clock based on the horizontal synchronization signal, and the fixed frequency divider 52 divides the frequency of the dot clock by (1 / M) to obtain a fixed frequency division. The variable frequency divider 53 frequency-divides the frequency of the fixed frequency-divided signal into (1 / N) based on the first switching signal of the transistor 40b, and generates a clock for the normal display mode at this frequency. CLK is output to scan electrode drive circuit 70. Further, the control circuit 50 outputs a control signal to both signal electrode drive circuits 80 and 90.

Accordingly, the scan electrode drive circuit 70 writes image data by applying a selection voltage to the scan electrodes during the selection period based on the control signal from the control circuit 50 and the clock CLK for the normal display mode. Data is held by a holding voltage during a holding period, and the held image data is erased by an erasing voltage during an erasing period.

Next, the power cutoff mode will be described.
The voltage forming circuit 30 and the power supply monitoring circuit 40
In the power supply monitoring circuit 40, the voltage detection circuit 40a turns off the transistor 40b according to the detection voltage, and the transistor 40b generates a second switching signal and outputs it to the variable frequency divider 53 of the control circuit 50. . This means that the control circuit 50 is set to the power cutoff mode.

Accordingly, the variable frequency divider 53 divides the frequency of the output of the fixed frequency divider 52 to (1 / L), and supplies the power cutoff mode clock CLK at this frequency to the scan electrode driving circuit. 70. Here, as described above, the frequency of the power cutoff mode clock CLK is increased five times as compared with that in the normal display mode. The control circuit 50 sets both the SI01 signal and the SI02 signal to low level (see FIG. 6). Accordingly, the scan electrode driving circuit 70 sequentially applies an erase voltage to the m scan electrodes. Thereby, the liquid crystal panel P is maintained at a constant voltage over all the scanning electrodes. After that, the generation of the logic voltage by the logic voltage forming unit 33 stops.

In this case, since the field frequency in the normal display mode is 60 Hz, it takes 17 msec to draw one screen of the liquid crystal panel P. However, in the power cutoff mode, the frequency of the clock CLK is changed to the normal display mode as described above. In this case, the voltage applied to all the scanning electrodes can be reduced to the erasing voltage in about 3 msec, thereby completing one screen quickly.

In such a time, the output of the scan voltage forming unit 31 and the output of the logic voltage forming unit 33 are kept in the capacitance of the voltage forming circuit 30 even after the interruption of the voltage forming circuit 30 from the external power supply 20. Since the voltage can be maintained under the circuit configuration, the voltage of the scan voltage forming unit 31 is cut off, and then the output of the logic voltage of the logic voltage forming unit 33 is stopped. That is,
The residual voltage is not applied from scan electrode drive circuit 70. Therefore, application of an abnormal voltage to the liquid crystal panel P and destruction of the scan electrode driving circuit 70 do not occur.

Further, since scan electrode driving circuit 70 outputs an erasing voltage which is the center voltage of the driving voltage of liquid crystal panel P, it is destroyed by formation of a short circuit (so-called latch-up) in scan electrode driving circuit 70. The operation of the liquid crystal display device can be safely stopped without fear of the occurrence.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an overall configuration of an embodiment of a matrix type liquid crystal display device according to the present invention.

FIG. 2 is a circuit configuration diagram of a power supply monitoring circuit of FIG. 1;

FIG. 3 is a schematic circuit configuration diagram of a control circuit of FIG. 1;

FIG. 4 is a specific circuit configuration diagram of the scan electrode driving circuit of FIG. 1;

FIG. 5 is a timing chart showing a driving waveform of each scanning electrode of FIG. 1 in relation to each signal of a control circuit.

FIG. 6 is a timing chart showing a state of each scanning electrode in a normal display mode and a power cutoff mode in relation to each signal of a control circuit.

[Explanation of symbols]

Reference Signs List 20: external power supply, 30: voltage forming circuit, 31: scanning voltage forming unit, 32: luminance voltage forming unit, 33: logic voltage forming unit, 40: power supply monitoring circuit, 40a: voltage detecting circuit, 4
0b: transistor, 50: control circuit, 53:
Variable frequency divider, 60: interface circuit, 70: scan electrode drive circuit, 80, 90: signal electrode drive circuit.

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 2H093 NA06 NA43 NC21 NC24 NC58 NC59 ND35 ND47 5C006 AA16 AA22 AF46 AF64 AF67 BB11 BF04 BF23 BF31 BF36 BF42 BF46 FA16 FA21 5C080 AA10 BB05 DD19 DD29 EE29 JJ03 JJ03 JJ03 JJ03 JJ03

Claims (5)

[Claims] 1. An m-number of scanning electrodes (X1 to Xm) and an n-number of signal electrodes (Y1) positioned so as to intersect these scanning electrodes via a liquid crystal and constitute a plurality of pixels in a matrix.
To Ym), an image data signal output means (60) for outputting image data as an image data signal, and a power supply voltage supplied from an external power supply (20) to form a plurality of voltages. A voltage forming means (31) for generating the plurality of voltages as a scanning voltage; and a scanning voltage input from the voltage forming means and scanning the m scanning electrodes while applying the scanning voltage to pixels on the scanned scanning electrodes. Scan electrode driving means (70) for writing image data and erasing the written image data
A signal electrode driving means (32, 8) operating to input a signal voltage to the n signal electrodes in accordance with the image data signal in synchronization with scanning by the scanning electrode driving means.
0, 90) and control means (5) for controlling the scanning electrode driving means so that the scanning electrode driving means selects the scanning voltage of the voltage forming means from the plurality of voltages in synchronization with the synchronization signal.
0), wherein the presence or absence of interruption of the external power supply is monitored in a matrix type liquid crystal display device in which a matrix display is performed by the plurality of pixels according to the operations of the scan electrode driving unit and the signal voltage driving unit. Power supply monitoring means (4
0), wherein the control means sets the voltage within the range of the power supply voltage as a fixed voltage when the monitoring state of the power supply monitoring means becomes a state corresponding to the interruption of the external power supply. Wherein the scan electrode driving means applies the fixed voltage to each of the scan electrodes. 2. The control unit according to claim 1, wherein when the monitoring state of the power supply monitoring unit becomes a state corresponding to the shut-down of the external power supply, the control unit sets any one of the plurality of voltages of the voltage forming unit as the fixed voltage and performs the scanning. 2. The matrix type liquid crystal display device according to claim 1, wherein control is performed so that the electrode driving means is selected. 3. The control unit according to claim 1, wherein the control unit controls the scan electrode driving unit to select a voltage close to a central value among the plurality of voltages as the fixed voltage. Matrix type liquid crystal display device. 4. The scanning electrode driving means scans the m scanning electrodes by line-sequential scanning, and the control means generates a control signal and a clock in synchronization with the synchronization signal. 2. The scanning electrode driving device according to claim 1, wherein the scanning electrode driving unit captures the control signal in synchronization with the clock, and sequentially applies the fixed voltage to the scanning electrodes scanned line-sequentially.
4. The matrix type liquid crystal display device according to any one of items 1 to 3. 5. The control unit according to claim 1, wherein the clock frequency when the monitoring state of the power supply monitoring unit becomes a state corresponding to the shut-down of the external power supply is determined by the monitoring state of the power supply monitoring unit. Frequency changing means (5) for changing the frequency to be higher than the frequency before the state corresponding to the cutoff.
3) wherein the scan electrode driving means sequentially applies the fixed voltage to the line-sequentially scanned scan electrodes in synchronization with the clock at a frequency changed by the frequency changing means. The matrix type liquid crystal display device according to claim 4.