JP2000299383A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor with an anti-fuse circuit which is easy for blow control. SOLUTION: When a high-voltage blow signal VG is applied to an anti-fuse 26, a blow-selective signal BADD with an activation potential of an inner power- supply voltage is entered in a bootstrap circuit 20 to control a high voltage. In the bootstrap circuit 20, the gate voltage of an n-channel MOS transistor 24 is boosted with a gate/drain capacity, when the blow selective signal BADD is activated, and the rise of the blow signal VG is made. Even if the amplitude of the blow selective signal is smaller than that of the blow signal VG, the high voltage can be applied to the anti-fuse 26.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an antifuse whose resistance value is reduced by being blown.

[0002]

2. Description of the Related Art Some semiconductor devices include a program circuit which can program an internal state setting later.

For example, in a memory integrated circuit such as a dynamic random access memory (DRAM), defective rows and columns are replaced with spare rows and columns in order to rescue defective chips on a wafer and improve product yield. In this case, a program circuit is provided for programming the address of a row and a column in which a defect is determined.

FIG. 16 is a circuit diagram showing a conventional configuration of a program circuit for programming an address.

Referring to FIG. 16, the program circuit includes a P-channel MOS transistor 151 and fuses 152.0 to 152. n, 152.0'-152. n '
And N channel MOS transistors 153.0 to 153.0
3. n, 153.0'-153. n '.

The P-channel MOS transistor 151 has
Power supply node receiving power supply potential Vcc and output node N51
And its gate receives the signal RP.

Fuse 152.0 and N-channel MO
S transistor 153.0 is provided corresponding to address signal A0, and is connected in series between output node N51 and a ground node receiving ground potential Vss. Fuse 15
2.0 'and N-channel MOS transistor 153.
0 'is provided corresponding to complementary signal / A0 of address signal A0, and is connected in series between output node N51 and the ground node. N-channel MOS transistor 153.
0, 153.0 'are connected to the address signal A, respectively.
0, / A0. Fuse 153.0-152.
n, 152.0'-152. n 'is formed of a polysilicon wiring or an aluminum wiring. Output node N51
Becomes the output signal φDA.

In such a program circuit, the fuse corresponding to the defective address is cut by a laser to program the defective address. When the input address matches the programmed defective address, the output node N51 and the ground node are rendered non-conductive, and the output node N51 which has been precharged in advance in response to the signal RP attaining the L level in advance. Holds the H level even when an address is input. Therefore,
A defective row or column is replaced with a spare row or column according to the level of signal φDA at the time of address input.

If the input address does not match the programmed defective address, the potential level of output node N51 precharged by signal RP goes low when the input address is input.

However, in the program circuit shown in FIG. 16, since a laser device is used to cut a fuse, there are problems such as high device cost and poor fuse cutting accuracy.

Therefore, a program circuit using an antifuse without using a laser device has been studied. The antifuse is an element having a high resistance before programming and changing its conduction state to a low resistance when an appropriate voltage is applied, as disclosed in Japanese Patent Application Laid-Open No. 7-37984. The antifuse has a capacitor type structure, for example, in which a thin insulating layer such as silicon dioxide is sandwiched between two conductive layers such as aluminum. Although it is a capacitor, that is, an open circuit as it is, when a high voltage is applied and blown, a conductive path is generated in the insulating layer, resulting in a resistance element having a resistance of about several kΩ.

FIG. 17 is a circuit diagram showing a conventional configuration of a fuse circuit including an antifuse and its blow circuit. Such a fuse circuit is disclosed, for example, in US Pat.
No. 6,186,862.

Referring to FIG. 17, this fuse circuit has
Anti-fuse 161, P-channel MOS transistors 162 to 164, and N-channel MOS transistor 1
65 to 169 and an inverter 170. MOS transistors 162, 164 and 165 are connected to power supply potential V
cc is connected in series between the power supply node receiving cc and node N65. The gate of P-channel MOS transistor 162 receives signal TRAS. The signal TRAS is a trigger signal that goes low during the address detection period and goes high during the other periods.

P channel MOS transistor 164 has
The gate is coupled to the ground potential and is always on. The channel length and channel width of P channel MOS transistor 164 are the same as those of P channel MOS transistor 1.
64 are set so that the conduction resistance value is about 300 kΩ. The gate of N-channel MOS transistor 165 receives signal DVCE. The signal DVCE is an enable signal for this fuse circuit, and
The potential level is set to one half of the power supply potential Vcc when blowing 61 and when detecting the address. The channel length and channel width of N-channel MOS transistor 165 are set such that the current driving capability of N-channel MOS transistor 165 is larger than that of P-channel MOS transistor 164.

Inverter 170 has an input node connected to connection node N64 between MOS transistors 164 and 165, and an output node connected to the gate of P-channel MOS transistor 163. In addition, the inverter 170
A signal FR, which is an output signal of the fuse circuit, is output from the output node of the fuse circuit. The signal FR becomes an input signal of a NOR type or NAND type address comparison circuit that compares an input address signal with a programmed address signal ADDR.

N channel MOS transistor 166 is
Connected between node N65 and a ground node receiving ground potential Vss, its gate receives reset signal RST.

The reset signal RST is set to the H level when setting the initial state of the fuse circuit. N-channel MOS transistors 167, 168 are connected in series between node N65 and a ground node, and each gate receives address signal ADDR and signal FR, respectively.

N channel MOS transistor 69 is connected between node N65 and one electrode of antifuse 161 and has its gate coupled to power supply potential Vcc.
The N-channel MOS transistor 169 is connected between the source and the gate or between the drain and the N-channel MOS transistors 165 to 167 when the antifuse 161 is blown.
A voltage higher than the withstand voltage of the gate oxide film is not applied between the gates so that the N-channel MOS transistors
167 is protected.

The other electrode of the antifuse 161 is connected to the terminal T61. The ground potential Vss is applied to the terminal T61 in the normal operation mode, and the antifuse 1
When blowing 61, a high voltage is applied.

Next, the operation of the fuse circuit will be described. When programming a defective address, first, the signal TRAS is set to the H level, the signal RST is raised to the H level, and the nodes N64 and N65 are set to the L level. Accordingly, signal FR rises to H level, and then signal RST
To the L level.

Next, the address signal ADDR corresponding to the defective address is set to the H level, and the antifuse 161 is set.
Are connected to N-channel MOS transistors 169, 1
Ground via 67 and 168. Next, the terminal T61
To apply a high voltage to blow the antifuse 161.

When the antifuse 161 is blown,
A current flows from the terminal T61 to the ground node via the antifuse 161 and the N-channel MOS transistors 69, 67, 68, and the node N64,
The potential of N65 increases. When the potential of node N64 rises above the logical threshold voltage of inverter 70, signal F
R goes to L level and N-channel MOS transistor 1
68 becomes non-conductive, interrupting the current path to the ground node. This prevents an excessive current from flowing through the circuit when the antifuse 61 is blown.

In the normal operation mode, the terminal T61
Is grounded, and the signal TRAS goes to L level. If the antifuse 161 is not blown, the node N6
4. N65 becomes H level and signal FR is latched at L level.

When the antifuse 161 is blown, the potential of the node N65 becomes the ground potential because the fuse 161 becomes a resistance element of several kΩ. N-channel MO
Since S transistor 165 has a higher current driving capability than P channel MOS transistor 164, node N64
Is lower than the logical threshold voltage of inverter 170, and signal FR attains H level. If there is an address detection circuit whose signal FR is at the H level when an address is input, it is determined that a defective address has been input, and the corresponding defective row and column are replaced with spare rows and columns. Is done.

[0025]

In the conventional fuse circuit, a control circuit for controlling an externally applied high voltage is additionally required, and there is a problem that the circuit scale becomes large. That is, normally, a high voltage is selectively applied to the anti-fuse 161 from among a plurality of anti-fuses, and the anti-fuse 161 is set. However, in the conventional fuse circuit, when the anti-fuse 161 is blown using a high voltage applied from the outside, the N-channel MOS transistor is required to selectively transmit the high voltage to the anti-fuse.
When a transistor is used, there is a problem that a voltage higher than this high voltage is required as a control voltage to be applied to its gate, so that a voltage generating circuit is required.

The antifuse when not blown is equivalent to a capacitor having a large capacitance value.
When a plurality of antifuses are selectively used, the potential of the node N64 precharged by the P-channel MOS transistor 162 drops when connected to any of the antifuses, which may cause a malfunction. There were also problems.

An object of the present invention is to provide a semiconductor device having a small circuit size and a small malfunction, and having an anti-fuse.

[0028]

According to a first aspect of the present invention, a semiconductor device includes: a first power supply node receiving a first power supply potential;
A first blow selection signal having a potential difference between the activation potential and the first power supply potential is a first predetermined value is activated, and a potential difference between the activation potential and the first power supply potential is a first predetermined value. A boost converter that outputs an internal potential corresponding to the activation potential of the blow signal in response to activation of a blow signal larger than the first blow node; a first internal node receiving an output of the boost converter;
A first antifuse connected at one end to the first power supply node, connected at the other end to the first internal node, and holding predetermined information with a resistance value between one end and the other end; The first antifuse is connected between one end and the other end when a voltage larger than a predetermined blow potential difference is applied between the one end and the other end in response to the internal potential being applied to the first internal node. Is maintained in a state where the resistance value is lower than the value before application.

The semiconductor device according to the second aspect is the first aspect.
In addition to the configuration of the semiconductor device described in 1 above, a second power supply potential having a first power supply potential difference between the first power supply potential and a first power supply potential is received to set predetermined information. An internal circuit that outputs a first blow selection signal, wherein the blow potential difference is greater than a first predetermined value, is equal to or less than a potential difference between an activation potential of the blow signal and the first power supply potential, and It is larger than the potential difference between the inactivation potential of the signal and the first power supply potential.

The semiconductor device according to the third aspect is the second aspect.
In addition to the configuration of the semiconductor device described in the above, the boost conversion circuit,
A first input node for receiving a first blow selection signal, a second input node for receiving a blow signal, an internal control node, and an internal control node provided between the first input node and the internal control node. While the potential difference between the potential of the internal power supply node and the first power supply node is smaller than the first predetermined value, the potential difference between the potential of the internal control node and the first power supply node is the first predetermined value. When the above condition is satisfied, the first connection circuit which becomes non-conductive and the first blow selection signal are activated, and when the potential of the internal control node becomes equal to the activation potential of the first blow selection signal, A second connection circuit that further increases the potential of the internal control node with the activation of the signal, and connects the second input node and the first internal node with a resistance value according to the potential of the internal control node; .

A semiconductor device according to a fourth aspect is the semiconductor device according to the second aspect.
In addition to the configuration of the semiconductor device described in the above, the boost conversion circuit,
A first input node receiving the first blow selection signal, a second input node receiving the blow signal, an internal control node, and a first input node provided between the first input node and the internal control node; A first field-effect transistor having a gate receiving a first fixed potential equal to the activation potential of the blow selection signal and smaller than the activation potential of the blow signal, a gate connected to the internal control node, and a second input node And a second field effect transistor provided between the first internal node and the first internal node.

According to a fifth aspect of the present invention, there is provided a semiconductor device according to the second aspect.
In addition to the configuration of the semiconductor device described in above, the semiconductor device further includes a resistance detection circuit that detects whether the resistance value of the first antifuse is lower than a predetermined resistance value and outputs a detection result signal.

The semiconductor device according to claim 6 is the same as the semiconductor device according to claim 5
In addition to the configuration of the semiconductor device described in the above, the resistance detection circuit,
It includes a first charging circuit for previously charging the first internal node to a predetermined potential, and an output circuit for outputting a detection result signal according to the potential of the first internal node.

According to a seventh aspect of the present invention, there is provided a semiconductor device according to the sixth aspect.
In addition to the configuration of the semiconductor device described in the above, the resistance detection circuit,
A second internal node, wherein the first charging circuit precharges the second internal node, and an output circuit outputs a signal corresponding to a potential of the second internal node, A second anti-fuse having one end connected to the third internal node, a first connection circuit connecting the second internal node and the first internal node in response to a first read selection signal, A second connection circuit connecting the third internal node and the first internal node in response to the second read selection signal, and connecting the first internal node to the first internal node before the first read selection signal is activated. A second charging circuit for charging the battery to a predetermined potential in advance.

The semiconductor device according to claim 8 is the semiconductor device according to claim 6.
In addition to the configuration of the semiconductor device described in the above, the resistance detection circuit,
A second internal node, wherein the first charging circuit precharges the second internal node, and an output circuit outputs a signal corresponding to a potential of the second internal node, A second antifuse having one end connected to the third internal node and the other end connected to the first power supply node;
A first connection circuit for connecting the second internal node and the first internal node in response to a read selection signal of the first and second internal nodes, and a third internal node and a first internal node in response to the second read selection signal. And a second connection circuit connecting the internal circuit and the internal circuit,
A regular memory array including a plurality of regular memory cells arranged in a matrix, a redundant memory array including a plurality of redundant memory cells arranged in a matrix, and first and second readouts according to an address signal. A decoding circuit for outputting a selection signal and selecting one of a normal memory array and a redundant memory array in accordance with an address signal and a detection result signal; Activated according to an address signal corresponding to a defective memory cell in the memory cell.

[0036]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1, this semiconductor device selects a predetermined operation mode based on externally applied signals / RAS and / CAS and generates a clock signal for controlling the entire semiconductor device 1. 12, a row and column address buffer 2 for generating row address signals RA0 to RAn and column address signals CA0 to CAn based on externally applied address signals A0 to An (n is an integer of 1 or more), and a row address signal Row decoder 3 includes a row decoder 3 that performs a decoding process in response to RA0 to RAn, and a column decoder 4 that performs a decoding process in response to column address signals CA0 to CAn.

The semiconductor device 1 further includes a gate circuit 13 for outputting a control signal in accordance with an externally applied signal / W and an output of the clock generation circuit 12;
, An input buffer 10 for receiving input data from data terminals DQ1 to DQm (m is a positive integer) and transmitting the data to data bus IOP in accordance with an output signal of gate signal 13 and an externally applied signal / OE. Data bus I
It includes an output buffer 11 for outputting OP data to data terminals DQ1 to DQm, and a memory mat 6 for designating a row and a column by column decoder 4 and row decoder 3 and transmitting / receiving data to / from data bus IOP.

The memory mat 6 includes a memory array 7 including a plurality of memory cells arranged in a matrix and each storing 1-bit data, and a memory cell at an address designated by the row decoder 3 and the column decoder 4. It includes a sense amplifier and an input / output control circuit 9 connected to one end of the bus IOP.

The memory array 7 includes a redundant memory array having a redundant memory cell for replacing a defective memory cell when the defective memory cell is found. Correspondingly, column decoder 4 includes a redundant column decoder 5 for designating a redundant memory array.

The semiconductor device 1 is further released from the standby state in response to the signal / RAS, receives the address signal predecoded by the column decoder, and receives the address of the defective memory cell set therein and the input address. Includes a redundancy judgment circuit for activating a redundant column decoder and inactivating an output of the column decoder when they match.

In the redundancy judgment circuit 14, a circuit including a fuse is used to set an address of a defective memory cell.

In FIG. 1, the configuration of the semiconductor memory device has been described as an example of the semiconductor device. However, the present invention is not limited to the semiconductor memory device but may be any other semiconductor device whose internal state needs to be set. It can also be used for devices.

FIG. 2 is a circuit diagram showing a configuration of the antifuse circuit used in the first embodiment.

Referring to FIG. 2, this anti-fuse circuit receives a blow signal VG for applying a high voltage when the anti-fuse is blown when blow select signal BADD is at an H level, and outputs a high voltage to node N2. Strap circuit 20 and antifuse 26 connected between node N2 and a ground node supplied with ground potential Vss are included.

The bootstrap circuit 20 has a gate coupled to the power supply potential Vcc and a source having a blow selection signal BAD
N-channel MOS transistor 22 provided with D and having a drain connected to node N1, and an N-channel MOS transistor 24 having a gate connected to node N1 and a blow signal VG provided to the drain and a source connected to node N2. .

When the potential at node N1 is charged to power supply potential Vcc via N-channel MOS transistor 22, a potential higher than power supply potential Vcc is input as blow signal VG. This is a circuit that performs boost conversion in which the potential of the node N1 is further boosted by the capacitance between the drain and source of the transistor 24, and as a result, a higher potential than the blow signal VG can be obtained as the gate potential of the N-channel MOS transistor 24.

Here, the operation will be described below with the potential of the node N2 as Vb. FIG. 3 is an operation waveform diagram for explaining a blowing operation of the anti-fuse circuit shown in FIG.

The blow operation of the anti-fuse is an operation of applying a high voltage to the anti-fuse to change from a capacitance to a resistance.

Referring to FIGS. 2 and 3, at time t1, blow select signal BADD rises from L level to H level. At this time, N channel MOS transistor 22
Has its gate coupled to power supply potential Vcc and is in a conductive state, and accordingly node N1 attains H level. As the potential of the node N1 becomes H level,
S transistor 24 also becomes conductive, and the potential level of blow signal VG is transmitted to node N2. At time t1, since the potential level of blow signal VG is at the L level, the potential of node N2 is also at the L level.

Next, at time t2, the blow signal VG
Rises to the voltage higher than the power supply potential Vcc (the voltage at which the antifuse causes blowing) at time t3.
, The potential of node N1 is boosted by the gate-drain capacitance of N-channel MOS transistor 24.

At this time, the potential of the node N1 is approximately (V
cc + VG). As a result, even if the node N2, that is, the source potential of the N-channel MOS transistor 24 rises to near VG, the voltage between the source and the gate of the N-channel MOS transistor 24 exceeds the threshold voltage. Keeps the conduction state.

Then, the potential level of blow signal VG is transmitted to node N2 as it is. Thus, the blow signal VG is applied to Vb, which is the voltage between both ends of the antifuse 26.
Is applied, a sufficiently high voltage is applied between both electrodes of the antifuse 26, and the fuse is blown.

FIG. 4 is an operation waveform diagram for explaining an operation when the antifuse circuit shown in FIG. 2 is not blown.

Referring to FIGS. 2 and 4, signal BADD is at L level.
When the blow signal VG rises and the high voltage is applied when the level is at the level, the potential of the node N1 is at the L level,
Since the channel MOS transistor 24 is off, the potential of the node N2 does not become high. Therefore, the antifuse 26 is not blown, and the state of the antifuse maintains the state of capacitance. As described above, in the first embodiment, since the anti-fuse circuit includes the self-boost circuit including N-channel MOS transistors 22 and 24, it supplies the high-voltage blow signal VG given from outside or generated inside. It is possible to control whether to blow the antifuse or not. Therefore, it is not necessary to separately provide a complicated circuit control circuit for controlling the high voltage, and the circuit scale can be reduced.

[Second Embodiment] FIG. 5 is a circuit diagram showing a second embodiment in which the anti-fuse circuit shown in FIG. 2 is applied to a redundancy judgment circuit.

Referring to FIG. 5, this redundancy judgment circuit is obtained by connecting a precharge circuit to the anti-fuse circuit shown in FIG.

This redundancy determining circuit receives a signal RAS, precharges node NPC and outputs a signal MIS corresponding to the potential of node NPC, and n antifuses connected together to node NPC. Circuits 52.0-52. n (n is a natural number of 2 or more).

The precharge circuit 40 has a power supply potential Vcc
A P-channel MOS transistor 34 connected between a power supply node supplied with a power supply node and a node NPC and receiving a signal RAS at a gate; a P-channel MOS transistor 36 connected between a power supply node and a node NPC and receiving a signal MIS at a gate; , Node NPC connected to the input node and outputting signal MIS.

The antifuse circuit 52.0 receives a blow signal VG for applying a high voltage when the antifuse is blown when the blow select signal BADD0 is at the H level, and outputs a high voltage to the node N2.
N-channel MOS transistor 32 connected between nodes NPC and N2 receiving read select signal ADD at its gate, and antifuse 26 connected between node N2 and a ground node supplied with ground potential Vss. And

Bootstrap circuit 20 has an N-channel MOS transistor 22 having a source receiving blow select signal BADD0, a drain connected to node N1 and a gate coupled to power supply potential Vcc, and a gate connected to node N1 and blowing to the drain. And an N-channel MOS transistor 24 receiving signal VG and having a source connected to node N2.

Antifuse circuit 52. n is the blow selection signal BA in the configuration of the anti-fuse circuit 52.0.
It receives blow select signal BADDn in place of DD0 and read select signal ADDn in place of read select signal ADD0, but the other parts have the same configuration and description thereof will not be repeated.

Blow selection signals BADD0 to BADDn
Is a signal generated internally in response to an address signal given at the time of blowing. Read selection signals ADD0-ADD
n is a signal generated internally in response to an address signal given during normal operation. Although not shown in the figure, a signal / B complementary to the blow selection signals BADD0 to BADDn is provided.
ADD0 // BADDn and read selection signal ADD0
Anti-fuse circuits are also provided for signals / ADD0 to / ADDn complementary to ADDn, respectively, and anti-fuse circuits 52.0 to 52. n and connected in parallel to the node NPC. In such a redundancy determination circuit, the blow selection signals BADD0 to BAD corresponding to the address to be set are provided.
DD0 and / BADD0 to / BADDn are given to perform blowing. In normal operation, blow select signals BADD0 to BADD0
BADD0 and / BADD0 to / BADDn are all inactive. When the address corresponds to the set address, only the unblown antifuse is connected to the node NPC, so that the potential of the node NPC holds the H level. Therefore, when the address signal is input, the signal MIS becomes L level, so that replacement is performed.

FIG. 6 is an operation waveform diagram for explaining the operation of the redundancy judgment circuit when the anti-fuse is blown in the redundancy judgment circuit of FIG.

Referring to FIG. 6, blow select signal BADD
A case where the antifuse 26 corresponding to 0 is blown will be described.

First, as an input signal, a blow selection signal BAD
D0 and the blow signal VG are both set to L level.

At time t1, blow selection signal BAD
D rises from L level to H level. Accordingly, the potential of node N1 rises from L level to H level.

Next, the potential level of the blow signal VG is raised to a predetermined high voltage. As described in the first embodiment, the potential of node N1 is accordingly raised, and N-channel MOS transistor 24 is completely turned on.
Then, the high voltage is completely applied to the node N2. Then, since a voltage exceeding the withstand voltage of the antifuse is applied to both ends of the antifuse, the antifuse changes from capacitance to resistance. At this time, the voltage Vb applied to N2 becomes equal to the high voltage applied to the blow signal VG.

Next, a case where the fuse is not blown in the second embodiment will be described. FIG. 7 is an operation waveform diagram for explaining the operation of the redundancy judgment circuit when the anti-fuse is not blown in the redundancy judgment circuit of FIG.

Referring to FIG. 7, in the initial state, L level is input to input signals BADD and VG. At time t1, a high voltage is applied as blow signal VG. However, since node N1 is at L level, N-channel MOS transistor 24 is off, and no high voltage is transmitted to node N2. Therefore, the antifuse is not blown.

As described above, when a plurality of antifuses provided corresponding to each internal address signal bit are blown, whether the antifuse is blown only by inputting the L level or the H level as the blow selection signal BADD is determined. You can choose not to. This blow selection signal BAD
The control of D is simple because the H level may be equal to the internal power supply potential Vcc.

Next, the read operation of the redundancy judgment circuit when the antifuse is not blown will be described.

FIG. 8 is a circuit diagram for explaining a circuit model when the antifuse is not blown.

Referring to FIG. 8, the redundancy judgment circuit precharges precharge node NPC in accordance with signal RAS, and outputs an output signal MIS in accordance with the potential of node NPC, The antifuse is blown according to BADD and VG, and the signal ADD0 is
And an anti-fuse circuit 52 for discharging the electric charge charged to the node NPC in response to

Precharge circuit 40 is the same as the circuit shown in FIG. 5, and description thereof will not be repeated. Antifuse circuit 52 has the same configuration as antifuse circuit 52.0 shown in FIG. 5, and therefore description thereof will not be repeated.

Here, the antifuse 26 is not blown, that is, the capacitor 26C.

FIG. 9 is an operation waveform diagram for describing a read operation when the fuse is not blown.

Referring to FIGS. 8 and 9, when performing a read operation, blow select signal BADD and blow signal V
G is always at the L level.

At time t1, signal RAS is set to the H level to change P channel MOS transistor 34 from the conductive state to the non-conductive state. At this time, the node NPC is at H
Level, and the output of the inverter 38 is at the L level. Therefore, P-channel MOS transistor 36 is rendered conductive, and node NPC remains precharged.

Next, at time t2, an address signal for selecting a memory cell is input. When read select signal ADD corresponding to the address signal is at L level, N-channel MOS transistor 32 is off, and node NPC holds the precharged state and is at H level. When address signal ADD is at H level, N-channel MOS transistor 32 is turned on, but antifuse 26 is not blown and is equivalent to a capacitor, so that there is no conduction path to the ground node. Therefore, although the potential is slightly lowered by being coupled to the capacitor, the level is restored again by the operation of P-channel MOS transistor 36, and node PNC maintains the precharged state and remains at the H level. Therefore, in each case, signal MIS is at H level, and it is determined that the input address does not match the defective address.

Next, the operation when the antifuse is blown will be described. FIG. 10 is a circuit diagram for explaining a circuit model when an antifuse is blown.

Referring to FIG. 10, this redundancy judgment circuit comprises:
A resistor 26R is included in place of the capacitor 26C of the redundancy judgment circuit shown in FIG. This indicates that the fuse was blown and changed to a resistance. The other configuration is the same as that of the redundancy judgment circuit shown in FIG. 8, and therefore description thereof will not be repeated.

FIG. 11 is an operation waveform diagram for describing a read operation of the redundancy judgment circuit when the antifuse is blown.

Referring to FIGS. 10 and 11, when performing a read operation, blow select signal BADD and blow signal VG are used.
Are set to the L level. Next, at time t1,
Signal RAS rises to the H level. Then, at time t2
Select signal AD corresponding to the input address signal
D rises from L level to H level. At this time, N
Channel MOS transistor 32 is rendered conductive. The node NPC is connected to the node N2. Since the node N2 is connected to the ground node by the resistor 26R,
Electric charges are discharged through this path. Therefore, the potential of node NPC drops to the ground level together with the potential of node N2. Accordingly, at time t3, output signal MIS which is the determination output rises to H level, and it is determined that the antifuse is blown.

As described above, in the second embodiment, an anti-fuse circuit having a self-boost circuit is applied to a redundancy judgment circuit. Therefore, it is possible to easily set an address corresponding to a defective memory cell to be replaced with a spare memory cell in redundant memory array 8 shown in FIG.

[Third Embodiment] In the case of the redundancy judgment circuit of the second embodiment, when the capacitance value of the antifuse 26C is large, the potential of the node NPC may be reduced and a malfunction may occur.

FIG. 12 is a circuit diagram showing a configuration of a redundancy judgment circuit used in the semiconductor device of the third embodiment.

Referring to FIG. 12, this redundancy judgment circuit includes:
The configuration of the redundancy determination circuit shown in FIG. 8 includes an anti-fuse circuit 52A instead of anti-fuse circuit 52. Anti-fuse circuit 52A is different from the configuration shown in FIG. 8 in that charging circuit 62 is connected to node N2 in the configuration of anti-fuse circuit 52 shown in FIG.

Charging circuit 62 includes a P-channel MOS transistor 64 and an N-channel MOS transistor 66 connected in series between a power supply node receiving power supply potential Vcc and node N2. The gate of P channel MOS transistor 64 receives signal / RAS. N-channel MO
The gate of S transistor 66 receives selection signal / ADD.

The other configuration is the same as that shown in FIG. 8, and description thereof will not be repeated. FIG. 13 is an operation waveform diagram for explaining the operation of the redundancy judgment circuit shown in FIG.

Referring to FIGS. 12 and 13, when a read operation is performed, blow select signal BADD, blow signal VG
Is set to L level.

When signal RAS rises to H level at time t1, P channel MOS transistor 34 is turned off, P channel MOS transistor 36 is turned on, and the potential of node NPC is held at H level.

At time t2, when read selection signal ADD corresponding to the input address signal is input, N-channel MOS transistor 32 is rendered conductive and charging circuit 6
If 2 does not exist, the potential of the node NPC may temporarily fall to the L level to charge the capacitor 26C, which is an antifuse, as shown by the waveform A1. Accordingly, the output of inverter 38 is inverted, and a malfunction occurs as shown by waveform A2, and signal MIS goes high. This is because, in the case of the circuit shown in FIG.
Since the node N2 is in a floating state before the read selection signal ADD is activated, it is highly likely that the read selection signal ADD is at the L level before activation.

When charging circuit 62 is present, signal RAS is at H level and read select signal ADD is at L level from time t1 to t2, so that P channel MOS transistor 64 and N channel MOS transistor Since 66 is in a conductive state, the node N2 is being charged. Therefore, after the time t2, the potential of the node NPC does not decrease as shown in the waveform B1, and the signal MIS operates normally, and thus maintains the L level state as shown in the waveform B2.

When the anti-fuse is blown, a current flows through the fuse.
It is not a problem because the time is short between t3 and t4.

As described above, in the third embodiment, since the anti-fuse circuit is further provided with the charging circuit, malfunctions are less likely to occur and reliability can be further improved.

[Embodiment 4] FIG. 14 shows Embodiment 4 of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a redundancy judgment circuit used in the semiconductor device of FIG.

Referring to FIG. 14, this redundancy judgment circuit comprises:
The configuration of the redundancy judgment circuit shown in FIG. 12 differs from the redundancy judgment circuit shown in FIG. 12 in that a charging circuit 72 is included instead of charging circuit 62.

Charging circuit 72 includes a P-channel MOS transistor 74 having a source and a back gate connected to a power supply node and a drain and a gate connected, and a gate connected between P-channel MOS transistor 74 and node N2. And a P-channel MOS transistor 76 receiving signal ADD.

The other configuration is the same as that of the redundancy judgment circuit shown in FIG. 12, and the description will not be repeated.

With such a configuration, node N2 is charged except when read select signal ADD corresponding to the address signal attains H level.

FIG. 15 is an operation waveform diagram for describing a read operation when the antifuse of the redundancy judgment circuit shown in FIG. 14 is not blown.

Referring to FIGS. 14 and 15, in the read operation, signals BADD and VG are at L level. At time t1, signal RAS rises, and subsequently at time t2 read select signal ADD rises. When the charging circuit 72 is not provided, the potential of the node NPC once falls from the time t2 as shown by the waveform A11 to charge the capacitor 26C which is an antifuse, and the signal MIS is accordingly supplied.
There is a possibility that a malfunction may occur as shown by the waveform A12.

By the presence of charging circuit 72, the potential of node N2 has been charged to a constant potential until time t2. Therefore, at time t2, N channel M
Even when the OS transistor 32 is turned on, the potential of the node NPC does not decrease as shown by the waveform B11. Therefore, as shown in the waveform B12, the output signal MIS does not malfunction. When the antifuse is blown, current flows through the fuse. However, the size of the P-channel MOS transistors 74 and 76 in the charging circuit 72 is reduced according to the length of the charging period to increase the resistance to some extent. This is not a problem.

As described above, also in the semiconductor device of the fourth embodiment, the reliability against malfunction can be improved.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0108]

According to the semiconductor device of the present invention, it is not necessary to provide a complicated circuit control circuit for controlling a high voltage, and the circuit scale can be reduced.

According to the semiconductor device of the fifth and sixth aspects, in addition to the effect of the semiconductor device of the first aspect, an output signal can be obtained by reading the resistance value of the anti-fuse circuit.

The semiconductor device according to the seventh aspect is the first aspect.
In addition to the effects of the semiconductor device described in (1), since the anti-fuse circuit is further provided with a charging circuit, malfunctions are less likely to occur and reliability can be further improved.

In the semiconductor device according to the eighth aspect, an address corresponding to a defective memory cell to be replaced with a spare memory cell can be easily set.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing a configuration of an anti-fuse circuit used in the first embodiment.

FIG. 3 is an operation waveform diagram for explaining a blowing operation of the anti-fuse circuit shown in FIG. 2;

FIG. 4 is an operation waveform diagram for describing an operation when blowing of the anti-fuse circuit shown in FIG. 2 is not performed.

FIG. 5 is a circuit diagram showing a second embodiment in which the anti-fuse circuit shown in FIG. 2 is applied to a redundancy judgment circuit.

6 is an operation waveform diagram for explaining an operation of the redundancy judgment circuit when an antifuse is blown in the redundancy judgment circuit of FIG. 5;

7 is an operation waveform diagram for explaining the operation of the redundancy judgment circuit in the case where the anti-fuse is not blown in the redundancy judgment circuit of FIG. 5;

FIG. 8 is a circuit diagram for explaining a circuit model when an antifuse is not blown.

FIG. 9 is an operation waveform diagram for describing a read operation when a fuse is not blown.

FIG. 10 is a circuit diagram for explaining a circuit model when an antifuse is blown.

FIG. 11 is an operation waveform diagram for describing a read operation of the redundancy judgment circuit when the antifuse is blown.

FIG. 12 is a circuit diagram showing a configuration of a redundancy judgment circuit used in the semiconductor device according to the third embodiment;

FIG. 13 is an operation waveform diagram for explaining the operation of the redundancy judgment circuit shown in FIG.

FIG. 14 is a circuit diagram showing a configuration of a redundancy judgment circuit used in the semiconductor device of the fourth embodiment;

FIG. 15 is an operation waveform diagram for describing a read operation when the antifuse of the redundancy judgment circuit shown in FIG. 14 is not blown;

FIG. 16 is a circuit diagram showing a conventional configuration of a program circuit for programming an address.

FIG. 17 is a circuit diagram showing a conventional configuration of a fuse circuit including an antifuse and its blow circuit.

[Explanation of symbols]

1 semiconductor device, 2 row and column address buffers, 3
Row decoder, 4 column decoder, 5 redundant column decoder,
Reference Signs List 6 memory mat, 7 memory array, 8 redundant memory array, 9 sense amplifier + input / output control circuit, 10 input buffer, 11 output buffer, 12 clock generation circuit, 13 gate circuit, 14 redundancy judgment circuit, 20
Bootstrap circuit, 22, 24, 32, 66 N-channel MOS transistor, 26 antifuse, 2
6C capacitor, 26R resistor, 34, 36, 64,
74, 76 P-channel MOS transistor, 40 precharge circuit, 52, 52A, 52B antifuse circuit, 72, 74 charging circuit.

Continued on the front page (72) Inventor Shigeki Tomishima 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5F038 AR19 AV01 AV09 AV14 BG03 DF05 DF16 5F064 BB07 BB14 BB16 BB26 CC12 CC22 CC23 FF02 FF05 FF28 FF46

Claims (8)

[Claims] A first power supply node receiving a first power supply potential; a first blow selection signal having a potential difference between an activation potential and the first power supply potential being a first predetermined value is activated; And in response to the activation of the blow signal in which the potential difference between the activation potential and the first power supply potential is larger than the first predetermined value,
A boost converter for outputting an internal potential corresponding to the activation potential of the blow signal; a first internal node receiving an output of the boost converter; one end connected to the first power supply node; A first antifuse connected to the first internal node and holding predetermined information by a resistance value between the one end and the other end, wherein the first antifuse has an internal potential When a voltage larger than a predetermined blow potential difference is applied between the one end and the other end in response to being given to the first internal node, a resistance value between the one end and the other end is increased. A semiconductor device that maintains a state lower than a value before application. A second power supply potential having a potential difference from the first power supply potential, the second power supply potential being the first predetermined value, and the first power supply potential, and a second power supply for setting the predetermined information; An internal circuit that outputs one blow selection signal, wherein the blow potential difference is greater than the first predetermined value and is equal to or less than a potential difference between an activation potential of the blow signal and the first power supply potential; 2. The semiconductor device according to claim 1, wherein the potential difference is larger than a potential difference between a deactivation potential of the blow signal and the first power supply potential. 3. The boost conversion circuit includes: a first input node that receives the first blow selection signal; a second input node that receives the blow signal; an internal control node; and the first input node. Between the internal control node and the internal control node, and while the potential difference between the potential of the internal control node and the first power supply node is smaller than the first predetermined value, the conductive state is established. A first connection circuit that is turned off when a potential difference between the potential of the first power supply node and the potential of the first power supply node is equal to or greater than the first predetermined value; When the potential of the internal control node becomes equal to the activation potential of the first blow selection signal, the potential of the internal control node is further increased in accordance with the activation of the blow signal, and the potential of the internal control node is increased according to the potential of the internal control node. Habit And a second connection circuit for connecting said second input node and said first internal node with the value, the semiconductor device according to claim 2. 4. The boost conversion circuit, wherein: a first input node receiving the first blow selection signal; a second input node receiving the blow signal; an internal control node; and the first input node And a first field effect provided between the gate and the internal control node, the gate receiving a first fixed potential equal to the activation potential of the first blow selection signal and smaller than the activation potential of the blow signal. 3. The semiconductor device according to claim 2, further comprising: a transistor; and a second field-effect transistor having a gate connected to the internal control node and provided between the second input node and the first internal node. 4. . 5. The semiconductor device according to claim 2, further comprising a resistance detection circuit that detects whether a resistance value of the first antifuse is lower than a predetermined resistance value and outputs a detection result signal.
3. The semiconductor device according to claim 1. 6. A resistance detection circuit, comprising: a first charging circuit for previously charging the first internal node to a predetermined potential; and a detection result signal according to a potential of the first internal node. 6. The semiconductor device according to claim 5, further comprising: an output circuit for outputting. 7. The resistance detection circuit further includes a second internal node, the first charging circuit precharges the second internal node, and the output circuit includes a second internal node. A third internal node, a second antifuse having one end connected to the third internal node, and a second internal node in response to a first read selection signal. A first connection circuit for connecting a node to the first internal node; a second connection circuit for connecting the third internal node to the first internal node in response to a second read selection signal 7. The semiconductor device according to claim 6, further comprising: a second charging circuit that charges said first internal node to said predetermined potential before said first read selection signal is activated. 8. The resistance detection circuit further includes a second internal node, the first charging circuit pre-charges the second internal node, and the output circuit includes a second internal node. A third anti-fuse having one end connected to the third internal node and the other end connected to the first power supply node; and A first connection circuit for connecting the second internal node and the first internal node in response to a first read selection signal; a third connection node and a third connection node in response to a second read selection signal; A second connection circuit connecting the first internal node to the first internal node, the internal circuit comprising: a regular memory array including a plurality of regular memory cells arranged in a matrix; and a plurality of regular memories arranged in a matrix. A redundant memory array including the redundant memory cells of Outputting the first and second read selection signals in response to a dress signal, and selecting one of the normal memory array and the redundant memory array in accordance with the address signal and the detection result signal 7. The semiconductor device according to claim 6, wherein said first blow select signal is activated in response to an address signal corresponding to a defective memory cell in said memory cell.