JP2000299377A - Multilayer wiring and forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the opening diameter of a contact hole from diminishing, even when errors in alignment are caused between the contact hole and a wiring groove in a dual damascene method. SOLUTION: A first insulating film 21, with a first opening part (P) for exposing an upper face of a first wiring 30, is formed as an upper layer of the first wiring 30 on a substrate 10. A second insulating film 22 having etching selective ratio with respect to the first insulating film 21 is formed in the first opening part (P) and on the first insulating film 21. A second opening part (T), having a width smaller than that of the first opening part (P) and formed in a groove shape, in which a pair of counterposed inner wall faces both pass the upper part of the first opening part (P), and a third opening part (CH) jointed with the second opening part (T), having substantially the same width as the second opening part (T) and exposing at least the upper face of the first wiring 30 are formed in the second insulating film 22. A plug 32 is embedded in the third opening part (CH), and a second wiring 32b is embedded in the second opening (T).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring and a method of forming the same, and more particularly to a multilayer wiring connecting a plurality of wirings by contacts and a method of forming the same.

[0002]

2. Description of the Related Art In semiconductor devices such as VLSIs in recent years, demands for miniaturization and high speed operation are increasing. For example, MOS (Metal-Oxide-Semiconductor)
The gate width of the gate electrode in a transistor, DRA
The area occupied by a capacitor in an M (Dynamic Random Access Memory) or the like is becoming increasingly smaller. On the other hand, there is also a demand for fine processing such as a multilayer wiring structure in the wiring section as well as a reduction in the capacitance between wirings, a reduction in wiring resistance and an improvement in wiring reliability.

In order to reduce the above-mentioned capacitance between wirings, as a material of an interlayer insulating film formed between wirings, the relative dielectric constant is lower than that of conventionally used silicon oxide (relative dielectric constant: 4.3). Research is being conducted on a method of forming the insulating layer using an insulating material. Examples of the insulating material having a lower relative dielectric constant than silicon oxide include organic materials such as polyarylether and SiO.
It is roughly classified into inorganic materials such as F.

On the other hand, in order to reduce the wiring resistance and improve the reliability of the wiring, a copper wiring having a lower resistance and an excellent electromigration resistance than an aluminum alloy based wiring which has been widely used in the past has been required. Attracting attention.

[0005] As a method of forming a copper wiring, a method of forming by a trench wiring method called a damascene process is considered to be promising, since dry etching of copper is generally not easy. Also, in conventional aluminum alloy-based wiring, it becomes difficult to etch fine aluminum alloy wiring as the wiring becomes finer,
It is also difficult to embed the insulating material between the narrow wirings, and it is considered that the formation by the groove wiring method is advantageous.

As the above-mentioned trench wiring method, a so-called single damascene method in which a connection plug buried in a contact hole and a wiring buried in a groove are separately formed, or a contact hole and a wiring groove are previously opened. A so-called dual damascene method has been studied in which a connection plug buried in a contact hole and a wiring buried in a groove are simultaneously formed by burying them simultaneously in a wiring material. Usually, the dual damascene method is advantageous in that the number of steps is smaller than the single damascene method.

Various methods have been proposed as a method of forming a connection plug buried in a contact hole and a wiring buried in a trench by the dual damascene method. The simplest method is to open a groove for wiring after opening a contact hole, and to simultaneously fill the formed contact hole and the groove for wiring with a wiring material. Also, the order of the step of opening a contact hole and the step of opening a groove for wiring can be interchanged.

However, in any of the above-mentioned methods, a wiring groove to be formed later is formed in an upper layer of an insulating film having a deep step such as a contact hole or a wiring groove formed earlier. Alternatively, it is necessary to form a resist film serving as a mask for forming a contact hole or the like. For this reason, problems such as a defective shape of the pattern of the formed resist film are likely to occur.

One of the methods for solving the above problem is as follows.
A method has been developed in which an etching stopper to which an opening pattern of a contact hole is transferred in advance is buried, and a contact hole is opened in a self-aligned manner by using the etching stopper when forming a wiring groove in a later process. .

The above method will be described below with reference to the drawings. 8A is a plan view of a multilayer wiring portion of a semiconductor device formed by the above method, FIG. 8B is a cross-sectional view taken along line XX ′ in FIG. 8A, and FIG. It is sectional drawing in YY 'of a middle. A first wiring 30 made of an aluminum alloy or the like is formed on the substrate 10,
A first interlayer insulating film 20 made of, for example, silicon oxide is formed so as to cover the upper layer, and a second interlayer insulating film 21 made of, for example, silicon nitride and serving as an etching stopper is formed thereover. Then, a third interlayer insulating film 22 made of, for example, silicon oxide is formed. A contact hole CH penetrating the first interlayer insulating film 20 and the second interlayer insulating film 21 and reaching the first wiring 30 is opened, and a wiring groove T is formed in the third interlayer insulating film. It is opened in communication with the hole CH. An adhesion layer 31 made of, for example, a laminate of titanium / titanium nitride or the like is formed so as to cover the inner wall of the contact hole CH and the trench T for wiring.
The plug 32 a made of, for example, tungsten and the second wiring 3 are buried in the contact hole CH and the wiring trench T.
2b are integrally formed.

A method for forming a multilayer wiring in the above semiconductor device will be described. First, FIG.
FIG. 8A is a cross-sectional view taken along line XX ′, and FIG.
(Corresponding to a cross-sectional view taken along line YY ′ in (a)) of FIG.
The wiring 30 is formed. Next, for example, CVD (Chemical V
A first interlayer insulating film 20 is formed by covering the first wiring 30 and depositing silicon oxide on the entire surface by an apor deposition method. Next, the first interlayer insulating film 2 is formed by, for example, a CVD method.
0, silicon nitride is deposited on the entire surface, and a second interlayer insulating film 21 is formed.

Next, FIG. 10 (a) is a cross-sectional view taken along line XX 'in FIG. 8 (a), and FIG.
As shown in a cross-sectional view) in the Y ', the upper layer of the second interlayer insulating film 21, by a photolithography process, a resist film R1 of the opening pattern P _CH contact hole. Next, etched, such as RIE (reactive ion etching) using the resist film R1 as a mask, to transfer the aperture pattern P _CH contact hole in the second interlayer insulating film 21.

Next, FIG. 11 (a) is a sectional view taken along line XX 'in FIG. 8 (a), and FIG.
(Corresponding to the cross-sectional view at Y ′), after removing the resist film R1 by ashing or the like, silicon oxide is deposited on the entire surface of the second interlayer insulating film 21 by, for example, a CVD method, An insulating film 22 is formed.

Next, FIG. 12A is a sectional view taken along line XX 'in FIG. 8A, and FIG.
(Corresponding to the cross-sectional view taken along the line Y ′), a resist film R of the opening pattern _PT of the second wiring groove is formed on the third interlayer insulating film 22 by a photolithography process.
Form 2

Next, FIG. 13A is a cross-sectional view taken along line XX ′ in FIG. 8A, and FIG.
(Corresponding to the cross-sectional view at Y ′), etching such as RIE (reactive ion etching) is performed using the resist film R2 as a mask to form a trench T for a second wiring in the third interlayer insulating film 22. Then, a contact hole CH communicating with the trench T for the second wiring is opened in a self-aligned manner with the second interlayer insulating film 21 as an etching stopper by further continuously performing an etching process.

In the subsequent steps, for example, the contact hole CH and the inner wall of the trench T for wiring are covered, and titanium / titanium nitride is laminated by, for example, a sputtering method to form an adhesion layer 31. CVD
A conductive material such as tungsten is deposited by filling the contact hole CH and the trench T for wiring by a method, and then, for example, CMP (Chemical Mechanical Polishing).
The conductive material such as titanium / titanium nitride and tungsten deposited outside the trench T for the second wiring is removed by a method or etchback by dry etching, and the plug 32a and the second wiring 32b are integrally formed. Above,
A semiconductor device having the multilayer wiring shown in FIG. 8 can be formed.

[0017]

However, according to the above-described method for forming a multilayer wiring, as shown in FIG. 14A, the opening pattern P of the second wiring groove is formed on the third interlayer insulating film 22. in the step of forming a resist film R2 _T, then if misalignment occurs, the sidewall of the opening of the aperture pattern P _T of the grooves for the second wiring had entered the inside of the opening pattern P _CH contact hole, FIG. 14 (b)
As shown in, when a contact hole communicating with the groove and that of a second wiring, a problem that the opening diameter phi _CH of the contact hole becomes smaller occurs. When the opening diameter of the contact hole is reduced as described above, the substantial aspect ratio of the contact hole increases, and it becomes difficult to embed a wiring material in the contact hole, causing problems such as poor connection. .

In recent years, with the miniaturization of the wiring, the margin for matching the opening diameter of the contact hole and the width of the groove for the wiring has been further reduced, or the margin for the opening of the contact hole has been completely eliminated. And the width of the wiring groove tends to be equal, and the problem of misalignment described above is becoming more and more serious.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and accordingly, an object of the present invention is to provide a dual damascene method for simultaneously forming a contact connection and a trench wiring.
An object of the present invention is to provide a multilayer wiring and a method for forming the same, which can prevent the opening diameter of the contact hole from being reduced due to misalignment between the contact hole and the wiring groove.

[0020]

In order to achieve the above object, a multilayer wiring according to the present invention comprises a substrate, a first wiring formed on the substrate, and a first wiring formed on the first wiring. An insulating film, a first opening formed in the first insulating film so as to expose at least an upper surface of the first wiring, and an insulating film having an etching selectivity with respect to at least a surface portion of the first insulating film. A second insulating film formed in the first opening and an upper layer of the first insulating film, and formed in the second insulating film and having a width smaller than the width of the first opening. A pair of opposed inner wall surfaces both of which pass above the region of the first opening;
A third opening communicating with the opening, having substantially the same width as the second opening, and formed on the second insulating film in the first opening so as to expose at least an upper surface of the first wiring; An opening, a plug embedded in the third opening, and a second wiring embedded in the second opening and integrated with the plug;

In the above-described multilayer wiring according to the present invention, preferably, the second opening is a groove-shaped opening formed in the second insulating film so as to expose an upper surface of the first insulating film. is there.

In the above-described multilayer wiring according to the present invention, preferably, at least a portion of the first insulating film having a thickness corresponding to the depth of the first opening is formed of foamed silicon oxide (nanoporous silica), silicon oxide, It is an insulating film containing either silicon-containing fluororesin or carbon-containing silicon oxide.

In the above-mentioned multilayer wiring according to the present invention, preferably, the second insulating film is made of a polyarylether resin, a cyclic fluororesin / siloxane copolymer, a fluorinated polyarylether resin, or polypentafluorostyrene. An insulating film containing any of a series resin, a polytetrafluoroethylene series resin, a fluorinated polyimide resin, a polyfluorinated naphthalene series resin, or a polyimide resin.

In the above-described multilayer wiring of the present invention, preferably, the plug and the second wiring are formed of a conductive material containing copper or aluminum.

In the above-described multilayer wiring according to the present invention, preferably, a third insulating film is further formed on the second insulating film with an insulating material having an etching selectivity with respect to the second insulating film. And the second opening is formed through the third insulating film. More preferably, the third
The insulating film is foamed silicon oxide (nanoporous silica),
The insulating film contains any of silicon oxide, silicon-containing fluororesin, and carbon-containing silicon oxide.

In the above-mentioned multilayer wiring according to the present invention, preferably, the first insulating film has substantially the same height as the upper surface of the first wiring, and the lower layer covers the side surface of the first wiring. A stacked insulating film of a first insulating film and an upper first insulating film formed on an upper layer of the first wiring and the lower first insulating film to cover an upper surface of the first wiring; The insulating film has an etching selectivity with respect to the upper first insulating film.

According to the above-described multilayer wiring of the present invention, the second insulating film is formed of an insulating material having an etching selectivity with respect to the surface portion of the first insulating film in which the first opening is formed. The pair of inner wall surfaces of the groove-like second opening (groove for wiring) formed in the second insulating film both pass over the region of the first opening, and the second opening and the second opening substantially overlap each other. Since the third openings (contact holes) are formed so as to communicate with each other with the same width, even if misalignment of a layer serving as a mask for forming the second openings occurs, the opening diameter of the contact holes is reduced. It can be prevented from becoming smaller.

In order to achieve the above object, a method for forming a multilayer wiring according to the present invention comprises the steps of forming a first wiring on a substrate, and forming a first insulating film covering the first wiring. Forming a first opening in the first insulating film to expose at least an upper surface of the first wiring;
Forming a second insulating film inside the opening and on the first insulating film using an insulating material having an etching selectivity with respect to at least a surface portion of the first insulating film; Forming a groove-shaped second opening in the film having a width smaller than the width of the first opening and having a pair of opposed inner wall surfaces both passing above the region of the first opening; And a second insulating film in the first opening that communicates with the second opening, has substantially the same width as the second opening, and exposes at least an upper surface of the first wiring. 3
Forming an opening, filling the third opening with a conductive material to form a plug, and filling the second opening with the conductive material to form a second wiring integrally with the plug. Forming.

In the method for forming a multilayer wiring according to the present invention, preferably, in the step of forming the first opening, the misalignment of a layer serving as a mask in the step of opening the second opening is maximized. The second groove-shaped second
The pair of inner walls facing each other in the opening are formed so as to be arranged so as to pass above the region of the first opening.

In the method of forming a multilayer wiring according to the present invention, preferably, in the step of forming the second opening, the upper surface of the first insulating film is exposed using the first insulating film as an etching stopper. Thus, a groove is formed in the second insulating film.

In the method of forming a multilayer wiring according to the present invention, preferably, at least a portion of the first insulating film having a thickness corresponding to a depth of the first opening is formed by using expanded silicon oxide (nanoporous silica). It is formed of an insulating film containing any of silicon oxide, silicon-containing fluororesin, and carbon-containing silicon oxide.

In the method of forming a multilayer wiring according to the present invention, preferably, the second insulating film is formed of a polyaryl ether resin, a cyclic fluororesin / siloxane copolymer, a fluorinated polyaryl ether resin, It is formed of an insulating film containing any of a pentafluorostyrene-based resin, a polytetrafluoroethylene-based resin, a fluorinated polyimide resin, a polyfluorinated naphthalene-based resin, and a polyimide resin.

In the above-described method for forming a multilayer wiring according to the present invention, preferably, the plug and the second wiring are formed of a conductive material containing copper or aluminum.

Preferably, in the method of forming a multilayer wiring according to the present invention, after the step of forming the second insulating film,
Prior to the step of forming an opening, the method further comprises the step of forming a third insulating film on the second insulating film using an insulating material having an etching selectivity with respect to the second insulating film;
In the step of forming the second opening, the second opening is formed to penetrate the third insulating film. More preferably, the third insulating film is formed of an insulating film containing any of foamed silicon oxide (nanoporous silica), silicon oxide, silicon-containing fluororesin, or carbon-containing silicon oxide.

In the method of forming a multilayer wiring according to the present invention, preferably, the step of forming the first insulating film has substantially the same height as the upper surface of the first wiring. 1
Multilayer insulation between a lower first insulating film covering a side surface of a wiring and an upper first insulating film covering an upper surface of the first wiring and formed on the first wiring and the lower first insulating film. A film is formed, and the second insulating film is formed of an insulating material having an etching selectivity with respect to the upper first insulating film.

Preferably, in the method of forming a multilayer wiring according to the present invention, a step of forming a lower first insulating film of the substrate before the step of forming the first wiring; Forming a groove-shaped first wiring opening in the film; and forming the first wiring in the film.
After the step of forming the first wiring and before the step of forming the second insulating film, the wiring opening is formed by filling the opening for wiring with a conductive material. The method further includes forming an upper first insulating film in the upper layer, wherein the second insulating film is formed of an insulating material having an etching selectivity with respect to the upper first insulating film.

In the method of forming a multilayer wiring according to the present invention, a first wiring is formed on a substrate, a first insulating film covering the first wiring is formed, and at least an upper surface of the first wiring is formed on the first insulating film. The first opening for exposing is formed. Next, a second insulating film is formed in the first opening and in an upper layer of the first insulating film using an insulating material having an etching selectivity with respect to at least a surface portion of the first insulating film. Next, in the second insulating film, a groove-shaped second opening having a width smaller than the width of the first opening and having a pair of opposed inner wall surfaces both passing above the region of the first opening. And a third opening communicating with the second opening in the second insulating film in the first opening, having substantially the same width as the second opening, and exposing at least an upper surface of the first wiring. To form Next, a plug is formed by filling the inside of the third opening with a conductive material, and a second wiring is formed integrally with the plug by filling the inside of the second opening with a conductive material.

According to the above-described method for forming a multilayer wiring of the present invention, the second layer is formed of an insulating material having an etching selectivity with respect to the surface layer of the first insulating film in which the first opening is formed.
Forming an insulating film, forming a groove-shaped second opening (wiring groove) formed in the second insulating film such that a pair of inner wall surfaces both pass over the region of the first opening; Since the third opening (contact hole) is formed so as to communicate with the second opening at substantially the same width, even if misalignment of a layer serving as a mask for forming the second opening occurs, the contact can be formed. It is possible to prevent the opening diameter of the hole from becoming small.

[0039]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A is a plan view of a multilayer wiring portion of a semiconductor device formed by the method of forming a multilayer wiring according to the present embodiment, and FIG. 1B is a cross-sectional view taken along line XX ′ in FIG. FIG. 3C is a sectional view taken along line YY ′ in FIG. A first wiring 30 made of, for example, an aluminum alloy is formed on the substrate 10. A first side surface of the first wiring 30 is covered and is made of, for example, polyarylether and has a height substantially equal to the upper surface of the first wiring 30.
An interlayer insulating film 20 is formed. The upper surface of the first wiring 30 is covered, and is formed on the first wiring and the first interlayer insulating film.
For example, the second interlayer insulating film 21 made of nanoporous silica (foamed silicon oxide) and serving as an etching stopper
Are formed.

In the second interlayer insulating film 21, a pattern opening P for forming a contact hole in a later step and exposing at least the upper surface of the first wiring 30 is formed. A third insulating film 22 made of, for example, polyarylether is formed on the second interlayer insulating film 21 so as to fill the pattern opening P. The third interlayer insulating film 22 is formed of an insulating material having an etching selectivity with respect to the second interlayer insulating film 21. A fourth interlayer insulating film 23 made of, for example, nanoporous silica (foamed silicon oxide) is formed on the third insulating film 22.

A trench T for a second wiring having the upper surface of the second interlayer insulating film 21 as a bottom surface is formed through the fourth interlayer insulating film 23 and the third interlayer insulating film 22. A contact hole CH is formed, which communicates with the groove T and penetrates the second interlayer insulating film 21 and exposes the upper surface of the first wiring 30. An adhesion layer 31 made of, for example, a laminate of tantalum nitride and copper is formed so as to cover the inner wall of the contact hole CH and the trench T for the second wiring. The contact layer CH and the wiring Of the plug 32a made of, for example, copper and
The wiring 32b is formed integrally.

Here, a pair of inner wall surfaces of the second wiring groove T facing each other are formed so as to pass above the area of the pattern opening P. For example, the width of the groove T for the first wiring 30 and the second wiring is l ₂ = 0.3 μm, and the opening diameter of the contact hole CH is l ₂ = l ₄ =
0.3 μm. On the other hand, the side of the pattern opening P on the side orthogonal to the extending direction of the second wiring groove T is l ₁
(0.1 μm) + l ₂ (0.3 μm) + l ₃ (0.1 μm
m) = 0.5 μm. As described above, the allowance for the alignment of the groove T for the second wiring with the pattern opening P is 0.1 μm.
Even if the maximum misalignment occurs, the second
The design is such that a pair of inner wall surfaces of the wiring groove T facing each other pass above the region of the pattern opening P.

In the above-described multilayer wiring, as the first interlayer insulating film 20 and the third interlayer insulating film 22, in addition to the polyaryl ether, a cyclic fluororesin / siloxane copolymer, a fluorinated polyarylether-based resin, Pentafluorostyrene resin, polytetrafluoroethylene resin,
Fluorinated polyimide resin, polyfluorinated naphthalene resin,
Alternatively, a low dielectric constant insulating material such as a polyimide resin can be preferably used. Also, the second interlayer insulating film 2
As the first and fourth interlayer insulating films 23, in addition to nanoporous silica (foamed silicon oxide), an insulating material such as silicon oxide, silicon-containing fluorine resin, or carbon-containing silicon oxide can be preferably used.

According to the above-described multilayer wiring of the present embodiment, the insulating material having an etching selectivity with respect to the second interlayer insulating film in which the pattern opening to be a region where a contact hole is formed in a later step is formed. To form a third interlayer insulating film, and even if the misalignment of a layer serving as a mask for forming a groove for the second wiring occurs to a maximum extent, the second interlayer insulating film formed in the third interlayer insulating film is formed. A pair of inner wall surfaces pass above the pattern opening region, and a contact hole is formed to communicate with the second wiring groove at substantially the same width. Even if misalignment of a layer serving as a mask for forming the groove for the second wiring occurs, it is possible to prevent the opening diameter of the contact hole from being reduced.

A method for forming a multilayer wiring in the above semiconductor device will be described. First, FIG.
FIG. 1A is a cross-sectional view taken along line XX ′, and FIG.
As shown in (a), a first wiring is formed on the substrate 10 by, for example, a damascene method. That is, an insulating material such as polyarylether is deposited on the substrate 10 using a spin coater or the like, and is solidified by a curing process.
To form Further, a groove for the first wiring is formed in the first interlayer insulating film 20, and the groove is filled with a conductive material such as an aluminum alloy to form the first wiring 30. Alternatively, after patterning the first wiring 30 on the substrate 10, the first interlayer insulating film 30 is formed and etched back or CMP.
The first interlayer insulating film 20 is exposed until the first wiring 30 is exposed by a polishing process such as a (Chemical Mechanical Polishing) method.
Can also be removed.

Next, FIG. 3 (a) shows X in FIG. 1 (a).
FIG. 1B is a cross-sectional view taken along a line X- ′, and FIG.
(Corresponding to the cross-sectional view taken along the line Y ′), a method using a spin coater or the like or a method using a spin coater or the like to cover the upper surface of the first wiring 30 and form an upper layer on the first interlayer insulating film 20.
An insulating material such as nanoporous silica (foamed silicon oxide) is deposited in a thickness of 800 nm by a D (Chemical Vapor Deposition) method or the like, subjected to an aging treatment at a temperature of 100 ° C., and further dried at a temperature of 100 ° C. And then annealing at a temperature of 300 ° C.
A second interlayer insulating film 21 is formed.

Next, FIG. 4 (a) shows X in FIG. 1 (a).
FIG. 1B is a cross-sectional view taken along a line X- ′, and FIG.
As shown in the sectional view at Y ′), a resist film R1 is patterned by a photolithography process, and an etching process such as RIE (reactive ion etching) is performed under the same conditions as the etching conditions of the silicon oxide-based material. Then, a pattern opening P for exposing at least the upper surface of the first wiring 30 is formed in the second interlayer insulating film 21 as a region where a contact hole is to be formed in a later step.

Next, FIG. 5 (a) shows X in FIG. 1 (a).
FIG. 1B is a cross-sectional view taken along a line X- ′, and FIG.
(Corresponding to a cross-sectional view taken along line Y ′), after removing the resist film R1 by an ashing process, an insulating material such as polyarylether is applied to the inside of the pattern opening P and to the second A third interlayer insulating film 22 is formed by depositing a 400 nm thick film on the interlayer insulating film 21 and solidifying it by a curing process at 400 ° C.

Next, a method using a spin coater or the like or CVD (Chemical) is applied to the upper layer of the third interlayer insulating film 22.
Insulation material such as nanoporous silica (foamed silicon oxide) is deposited to 100 nm by Vapor Deposition method.
Then, the fourth interlayer insulating film 23 is formed by performing an annealing process or the like.

Next, FIG. 6 (a) shows X in FIG. 1 (a).
FIG. 1B is a cross-sectional view taken along a line X- ′, and FIG.
(Corresponding to the cross-sectional view taken along the line Y ′), a resist film R of the opening pattern _PT of the second wiring groove is formed on the fourth interlayer insulating film 23 by a photolithography process.
Form 2

Next, an etching process such as RIE is performed to process the fourth insulating film 23 along the opening pattern _PT of the second wiring groove.

Next, FIG. 7 ((a) shows X in FIG. 1 (a).
FIG. 1B is a cross-sectional view taken along a line X- ′, and FIG.
As shown in a sectional view of Y ′, for example, using an ECR (Electron Cyclotron Resonance) type plasma etching apparatus (etching gas and flow rate: N ₂ / He = 40/165 sccm, pressure: 0.8 Pa) , Microwave power: 500 W (2.45 GHz), RF power: 1
The trench T for the second wiring is formed in the third interlayer insulating film 22 by an etching process under the conditions of (00 W, substrate temperature: −50 ° C.). The groove T for the second wiring is a groove penetrating the third interlayer insulating film 22 and having the upper surface of the second interlayer insulating film 21 as a bottom surface. Since the resist film R2 is similar to the characteristics of the polyarylether to be etched, the resist film R2 is also removed in a short time in the above-described etching process, and the fourth interlayer insulating film 2 made of nanoporous silica (foamed silicon oxide) is formed.
3 functions as an etching mask.

Next, the above etching process is further continued until the first wiring 30 is exposed in the pattern opening P, and the second wiring for the second wiring is self-aligned with the second interlayer insulating film 21 as an etching stopper. A contact hole CH communicating with the trench T is opened.

In the subsequent steps, for example, the inner wall of the contact hole CH and the trench T for wiring is coated, and tantalum nitride is deposited to a thickness of 30 nm and copper is deposited to a thickness of 150 n by a DC magnetron sputtering method.
1 and a conductive material such as copper is deposited in a thickness of 1.5 μm on the upper layer by filling the contact hole CH and the trench T for wiring by electrolytic plating, for example.
Next, the conductive material such as tantalum nitride and copper deposited outside the trench T for the second wiring is removed by, for example, the CMP method, and the plug 32a and the second wiring 32b are formed integrally. Thus, the semiconductor device having the multilayer wiring shown in FIG. 1 can be formed.

In the above-described method for forming the multilayer wiring, the pair of inner wall surfaces of the second wiring groove T are formed so as to pass over the area of the pattern opening P.
For example, the width of the groove T for the first wiring 30 and the second wiring is l
Assuming that ₂ = 0.3 μm, the opening diameter of the contact hole CH is l ₂ = l ₄ = 0.3 μm. In contrast, the second
The side of the pattern opening P on the side orthogonal to the extending direction of the wiring groove T is defined as l ₁ (0.1 μm) + l ₂ (0.3 μm) +
l ₃ (0.1 μm) = 0.5 μm. in this way,
By making the alignment margin of the second wiring groove T with respect to the pattern opening P 0.1 μm, even if the maximum misalignment occurs, the pair of opposed inner wall surfaces of the second wiring groove T both It is designed to pass above the area of the pattern opening P.

In the above-described method for forming the multilayer wiring, the first interlayer insulating film 20 and the third interlayer insulating film 22 are not limited to polyaryl ethers, but are not limited to cyclic fluororesin / siloxane copolymers and fluorinated polyarylethers. A low dielectric constant insulating material such as a resin, a polypentafluorostyrene-based resin, a polytetrafluoroethylene-based resin, a fluorinated polyimide resin, a polyfluorinated naphthalene-based resin, or a polyimide resin can be preferably used. In addition, as the second interlayer insulating film 21 and the fourth interlayer insulating film 23, in addition to nanoporous silica (foamed silicon oxide), insulating materials such as silicon oxide, silicon-containing fluorine resin, or carbon-containing silicon oxide are preferably used. Can be used.

According to the above-described method for forming a multilayer wiring of the present embodiment, the etching selectivity is obtained with respect to the second interlayer insulating film in which a pattern opening to be a region where a contact hole is formed in a later step is formed. Since the third interlayer insulating film is formed of an insulating material, even if the misalignment of a layer serving as a mask for forming a groove for the second wiring occurs to a maximum, the third interlayer insulating film formed on the third interlayer insulating film is formed. The pair of inner wall surfaces of the two wiring grooves are designed so as to pass above the pattern opening area, and communicate with each other with substantially the same width as the second wiring groove. Since a contact hole is formed,
Even if misalignment of a layer serving as a mask for forming the groove for the second wiring occurs, it is possible to prevent the opening diameter of the contact hole from being reduced.

The present invention can be applied to any semiconductor device having multilayer wiring, such as a MOS transistor semiconductor device such as a DRAM, a bipolar semiconductor device, or an A / D converter. A highly reliable multilayer wiring can be provided for a semiconductor device which has been miniaturized, miniaturized, and miniaturized.

The present invention is not limited to the above embodiment. For example, in the present embodiment, a multi-layer wiring of a wiring layer having a two-layer structure is described, but a multi-layer wiring of a wiring layer having a wiring structure of three or more layers may be used, or a wiring layer having a wiring structure of three or more layers may be used. The multilayer wiring of the present invention can be applied to a part of them. Each of the first to fourth interlayer insulating films may have a single-layer structure or a multilayer structure of two or more layers. Further, the first wiring and the second wiring may also have a multilayer structure. Further, as a material of the wiring layer, other conductive materials such as an aluminum alloy can be used in addition to copper. In addition, various changes can be made without departing from the spirit of the present invention.

[0061]

According to the multilayer wiring of the present invention, in the multilayer wiring formed by the dual damascene method for simultaneously forming the contact connection and the groove wiring, the opening of the contact hole caused by misalignment between the contact hole and the wiring groove. It is possible to prevent the aperture from becoming small.

According to the method of forming the multilayer wiring of the present invention, the multilayer wiring of the present invention can be easily formed, and in the dual damascene method for simultaneously forming the contact connection and the groove wiring, the misalignment of the contact hole and the wiring groove is performed. Therefore, it is possible to form a multilayer wiring by preventing the opening diameter of the contact hole from being reduced due to the above.

[Brief description of the drawings]

FIG. 1A is a plan view of a multilayer wiring according to an embodiment of the present invention, FIG. 1B is a cross-sectional view taken along line XX ′ in FIG. 1A, and FIG. It is sectional drawing in YY '.

FIGS. 2A and 2B show the steps up to the step of forming a first wiring in the forming step of the method of forming a multilayer wiring according to the embodiment of the present invention. FIG. ,
FIG. 2B is a cross-sectional view taken along a line YY ′ in FIG.

3A and 3B show a process subsequent to FIG. 2 up to a process of forming a second interlayer insulating film. FIG. 3A is a cross-sectional view taken along line XX ′ in FIG. 1A, and FIG. It is sectional drawing in YY 'in (a).

4A and 4B show a process subsequent to that of FIG. 3 up to a process of forming a pattern opening in a second interlayer insulating film.
FIG. 1A is a cross-sectional view taken along line XX ′, and FIG.
It is sectional drawing in YY 'in (a).

FIGS. 5A and 5B show a process following the process shown in FIG. 4 up to the step of forming a fourth interlayer insulating film. FIG. 5A is a cross-sectional view taken along line XX ′ in FIG. 1A, and FIG. It is sectional drawing in YY 'in (a).

FIGS. 6A and 6B show a process subsequent to that of FIG. 5 up to a process of forming a groove pattern for a second wiring of the fourth interlayer insulating film.
FIG. 1A is a cross-sectional view taken along line XX ′, and FIG.
It is sectional drawing in YY 'in (a).

FIGS. 7A and 7B show up to a step of forming a second wiring groove and a contact hole in a step subsequent to FIG. 6; FIG.
FIG. 1A is a cross-sectional view taken along line XX ′, and FIG.
It is sectional drawing in YY 'in (a).

8A is a plan view, FIG. 8B is a cross-sectional view taken along line XX ′ in FIG. 8A, and FIG.
(C) is a sectional view taken along line YY 'in (a).

9A and 9B are cross-sectional views taken along the line XX ′ in FIG. 1A, showing up to a step of forming a second interlayer insulating film in a forming step of a method of forming a multilayer wiring according to a conventional example.
FIG. 2B is a cross-sectional view taken along a line YY ′ in FIG.

10A and 10B show up to a step of forming a pattern opening of a contact hole in the second interlayer insulating film in a step subsequent to that of FIG. 9; FIG. 10A is a cross section taken along line XX ′ in FIG. FIG. 1B is a cross-sectional view taken along the line YY ′ in FIG.

FIGS. 11A and 11B show a process subsequent to that of FIG. 10 up to a process of forming a third interlayer insulating film.
FIG. 1B is a cross-sectional view taken along the line X ′, and FIG.
FIG.

FIGS. 12A and 12B are cross-sectional views taken along line XX 'in FIG. 1A, up to a step of forming a resist film of an opening pattern of a second wiring groove in a step subsequent to that of FIG. ,
FIG. 2B is a cross-sectional view taken along a line YY ′ in FIG.

FIG. 13 shows a process up to a process of forming a second wiring groove and a contact hole in a process subsequent to that of FIG. 12 (a).
1A is a sectional view taken along line XX ′ in FIG. 1A, and FIG. 1B is a sectional view taken along line YY ′ in FIG.

FIGS. 14A and 14B are cross-sectional views for explaining a problem in the conventional example, in which FIG. 14A shows a step of forming a resist film of an opening pattern of a second wiring groove, and FIG. 14B shows a second wiring groove. And the steps up to the step of forming a contact hole.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... board | substrate, 20 ... 1st interlayer insulation film, 21 ... 2nd interlayer insulation film, 22 ... 3rd interlayer insulation film, 23 ... 4th interlayer insulation film,
Reference numeral 30: first wiring, 31: adhesion layer, 32a: plug, 32
b: second wiring, P: pattern opening, T: groove for second wiring, CH: contact hole.

Claims (18)

[Claims] A first wiring formed on the substrate; a first insulating film formed on an upper layer of the first wiring; and a first insulating film exposing at least an upper surface of the first wiring. A first opening formed in the insulating film, and an insulating material having an etching selectivity with respect to at least a surface layer portion of the first insulating film, the inside of the first opening and the upper layer of the first insulating film. A second insulating film formed on the second insulating film, the second insulating film having a width smaller than a width of the first opening, and a pair of opposing inner wall surfaces both of the first insulating film;
A groove-shaped second opening passing above the region of the opening, communicating with the second opening, having substantially the same width as the second opening, and forming at least an upper surface of the first wiring; A third opening formed in the second insulating film in the first opening so as to be exposed; a plug embedded in the third opening; and a plug embedded in the second opening. A multilayer wiring having a plug and a second wiring integrally formed. 2. The multilayer wiring according to claim 1, wherein the second opening is a groove-shaped opening formed in the second insulating film so as to expose an upper surface of the first insulating film. 3. A first insulating film having a thickness corresponding to at least the depth of the first opening is formed of expanded silicon oxide (nanoporous silica), silicon oxide, silicon-containing fluororesin, or carbon-containing silicon oxide. 2. The multilayer wiring according to claim 1, wherein the multilayer wiring is an insulating film containing any of the following. 4. The method according to claim 1, wherein the second insulating film is formed of a polyarylether resin, a cyclic fluororesin / siloxane copolymer, a fluorinated polyarylether resin, a polypentafluorostyrene resin, a polytetrafluoroethylene resin, or a fluorine-containing resin. The multilayer wiring according to claim 1, wherein the multilayer wiring is an insulating film containing any one of a polyimide resin, a polyfluorinated naphthalene resin, and a polyimide resin. 5. The multilayer wiring according to claim 1, wherein said plug and said second wiring are formed of a conductive material containing copper or aluminum. 6. A third insulating film made of an insulating material having an etching selectivity with respect to the second insulating film is further formed on the second insulating film, wherein the second opening is formed by:
2. The multilayer wiring according to claim 1, wherein the multilayer wiring is formed so as to penetrate the third insulating film. 7. The multilayer according to claim 6, wherein the third insulating film is an insulating film containing any of foamed silicon oxide (nanoporous silica), silicon oxide, silicon-containing fluororesin, and carbon-containing silicon oxide. wiring. 8. A lower first insulating film having substantially the same height as the upper surface of the first wiring, covering a side surface of the first wiring, and a first insulating film for the first wiring. Cover the top surface,
An upper layer first insulating film formed on the first wiring and the lower layer first insulating film, wherein the second insulating film has an etching selectivity with respect to the upper layer first insulating film. 2. The multilayer wiring according to claim 1, comprising: 9. A step of forming a first wiring on a substrate, a step of forming a first insulating film covering the first wiring, and exposing at least an upper surface of the first wiring to the first insulating film. Forming a first opening, inside the first opening and above the first insulating film,
A step of forming a second insulating film by using an insulating material having an etching selectivity with respect to at least a surface layer portion of the first insulating film; a width of the second insulating film smaller than a width of the first opening; Forming a groove-shaped second opening in which a pair of opposed inner wall surfaces both pass over the region of the first opening; and forming a second insulating film in the first opening. Forming a third opening communicating with the second opening, having substantially the same width as the second opening, and exposing at least an upper surface of the first wiring; Forming a plug by filling the second opening with the conductive material, and forming a second wiring integrally with the plug by filling the second opening with the conductive material. 10. The step of forming the first opening, wherein the groove-shaped second opening is formed even when the misalignment of a layer serving as a mask is maximized in the step of opening the second opening. The pair of inner wall surfaces facing each other
10. The method for forming a multilayer wiring according to claim 9, wherein the wiring is formed so as to pass above the region of the opening. 11. The step of forming the second opening, wherein the second insulating film is formed in a groove shape so that an upper surface of the first insulating film is exposed using the first insulating film as an etching stopper. Item 10. The method for forming a multilayer wiring according to Item 9. 12. A method in which a portion of the first insulating film having a thickness corresponding to at least the depth of the first opening is formed by using foamed silicon oxide (nanoporous silica), silicon oxide, silicon-containing fluororesin, or carbon-containing silicon oxide. The method for forming a multilayer wiring according to claim 9, wherein the method is formed using an insulating film containing any of the above. 13. The second insulating film is formed of a polyaryl ether resin, a cyclic fluororesin / siloxane copolymer, a fluorinated polyaryl ether resin, a polypentafluorostyrene resin, a polytetrafluoroethylene resin, or a fluorine-containing resin. The method for forming a multilayer wiring according to claim 9, wherein the multi-layer wiring is formed by an insulating film containing any of a fluorinated polyimide resin, a polyfluorinated naphthalene-based resin, and a polyimide resin. 14. The method according to claim 9, wherein the plug and the second wiring are formed of a conductive material containing copper or aluminum. 15. After the step of forming the second insulating film and before the step of forming the second opening, an etching selectivity on the second insulating film is formed above the second insulating film. 10. The formation of the multilayer wiring according to claim 9, further comprising the step of forming a third insulating film using an insulating material having the third insulating film, wherein the step of forming the second opening is formed through the third insulating film. Method. 16. The third insulating film according to claim 15, wherein said third insulating film is formed of an insulating film containing any of foamed silicon oxide (nanoporous silica), silicon oxide, silicon-containing fluororesin, or carbon-containing silicon oxide. Multi-layer wiring. 17. A step of forming the first insulating film, the lower first insulating film having substantially the same height as the upper surface of the first wiring and covering a side surface of the first wiring; Forming a laminated insulating film of the first wiring and an upper first insulating film formed on the first wiring and the lower first insulating film by covering an upper surface of the first wiring; 10. An insulating material having an etching selectivity with respect to the upper first insulating film.
The method for forming a multilayer wiring according to the above. 18. A step of forming a lower first insulating film of the substrate before the step of forming the first wiring, and forming a groove-shaped first wiring opening in the lower first insulating film. The step of forming the first wiring includes forming the first wiring opening by filling the opening with a conductive material; and forming the second wiring after the step of forming the first wiring. Forming an upper first insulating film on the first wiring and the lower first insulating film before forming the second insulating film, wherein the second insulating film is formed on the upper first insulating film. 10. An insulating material having an etching selectivity with respect to an insulating material.
The method for forming a multilayer wiring according to the above.