JP2000298596A - Vlsi emulator using processor and resettable chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to optionally verify the design of a VLSI from the initial stage of the design up to the latter half stage. SOLUTION: A model of a VLSI chip is divided into a function part and an external interface part. The function part is executed by a processing module 3 consisting of a processor. The external interface part is realized by an external interface signal generator 4 using a resettable circuit and generates a practical pin signal. An interface control packet consisting of an instruction word and data is used for information exchange between the function part and the external interface part. Since the module 3 and the signal generator 4 are built in a device, the internal function part and the external interface part can be verified in a practical object system on the various stages of VLSI design, the design time of the VLSI and the verification and design time of the whole system can be saved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus capable of emulating a VLSI for verification. More specifically, a processor and a reconfigurable chip are used to emulate a VLSI design before producing it as a chip so that it can be verified together with a system in which the chip is built and executed (hereinafter referred to as a “target system”). VLSI emulator.

[0002]

2. Description of the Related Art In general, it takes a considerable amount of time to design a VLSI and produce it as a chip, and its cost is high. Therefore, it is desirable to eliminate any errors at a design stage before the chip is produced as a chip. As the structure of the VLSI becomes more complicated and the system in which the chip is built becomes more complicated, the probability of occurrence of an error increases. Therefore, emulation for pre-verifying the design together with the target system is indispensable. .

On the other hand, a conventional emulator is a resettable chip (FPGA: Field Programmable Gate Array).
Are connected by a resettable network, and emulates a gate-level logic circuit.
Such an emulator can only verify the design in the latter half of the design stage. Therefore, there is a problem that verification cannot be performed at the initial stage of the design.

[0004] Watkins US Patent No. 490125
In the ASIC emulator of No. 9, the software model of the entire VLSI is executed by a host computer,
The ASIC emulator system converts the value of the pin signal generated when performing the model into an electrical signal and sends it to the socket. Communication between the host computer and the ASIC emulator is a set of pin signal values required for each pin. In this method, there is a limit in increasing the emulation speed, and there is a problem in verifying various VLSIs, for the following reasons.

[0005] 1) The host computer performs all the parts, including generation of pin signals required for the external interface, by software. 2) Generally, computer I
Communication using the / O port is very slow compared to the performance of the processor. 3) Since the host computer and the ASIC emulator are connected through a cable, the transmission is affected by the cable transmission capability. By using a host computer, a part that is not directly necessary for emulation is included, and the system becomes large.

Therefore, in the present invention, the VLSI model is divided into a functional part and an external interface part, and the performance of the functional part is performed by a processing module embodied by one or more processors. Allows the external interface signal generator to use the reconfigurable circuit to create the actual pin signals, while the communication between both is controlled by the interface control packet (command and data By embedding both of them (a processing module and a signal generator for an external interface) in one device, the emulation speed is increased, and a VLSI design that requires various speeds efficiently is required. Present a plan that can verify.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to reset a VLSI software model to a processor-based processing module. A processor and a reconfigurable chip that can be freely verified not only in the second half of the design but also in the early stages of the design, because emulation using a signal generator for an external interface using a possible chip is possible. And a VLSI emulator using the same.

Another object of the present invention is to provide a processor-based processing module for a functional part of a VLSI, a reconfigurable circuit for an external interface part, and an interface for communication between the two. By using control packets and incorporating both into one device, the overall emulation speed is increased,
Another object of the present invention is to generate an accurate pin signal.

[0009]

A VLSI emulator using a processor and a reconfigurable chip according to the present invention to achieve the above object is a VLS to be verified.
A processor for executing a software model of a functional part of I, a memory for storing ROM and / or RAM for storing the software model and monitoring code, and a processing module for connecting a channel between the processor and the memory; A pin signal processing unit comprising one or more resettable elements for performing the external interface model of the above; a buffer for buffering and synchronizing a speed difference between the processing module and the pin signal processing unit; and A signal generator for an external interface comprising a controller for managing a buffer; a channel for communication of an interface control packet between the processing module and the signal generator for the external interface; a signal generator for the external interface A socket for connecting between the target system VLSI is provided to be verified; including.

The above objects and various advantages of the present invention will become more apparent by preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG.
1 is a drawing for explaining an emulator system (hereinafter, referred to as “emulator”) according to an embodiment of the present invention and a peripheral system thereof.

The VLSI model to be verified is divided into a software model describing functions and an external interface model. In the drawing, the emulator 2
Includes a processing module 3 and a signal generator 4 of an external interface. The processing module 3 includes one or more processors that execute a software model describing a function. The signal generator 4 of the external interface is a resettable chip (for example, FPG
A). This resettable chip (eg, FPG
A) is responsible for interfacing with the outside according to the external interface model. Processing module 3
If an external interface is required, the corresponding interface control packet is transmitted through the channel 5 by the signal generator 4 of the external interface. The signal generator 4 of the external interface decodes the interface control packet and sends an electrical signal to the target system 9 on demand or reads an electrical signal from the target system 9 and transmits it to the processing module 3 I do.

The target system 9 has a socket 6 to which an electrical pin signal generated by the signal generator 4 of the external interface is connected. Thereby, it can be electrically connected to another VLSI chip 7 inside the target system 9 and another socket 8 connected to another emulator 11. On the other hand, the emulator 2 is connected to an external monitoring / control computer 10 through an internal monitoring / control port 1. Thereby, the emulation status can be observed and controlled from the outside. Monitoring / control port 1
Is used by the processing module 3 to download a software model before starting emulation or to reset a resettable chip inside the signal generator 4 of the external interface.

FIG. 2 is a drawing for explaining an embodiment of the processing module 3. As shown in the figure, the software model describing the function is converted (compiled) into a form executable by the processor 12 in the processing module 3 and stored in the memory 13 together with the code for monitoring. The processor 12
Executes the software model in the memory 13.
At this time, the software model is divided into multiple blocks,
It can be executed by a plurality of processors and a plurality of memories. In this case, a communication channel for communication between a plurality of processors is provided. The memory 13 is a ROM
And / or RAM, having the code to be executed, either pre-loaded or received through the monitoring / control port 1.

When the software model describing the function attempts to read data from or write data to the target system 9, the processor 12 sends a corresponding interface control packet to the external interface signal generator 4. To send through the channel. When writing data to the target system 9, the interface control packet includes a write command, an address, and data to be written. When reading data in the target system 9, the interface control packet includes a read command and an address. This packet is sent to the signal generator 4 of the external interface, and after confirming that the signal generator 4 has read the data of the target system 9, the processor 12 indicates that the result value is to be obtained. An interface control packet is sent to the signal generator 4 and its value is read. The state of the emulation is controlled and monitored by a command sent from the monitoring / control computer 10 through the monitoring / control port 1 by the user.

FIG. 3 is a diagram for explaining an embodiment of the signal generator 4 of the external interface. The interface control packet sent from the processing module 3 through the channel 5 is held in the buffer 15 through the controller 14. The command and data of the packet are generated as a corresponding pin signal sequence by the pin signal processing unit 16 composed of a reconfigurable chip pre-configured by an external interface model, and sent to the socket 6. . The resetting of the resettable chip in the pin signal processing unit 16 is performed by the value stored in the ROM of the memory 13 in the processing module 3 or the ROM / RAM dedicated to resetting before the emulation starts. Also,
Reconfiguration of the chip may be downloaded and performed by the monitoring / control port 1.

In the case of reading, the pin signal processing unit 16 holds the value read from the socket 6 in the buffer 15 and then notifies the processing module 3 of the state. Then, the processing module 3 later acquires the stored value. Controller 14
Manages the buffer 15 so that the buffer 15 serves to buffer and synchronize the speed difference between the processing module 3 and the pin signal processing unit 16. In the case of writing, the pin signal processing unit 16 changes the data in the buffer 15 as an electrical signal according to a command, and transmits the electrical signal to the socket 6.

From the above description, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

[0019]

As described above, according to the present invention, not only the design in the late stage of the design but also the design in the early stage of the design can be emulated, so that the functional portion and the external interface are verified in the early stage of the VLSI design. Therefore, the development time of the application system can be shortened.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a system according to the present invention and an embodiment example.

FIG. 2 is a diagram illustrating an embodiment of a processor-based processing module according to the present invention.

FIG. 3 is a diagram showing an embodiment of a signal generator of an external interface according to the present invention.

[Explanation of symbols]

 1: monitoring / control port 2, 11: emulator 3: processing module 4: signal generation of external interface 5: interface control packet channel 6, 8, socket 7: VLSI chip 9: target system 10: monitoring / control computer 12: 1 One or more memories 14: Controller 15: Buffer 16: Pin signal processing unit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Lee Jong-jong, Korea

Claims (5)

[Claims] 1. A device for emulating a VLSI design, comprising: a processing module having a processor for executing a software model of a functional part of the VLSI design; and a hardware model of an external interface part of the VLSI design. An emulator for a VLSI design, comprising: a formed reconfigurable module; wherein communication between the processing module and the reconfigurable module uses an interface control packet composed of commands and data. 2. The processing module according to claim 1, wherein the processing module includes at least one processor, at least one memory including a ROM and / or a RAM, and a bus for connecting the processor and the memory. An emulator for a VLSI design according to item 1. 3. A pin signal processing unit for generating a pin signal sequence by output data processing and receiving input data by pin signal sequence processing, and an output data sent from the processing module. A buffer set for holding input data sent from the pin signal processing unit, and a controller for managing the buffer set for synchronizing a speed difference between the processing module and the pin signal processing unit. The emulator of a VLSI design according to claim 1, comprising: 4. The VLSI design emulator according to claim 1, further comprising a socket for connecting the reconfigurable module to a target system to which the VLSI is applied. 5. A monitoring control port for connecting to a monitoring and control computer, wherein the monitoring and control computer downloads a monitoring code and a software model for the processing module, and monitors and monitors an external emulation status. The VLSI of claim 1, which controls.
Emulator of design.