JP2000293557A - Simulation method for power consumption - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method which can fast estimate the power consumption of a semiconductor integrated circuit when this circuit is designed with reuse of a processor core, etc., by calculating the power consumption that is needed for a processor to execute a program code from the power consumption of a CPU core part and a cache part. SOLUTION: In a cache part power consumption calculation process 104, the electric power consumed at a cache part is calculated from the power consumption information on every cache operation and in accordance with the operation of the cache part which is simulated in an instruction reading process 103. In an instruction execution process 105, the processor operation of a read instruction is simulated. In a CPU part power consumption calculation process 106, the power consumption is calculated in response to the instruction that is simulated in the process 105. In a power consumption calculation process 107, the power consumption necessary for the current execution cycle of a processor model is calculated from the power consumption which are calculated in both processes 104 and 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simulating power consumption of a semiconductor integrated circuit using a computer, and more particularly, to a method of reusing and integrating a core library already designed, such as a processor core or a megacell core, and integrating it. It is an object of the present invention to provide a simulation method which simulates the circuit operation of the semiconductor integrated circuit when designing the semiconductor integrated circuit and estimates the power consumption at high speed.

[0002]

2. Description of the Related Art Heretofore, as a method of simulating power consumption of a semiconductor integrated circuit using a computer, a circuit level or gate level method has been used.

In a circuit-level power consumption simulation, a transistor-level netlist of a target semiconductor integrated circuit is analyzed by a circuit-level simulation method such as SPICE, and power is calculated from the resulting voltage value and current value. Is what you do.

As a method for simulating power consumption at the gate level, Japanese Patent Publication No. 2518553 discloses a method.
JP-A-2-171861, JP-A-3-127180
No., etc. The methods disclosed in these publications use a circuit-level power consumption simulation method for the components of a circuit included in a circuit to be simulated in advance, such as input / output of gates in the circuit and nets and the like. The power consumption per signal change of the node is obtained in advance. Then, a gate-level logic simulation of the target semiconductor integrated circuit is performed to determine input / output of gates in the circuit and signal changes at nodes such as nets. The power consumption of the entire circuit is calculated from the power.

[0005] These conventional power consumption simulation methods can be used when designing at the gate level or at the transistor level in the design process of a semiconductor integrated circuit.

Japanese Patent Application Laid-Open Nos. 9-218731 and 10-401 disclose a method for determining the power consumption of a cache memory, particularly a processor having an instruction cache.
No. 44 and JP-A-10-254944. The method disclosed in Japanese Patent Application Laid-Open No. 9-218731 calculates power consumption when an instruction cache misses and when an instruction cache hits, and uses statistical information of CPU operation in consideration of a cache page size, instruction branch, and the like. Estimate power consumption. The method disclosed in Japanese Patent Application Laid-Open No. H10-40144 executes a plurality of instructions for a cache miss and a cache hit in an actual microprocessor, and measures the power consumption at that time to determine each instruction in consideration of the cache. Find the power consumption of The method disclosed in Japanese Patent Application Laid-Open No. H10-254944 finds power consumption at the instruction level in consideration of the stall of the processor.

[0007] These conventional methods and apparatuses for simulating power consumption of a processor focus on an instruction memory,
The power consumption of the processor at the instruction level is statistically obtained.

[0008]

However, in recent years,
In the design of semiconductor integrated circuits, instead of designing a new target circuit, the design data that was designed at least once in the past, called a processor core or megacell core, is converted into a reusable core library, which is then reused and integrated. Core-based design or I for designing large-scale semiconductor integrated circuits
A design called P (Intellectual Property) base design has come to be performed. This core-based design combines multiple core libraries to achieve the desired speed,
It is necessary to estimate at an early stage whether or not a semiconductor integrated circuit having the specifications of the area and the power consumption can be realized. However, in the conventional method of simulating the power consumption at the gate level or the circuit level, the design advances to the gate level or the circuit level. There is a problem that the power consumption cannot be estimated unless the power is used.

In recent semiconductor integrated circuit designs, not only a combination of a core library as hardware but also a case where necessary functions are realized by software on a processor core and a case where hardware is realized by hardware using a megacell core A hardware / software co-design for designing a desired semiconductor integrated circuit while making a trade-off with the case has become necessary. This hardware /
In software co-design, it is important to estimate power consumption in a single chip, as well as speed and area.However, by selecting the necessary core library from many core libraries such as processor cores and megacell cores, Estimation of power consumption of a large-scale semiconductor integrated circuit including software at a gate level or a circuit level requires a huge amount of calculation time. Furthermore, the speeding up of the semiconductor circuit, the system L
The use of SI makes it possible to use processor cores with cache memory and to integrate many cores using buses on the chip, making various architectural trade-offs and searching for the optimal system configuration. There is a need to do. Also in this case, the power consumption is dynamically determined for various operations of software executed by the processor, and the operation speed and power consumption when the same function is executed by hardware are compared. The hardware will be considered as hardware. In this case, it is necessary to make a trade-off by dynamically evaluating the power consumption for each software module actually used, instead of using only the statistical information to calculate the power.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to design a large-scale semiconductor integrated circuit by reusing and integrating an already designed core library called a processor core or a megacell core. It is another object of the present invention to provide a simulation method for simulating the circuit operation of the semiconductor integrated circuit and estimating the power consumption at a high speed.

[0011]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a method for storing, in advance, power consumption information for each instruction at an instruction level of a processor and a cache operation for a cache memory. Power consumption information for each bus, the power consumption information for each address area in the bus address space for the bus, and during or after the simulation, the entire circuit to be simulated from the power consumption information. Is used to calculate the power consumed by.

Specifically, the simulation method according to the first aspect of the present invention is directed to a method for simulating the instruction operation of a processor having a cache memory in a computer. On the other hand, the power consumed when each instruction is executed is obtained, stored as power consumption information for each instruction, and for a plurality of operations of the cache memory,
When the power consumed for each operation is obtained and stored as power consumption information for each cache operation, the instruction operation and the cache operation are simulated for each instruction when a simulation is performed for a given program code. At the same time, the power consumption of the CPU core unit corresponding to the instruction being executed is obtained from the power consumption information for each instruction,
From the power consumption information for each of the cache operations, the power consumption of the cache unit corresponding to the cache operation generated by the bus access is obtained, and the power consumption of the CPU core unit and the power consumption of the cache unit are obtained. Of the present invention calculates the power consumption during execution of the program code.

According to the first aspect of the present invention, before execution of the simulation, simulation of a circuit level or a gate level, or a real chip actually manufactured on a trial basis, for each instruction of an instruction set of a processor and a plurality of operations of a cache memory. From the evaluation result, the power consumed when each instruction is executed is obtained and stored in the power consumption information for each instruction, and the power consumed when each cache operation is executed is obtained and stored in the power consumption information for each cache operation. Keep it. In this process, it is sufficient to perform processes for the number of instructions in the instruction set and the number of cache operation types, so that calculations can be performed within a realistic time even by using a circuit-level or gate-level simulation. . Then, while simulating the instruction operation for the program code given during the execution of the simulation, the value of the consumption output corresponding to the executed instruction is searched from the power consumption information for each instruction.
With respect to the cache, the cache operation simulates the cache operation of fetching an instruction to be executed and, for some instructions, writing or reading of data, and the value of the power consumption corresponding to the executed cache operation. Search from the power consumption information for each.
By summing up these power consumption values at regular intervals, a time transition of the power consumed by the CPU core unit and the cache unit of the processor when operating with the given program code is obtained. Here, the number of cycles executed according to the program code is usually a huge number of thousands or millions of cycles or more, but the power consumption information for each instruction must be held in a table format or function format in the computer. Can be easily searched and calculated, and the power consumption for each fixed time can be calculated at high speed by simple integration and average calculation.

According to a second aspect of the present invention, in the simulation method according to the first aspect, the power consumption information for each cache operation includes at least an operation when the cache hits and an operation when the cache misses. Power consumption information that is distinguished, and when executing a simulation for a given program code, for each instruction,
When the cache hits for the generated bus access, the power consumption information of the cache unit is obtained from the power consumption information for the hit operation in the power consumption information for each cache operation. The power consumption of the cache unit is obtained from the power consumption information of the operation in the case of a miss.

According to a third aspect of the present invention, in the simulation method of the first aspect, the power consumption information for each cache operation includes at least a case where the cache operation is a write operation and a case where the cache operation is a read operation. And power consumption information that distinguishes between an operation when a cache hits and an operation when a cache miss occurs for each of a write process and a read process. When a simulation is performed for each instruction, it is determined for each instruction whether the generated bus access is a read operation or a write operation, and whether the cache has hit or missed. The power consumption of the cache unit is obtained from the corresponding power consumption information.

According to a fourth aspect of the present invention, in the simulation method of the first aspect, the power consumption information for each cache operation includes an instruction cache data and a data cache information, and the power consumption information for each cache operation. Power consumption information is power consumption information that distinguishes between an operation when a cache hits and an operation when a cache miss occurs, and the power consumption information for each cache operation for a data cache includes at least a cache operation Power consumption information that distinguishes between write processing and read processing, and distinguishes between cache hit operations and cache miss operations for each of the write and read processes. Power consumption information and execute simulation for given program code When the generated bus access is to the instruction cache for each instruction, it is determined whether or not the cache has been hit based on the power consumption information for each cache operation for the instruction cache, and the consumption of the instruction cache unit is determined. When power is obtained and the generated bus access is to the data cache, it is determined whether the generated bus access is a read process or a write process, and whether the cache has hit or missed. The power consumption of the data cache unit is obtained from the corresponding power consumption information of the power consumption information for each cache operation, and the power consumption of the entire cache unit is calculated from the power consumption of the instruction cache unit and the power consumption of the data cache unit. It is characterized by seeking.

According to a fifth aspect of the present invention, there is provided a method for simulating, in a computer, an architecture-level operation of a circuit in which one or more bus masters and bus slaves are connected by a bus, the method comprising: The power consumed when the bus master operates is described in power consumption information for each bus master, and the power consumed when the bus slave operates is described in power consumption information for each bus slave.
With respect to the address space of the bus, for each address area, the power consumed by the bus unit at the time of bus access to the address area is stored as power consumption information for each address area. At the time of executing the simulation, for each bus access, at the same time as simulating the operation of the bus, the power consumption of the bus master is obtained from the power consumption information of each bus master, and the power consumption information of each bus slave is obtained. The power consumption of the bus slave is determined, and the power consumption of the bus unit corresponding to the generated address value of the bus access is determined from the power consumption information for each address area, and the power consumption of the bus master and the bus slave are determined. And the power consumption of the bus unit is obtained from the power consumption of the circuit unit and the power consumption of the bus unit. .

According to the fifth aspect of the present invention, before execution of the simulation, simulation of a circuit level or a gate level or an actual chip actually produced on a trial basis is performed for each bus master, bus slave, and bus unit in the circuit. From the evaluation result, the power consumed per bus cycle is obtained and stored in the power consumption information for each bus master, the power consumption information for each bus slave, and the power consumption information for each address area. The bus master is a processor, D
An SP, a DMA controller, and the like, perform read / write processing via the bus for a bus slave that has acquired the bus and connected to the bus or a bus master that has not acquired the bus. The bus master acquires the bus and stores the power consumed internally when executing a bus cycle in the power consumption information for each bus master. The bus slave is
These are a memory, a timer, a serial I / F, and dedicated hardware. Also included are bus masters that are designed so that internal registers and the like can be accessed externally when the bus is not acquired. The power consumed internally when the bus slave is selected and accessed from the bus master via the bus is stored in the power consumption information for each bus slave. The bus unit includes a bus arbiter, a bus decoder, a bus adapter, a bus signal line, and the like. Since the power consumed by the bus section differs depending on the conditions at the time of executing the bus cycle such as the address space, the power consumption at the time of the bus cycle is obtained for each address area and stored in the power consumption information for each address area. I do. This processing is performed even if the number of the address areas of the bus master, the bus slave, and the bus unit is different, and even if there are a plurality of operation states in the case where the power consumption differs depending on the operation state, the processing is further performed. Processing is performed for the number of operating states, but these numbers are a finite number of at most several tens to several hundreds, and the number can be reduced by functionalization, using circuit-level and gate-level simulations. Can be calculated in a realistic time. During the execution of the simulation, the power consumption information for each bus master,
From the power consumption information for each bus slave and the power consumption information for each address area, power consumption corresponding to the operation state of each bus cycle is searched, and the power consumption of the entire circuit is obtained from the searched power consumption. Here, the number of bus cycles executed in the simulation is usually a huge number of thousands or more than a few million cycles, but the above-mentioned power consumption information should be held in a table format or a function format in a computer. Can be easily searched and calculated, and the power consumption for each fixed time can be calculated at high speed by simple integration and average calculation.

According to a sixth aspect of the present invention, in the simulation method according to the fifth aspect, the power consumption information for each address area is at least power consumption information distinguishing a bit width of a bus access. When executing the simulation for the circuit, for each bus access,
When a bus access occurs, the power consumption of the bus section corresponding to the address value of the generated bus access and its bit width is obtained from the power consumption information for each address area.

According to a seventh aspect of the present invention, in the simulation method according to the fifth aspect, the power consumption information for each address area includes at least a case where a bus access is a read process and a case where a bus access is a write process. When the bus access occurs for each bus access during the simulation of the circuit, the address value of the generated bus access is obtained from the power consumption information for each address area. And the power consumption of the bus unit corresponding to the read processing or the write processing.

According to an eighth aspect of the present invention, in the simulation method according to the fifth aspect, the power consumption information for each address area is at least power consumption information based on a bus transfer mode and a transfer word number. If a bus access occurs for each bus access during the simulation of the circuit, the address value of the generated bus access, the transfer mode, and the transfer word are obtained from the power consumption information for each address area. The power consumption of the bus unit corresponding to the number is obtained.

A ninth aspect of the present invention is directed to a method in which a processor comprising a CPU core and a cache memory and a bus slave simulate, in a computer, an architecture-level operation of a circuit connected by a bus, The method according to claim 1, wherein the power consumption of a CPU core unit is obtained by a method according to claim 1 for a given program code, and the power consumption of a cache unit is calculated by a method according to claim 2, 3, or 4. And the power consumption of the bus unit and the power consumption of the bus slave unit are determined by at least one of the methods described in claim 5, claim 6, claim 7, and claim 8. The power consumption of the CPU core unit, the power consumption of the cache unit, the power of the bus slave unit, and the power consumption of the bus unit. And it obtains the power consumption during the program code executed on the architecture.

The invention according to claim 10 is the invention according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8, or claim 9. In the simulation method, during the execution of the simulation, information necessary for the power consumption calculation is stored in a storage device, and after the simulation, the information necessary for the power consumption calculation stored in the storage device is stored. The power consumption of the circuit during the circuit operation obtained by the simulation is obtained.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) In a first embodiment, the invention according to claims 1 and 2 will be described with reference to the drawings.

FIG. 1 is a flowchart showing the flow of processing when a simulation is performed in the power consumption simulation method according to the present embodiment. In FIG.
Is the CP of the processor model that simulates the instruction operation
This is initialization processing for setting internal variables and the like of the U core unit and the cache memory unit to initial values. A program reading process 102 reads a program code given to a processor model to be simulated, and sets a position of an instruction to start a simulation and a position of an instruction to end a simulation. An instruction reading process 103 reads an instruction to be executed by the processor model in the current execution cycle from the given program code. Since the instruction is read from the CPU unit via the cache memory, the simulation of the operation of the cache unit is also performed here. Reference numeral 104 denotes a cache unit power consumption calculation process for obtaining power consumed by the cache unit from power consumption information for each cache operation in accordance with the operation of the cache unit simulated in the instruction reading process 103. An instruction execution process 105 simulates a processor operation of the instruction read in the instruction reading process 103. 106
Is a CPU that obtains power consumption corresponding to an instruction simulated in the instruction execution processing 105 from power consumption information for each instruction.
This is a part power consumption calculation process. 107 is a cache unit power consumption calculation process 104 and a CPU unit power consumption calculation process 10
This is a power consumption calculation process for calculating the power consumption consumed in the current execution cycle by the processor model from the power consumption obtained in 6. 108 is a program reading process 102
Is a program code end determination process for determining whether or not the program code to be simulated is ended based on the end instruction position set by the above. An execution cycle update process 109 advances the execution cycle for performing the simulation by one when it is determined in the program code end process 108 that the simulation of the program code is not completed. Processing of the next execution cycle is continued. Reference numeral 110 denotes a power consumption output process for outputting information on the power consumption calculated in the power consumption calculation process 107 when the program code to be simulated by the program code completion determination process 108 has been completed.

FIG. 2 is an example of a simulated processor instruction set. 201 is an instruction table showing a list of instruction sets. The instruction LD is a data load instruction for transferring data from data in a memory area specified by an address to a register. The instruction ST is a data store instruction for transferring data from a register to a memory area specified by an address. The instruction MOV is a data transfer instruction for substituting a register specified by the source into a register specified by the destination. Instruction ADD
Is an addition instruction for adding the value of the register specified by the source and the value of the register specified by the destination, and assigning the result to the register specified by the destination. The instruction SUB is a subtraction instruction for subtracting the value of the register specified by the source from the value of the register specified by the destination, and assigning the result to the register specified by the destination. The instruction MUL is a multiplication instruction that multiplies the value of the register specified by the source by the value of the register specified by the destination, and assigns the result to the register specified by the destination. The instruction CMP is a comparison instruction that compares the value of a register or a constant value specified by a source with the value of a register specified by a destination, resets a comparison result flag if they are equal, and sets a comparison result flag if they are not equal. is there. The instruction BNE is a conditional branch instruction that causes the processing to jump to the instruction position specified by the label if the comparison result flag is set. The instruction JMP is an unconditional branch instruction that causes the processing to jump to the instruction position specified by the label.

FIG. 3 shows power consumption information for each instruction of a processor to be simulated. Reference numeral 301 denotes a power consumption table for each instruction, which stores a power consumption value when the instruction is executed once for each instruction defined in the instruction table 201.

FIG. 4 shows an example of a program executed by a processor to be simulated. Reference numeral 401 denotes the entire program, and each line from 411 to 420 represents one instruction, and each line includes a label, an instruction,
Indicates the destination (label for a branch instruction) and source. [80] of the source of the LD instruction 411 indicates the address 80 in the address space. The same applies to other LD and ST instructions.

FIG. 5 shows an example of power consumption information for each cache operation. Reference numeral 501 denotes a power consumption table for each cache operation. A hit and a miss are defined as cache operations in 502. The cache operation hits and misses are obtained in advance by a circuit simulator or the like, and the power consumption table for each cache operation is obtained. It is stored in the power table 501. Here, at the time of hit, 20 [μW / MH
z], and a value of 100 [μW / MHz] at the time of mistake.

FIG. 15 is an example of a hardware configuration diagram of a computer that executes the simulation processing according to the present embodiment. 1501 is a display device for viewing all processed information, 1502 is a keyboard for the designer to input all information and processing instructions, 1503
Is a central processing unit that performs all kinds of processing, and 1504 is a storage device that stores various information.

Hereinafter, a method of simulating power consumption according to the present embodiment will be specifically described with reference to the follow-up of FIG.

In an initialization process 101, initialization for executing a program is performed. Here, the CPU unit of the processor model and various registers of the cache memory unit are set. It is assumed that the contents of the memory are set to 2 for [80] and 5 for [A0]. Program reading processing 1
In 02, the program code 401 is read into the storage means, and the program counter register is set so as to start the execution of the program from 411. Further, it is set so that the execution of the program is terminated when the number reaches 420. In the instruction reading process 103, the instruction pointed to by the program counter register is fetched. In this case, the LD instruction 411 is fetched via the cache, but the cache accesses the address for the first time, so the cache misses. Then, the cache unit power consumption calculation processing 104 uses the power consumption table 501 for each cache operation to calculate 100 [μW / MH] when a miss occurs.
z] is required. Here, the calculation of the power consumption is a simple process of simply subtracting the power consumption value of the corresponding cache operation from the power consumption table 104 for each cache, and is easily and quickly calculated. Next, L
The operation of the D instruction 411 is simulated, and the value 2 of the memory address [80] is read into the register reg0.
Next, the CPU unit power consumption calculation processing 106 calculates a value corresponding to the LD instruction from the power consumption table 301 for each instruction.
[ΜW / MHz] is required. Then, the cache unit power consumption calculation processing 10 is performed by the power consumption calculation processing 107.
100 [μW / MHz] obtained in step 4 and 50 [μW / MHz] obtained in the CPU unit power consumption calculation processing 106.
Are added, and 150 [μW / MHz] is obtained as the power consumption in cycle 1. Next, it is determined whether or not the code of the simulation end condition has been reached by the program code end determination processing 108. Since the code has not been reached in this case, the cycle number is set to 2 in the execution cycle update processing 109, and the program counter register is also advanced by one. And
The next instruction code 412 is fetched in the instruction reading processing 103. Hereinafter, the processing from the instruction reading processing to the execution cycle updating processing 109 is repeated until the code of the end condition is reached. FIG. 6 shows the result.

In FIG. 6, reference numeral 601 denotes the number of cycles;
Reference numeral 2 denotes an executed instruction, and reference numeral 603 denotes power consumed by the CPU unit. Reference numeral 604 denotes an operation of the cache unit in the instruction fetch in the instruction read 703.
"Hit" represents a hit. Reference numeral 605 denotes the power consumption obtained from the power consumption information for each cache operation in accordance with the cache operation of 604, 606 denotes the operation of the cache unit when a bus access occurs due to the executed instruction, and "R miss" , "R hit" indicates a read hit, "W miss" indicates a write miss, "W hit" indicates a write hit, and a blank indicates no bus access. Reference numeral 606 denotes the power consumption of the entire processor obtained by adding the power consumptions of 603 and 605.

When the simulation termination condition code is reached, the power consumption output processing 110 outputs a simulation result of the power consumption to the display device 1501 or to the storage means 1504.

As described above, according to the embodiment of the present invention, the power consumption simulation method according to the first or second aspect of the present invention allows each of the power consumption For the instruction and the operation state of the cache unit, the power consumption information for each instruction and the power consumption information for each cache operation are stored. be able to. In particular, the invention according to claim 2 provides a simulation method of power consumption at an architectural level that is optimal for a processor having an instruction cache because hits and misses are considered as power consumption for each cache operation. be able to.

In this embodiment, a simple table format is used as power consumption information for each cache operation.
It goes without saying that the same effect can be obtained even if the function is defined as a function depending on whether the cache operation is a hit or a miss.

(Second Embodiment) In a second embodiment, the invention according to claims 1 and 3 will be described with reference to the drawings.

FIG. 7 is a flowchart showing the flow of processing when a simulation of the power consumption simulation method according to the present embodiment is executed. In FIG.
Is the CP of the processor model that simulates the instruction operation
This is initialization processing for setting internal variables and the like of the U core unit and the cache memory unit to initial values. Reference numeral 702 denotes a program reading process for reading the program code given to the processor model to be simulated, and setting the position of the instruction to start the simulation and the position of the instruction to end the simulation. 703 is an instruction reading process for reading an instruction to be executed by the processor model in the current execution cycle from the given program code. Since the instruction is read from the CPU unit via the cache memory, the simulation of the operation of the cache unit is also performed here. Reference numeral 704 denotes a first cache unit power consumption calculation process for calculating the power consumed by the cache unit from the power consumption information for each cache operation for the read process in accordance with the operation of the cache unit simulated in the instruction reading process 703. An instruction execution process 705 simulates a processor operation of the instruction read in the instruction read process 703. Reference numeral 706 denotes CPU unit power consumption calculation processing for obtaining power consumption corresponding to the instruction simulated in the instruction execution processing 705 from the power consumption information for each instruction. 7
07 is a command simulated in the instruction execution processing 705, when a data access bus access occurs.
When the data access is a write, the power consumed by the cache unit is based on the power consumption information for each cache operation for the write process, and when the data access is a read, the power consumption is based on the power consumption information for each cache operation for the read process. Is a second cache unit power consumption calculation process for calculating 708 denotes a first cache unit power consumption calculation process 7
04, a CPU unit power consumption calculation process 706, and a power consumption calculation process of calculating the power consumption consumed in the current execution cycle by the processor model from the power consumption obtained in the second cache unit power consumption calculation process 707. 709
Is a program code end judging process for judging whether the program code to be simulated is ended based on the end instruction position set by the program reading process 702. 710 is an execution cycle update process for advancing the execution cycle for performing the simulation by one when it is determined in the program code end determination process 709 that the simulation of the program code is not completed. Return The process of the next execution cycle is continued. Reference numeral 711 denotes a power consumption output process for outputting information on the power consumption calculated in the power consumption calculation process 708 when the program code to be simulated by the program code end determination process 709 has finished.

As the instruction set of the processor to be simulated, the same instruction set as that used in the first embodiment shown in FIG. 2 is used as an example.

FIG. 8 shows power consumption information for each instruction of a processor to be simulated. Reference numeral 801 denotes a power consumption table for each instruction, which stores a power consumption value when the instruction is executed once for each instruction defined in the instruction table 801.

As a program executed by the processor to be simulated, the program used in the first embodiment shown in FIG. 4 is used as an example.

FIG. 9 shows an example of power consumption information for each cache operation. Reference numeral 901 denotes a power consumption table for each cache operation. A cache operation 902 includes a write process and a read process, and a hit and a miss are defined for each. The power consumption information for each cache operation for write processing is 910, and the power consumption information for each cache operation for read processing is 911.
A power consumption table 90 for each cache operation is obtained in advance by a circuit simulator or the like for each cache operation.
1 is stored. Here, the power consumption information for each write operation cache operation is 100 at the time of hit.
[ΜW / MHz], 80 [μW / MHz] at the time of a miss, and 20 [μW / MHz] at the time of a hit and 100 at the time of a miss as the power consumption information for each cache operation for read processing.
The value of [μW / MHz] is stored.

The same hardware configuration as that of the first embodiment shown in FIG. 15 is used as a hardware configuration diagram of a computer that executes the simulation processing according to the present embodiment.

Hereinafter, the method of simulating power consumption according to the present embodiment will be described in detail with reference to the example shown in FIG.

In an initialization process 701, initialization for executing a program is performed. Here, the CPU unit of the processor model and various registers of the cache memory unit are set. It is assumed that the contents of the memory are set to 2 for [80] and 5 for [A0]. Program reading processing 7
In 02, the program code 401 is read into the storage means, and the program counter register is set so as to start the execution of the program from 411. Further, it is set so that the execution of the program is terminated when the number reaches 420. In the instruction reading process 703, an instruction indicated by the program counter register is fetched. In this case, the LD instruction 411 is fetched via the cache, but the cache accesses the address for the first time, so the cache misses. Then, since the instruction reading is a reading process, the first cache unit power consumption calculation process 704 uses the power consumption information 910 for each cache operation for the reading process to calculate 100 [μW
/ MHz] is required. Here, the calculation of the power consumption is a simple process of simply subtracting the power consumption value of the corresponding cache operation from the power consumption table 901 and is easily and quickly calculated. Next, by the instruction execution processing 705, the LD instruction 4
11 is simulated and the memory address [8
0] is read into the register reg0. next,
From the power consumption table 801 for each instruction, 20 [μW /
MHz]. Next, in an instruction execution process 705,
When a bus access occurs, the second cache unit power consumption calculation processing 707 determines the power consumption of the cache operated by the bus access. In the LD instruction, a read bus access occurs, access to the address [80] is started from the start of the program, and a cache miss occurs. ] Is required. Then, in the power consumption calculation processing 708, the 100 calculated in the first cache unit power consumption calculation processing 704 is calculated.
[ΜW / MHz], 20 [μW / MHz] obtained in the CPU unit power consumption calculation processing 706, and 100 [μW] obtained in the second cache unit power consumption calculation processing 707.
/ MHz], and 220 [μW / MHz] is obtained as the power consumption in cycle 1. Next, it is determined by the program code end determination processing 709 whether or not the code of the simulation end condition has been reached. In this case, since the code has not been reached, the cycle number is set to 2 in the execution cycle update processing 710 and the program counter register is also advanced by one. And the next instruction code 412 is
Fetched at 3. Hereinafter, the processing from the instruction reading processing to the execution cycle updating processing 710 is repeated until the end condition code is reached. FIG. 10 shows the result.

In FIG. 10, 1001 is the number of cycles,
1002 is an executed instruction, and 1003 is power consumed by the CPU unit. Reference numeral 1004 denotes an operation of the cache unit in the instruction fetch in the instruction read 703, where “R miss” indicates a read miss and “R hit” indicates a read hit. 1005 is the power consumption obtained from the power consumption information for each cache operation according to the cache operation of 1004, 1006 is the operation of the cache unit when a bus access is caused by the executed instruction, and "R miss" is a read error. , "R hit" indicates a read hit, "W miss" indicates a write miss, "W hit" indicates a write hit, and a blank indicates no bus access. 1007
Is power consumption obtained from power consumption information for each cache operation when a bus access occurs in 1006;
Is the power consumption of the entire processor obtained by adding the power consumptions of 1003, 1005, and 1007.

When the simulation end condition code is reached, the power consumption output processing 711 outputs a simulation result of the power consumption to the display device 1501 or to the storage means 1504.

As described above, according to the embodiment of the present invention, by the power consumption simulation method according to the first or third aspect of the present invention, each of the previously obtained respective The power consumption information for each instruction and the cache operation is stored in the power consumption information for each instruction and the cache operation for the operation state of the cache unit. be able to. In particular, in the invention according to claim 3, since power consumption for each cache operation is provided for writing and reading, simulation of power consumption at an architectural level optimal for a processor with an instruction / data cache of a unified type is provided. A method can be provided.

In this embodiment, a simple table format is used as power consumption information for each cache operation.
It goes without saying that the same effect can be obtained even if the function is defined as a function depending on whether the cache operation is a hit or a miss.

(Third Embodiment) In a third embodiment, the invention according to claims 1 and 4 will be described with reference to the drawings.

FIG. 7 is a flowchart showing the flow of processing when a simulation of the power consumption simulation method according to the present embodiment is performed. This flowchart is the same as the flowchart used in the second embodiment.

As the instruction set of the processor to be simulated, the same instruction set as that used in the first embodiment shown in FIG. 2 is used as an example.

As the power consumption information for each instruction of the processor to be simulated, the same information as that used in the second embodiment shown in FIG. 8 is used as an example.

As the program executed by the processor to be simulated, the program used in the first embodiment shown in FIG. 4 is used as an example.

FIG. 11 shows an example of power consumption information for each cache operation according to the present embodiment. Reference numeral 1101 denotes a power consumption table for each cache operation. Reference numeral 1102 denotes power consumption information for each instruction cache operation.
103 is power consumption information for each data cache operation. The cache operation 1104 includes a hit and a miss for the instruction cache, a write process and a read process for the data cache, and defines a hit and a miss for each. Each cache operation is obtained in advance by a circuit simulator or the like, and stored in the power consumption table 1101 for each cache operation. Here, the power consumption information for each instruction cache operation is 30 [μW / MH] at the time of hit.
z], 120 [μW / MHz] at the time of miss, 100 [μW / MHz] at the time of hit, 80 [μW / MHz] at the time of miss, and read processing as power consumption information for each cache operation for write processing for data cache. Power consumption information for each cache operation
[ΜW / MHz], and a value of 90 [μW / MHz] at the time of mistake.

The same hardware configuration as that of the first embodiment shown in FIG. 15 is used as the configuration diagram of the computer that executes the simulation processing according to the present embodiment.

Hereinafter, the method of simulating power consumption according to the present embodiment will be specifically described with reference to the follow-up of FIG.

In the initialization processing 701, initialization for executing a program is performed. Here, the CPU unit of the processor model and various registers of the cache memory unit are set. It is assumed that the contents of the memory are set to 2 for [80] and 5 for [A0]. Program reading processing 7
In 02, the program code 401 is read into the storage means, and the program counter register is set so as to start the execution of the program from 411. Further, it is set so that the execution of the program is terminated when the number reaches 420. In the instruction reading process 703, an instruction indicated by the program counter register is fetched. In this case, the LD instruction 411 is fetched via the cache, but the cache accesses the address for the first time, so the cache misses. Since the instruction reading is a reading process, the first cache unit power consumption calculating process 704 obtains, based on the power consumption information 1102 for each cache operation for the instruction cache, 120
[ΜW / MHz] is required. Here, the calculation of the power consumption is a simple process of simply subtracting the power consumption value of the corresponding cache operation from the power consumption table 1101, and is easily and quickly calculated. Next, L by instruction execution processing 705
The operation of the D instruction 411 is simulated, and the value 2 of the memory address [80] is read into the register reg0.
Next, according to the CPU unit power consumption calculation processing 706, the power consumption table 801 corresponding to each instruction indicates that 20
[ΜW / MHz] is required. Next, instruction execution processing 7
At 05, when a bus access occurs, the second cache unit power consumption calculation processing 707 determines the power consumption of the cache operated by the bus access. In the LD instruction, a read bus access occurs, and the address [80]
Is accessed from the beginning of the program, and the cache misses. In the second cache unit power consumption calculation processing 707, data access is performed, and the data cache operates. Therefore, the power consumption is calculated from the power consumption information 1103 for each data cache operation. In this case, because of a mistake in reading, 90 [μW / M
Hz] is required. Then, the power consumption calculation processing 708
As a result, 120 [μW / MHz] obtained in the first cache power consumption calculation processing 704, 20 [μW / MHz] obtained in the CPU power consumption calculation processing 706, and the second cache power consumption calculation 90 [μW / MHz] obtained in process 707 is added, and 230 [μW / M] is added.
Hz] is obtained as the power consumption in cycle 1. Next, it is determined by the program code end determination processing 709 that the code of the simulation end condition has been reached. In this case, the code has not been reached. Then, the next instruction code 412 is fetched in the instruction read processing 703. Hereinafter, the processing from the instruction reading processing to the execution cycle updating processing 710 is repeated until the end condition code is reached. FIG. 12 shows the result.

In FIG. 12, reference numeral 1201 denotes the number of cycles;
Reference numeral 1202 denotes an executed instruction, and reference numeral 1203 denotes power consumed by the CPU unit. Reference numeral 1204 denotes an operation of the cache unit in the instruction fetch in the instruction read 703, where "R miss" indicates a read miss and "R hit" indicates a read hit. Reference numeral 1205 denotes the power consumption obtained from the power consumption information for each cache operation in accordance with the cache operation of 1204; 1206, the operation of the cache unit when a bus access occurs due to the executed instruction; , "R hit" indicates a read hit, "W miss" indicates a write miss, "W hit" indicates a write hit, and a blank indicates no bus access. 1207
Are power consumption obtained from power consumption information for each cache operation when a bus access occurs in 1206,
Is the power consumption of the entire processor obtained by adding the power consumptions of 1203, 1205, and 1207.

When the simulation end condition code is reached, the power consumption output processing 711 outputs a simulation result of the power consumption to the display device 1501 or to the storage means 1504.

As described above, according to the embodiment of the present invention, by the power consumption simulation method according to the first or fourth aspect of the present invention, each of the previously determined respective values before the simulation is executed. The power consumption information for each instruction and the cache operation is stored in the power consumption information for each instruction and the cache operation for the operation state of the cache unit. be able to. In particular, in the invention according to claim 4, since the power consumption for each cache operation is provided for the instruction cache and the data cache, the power consumption at the architectural level optimal for the Harvard type processor with the instruction / data cache is provided. A simulation method can be provided.

In this embodiment, a simple table format is used as power consumption information for each cache operation.
It goes without saying that the same effect can be obtained even if the function is defined as a function depending on whether the cache operation is a hit or a miss.

(Fourth Embodiment) In a fourth embodiment, the invention according to claim 10 will be described with reference to the drawings.

As the configuration diagram of the hardware of the computer that executes the simulation processing according to the present embodiment, the same configuration as that of the first embodiment shown in FIG. 15 is used.

FIG. 13 is a flowchart showing the flow of processing when a simulation of the power consumption simulation method according to the present embodiment is executed. In FIG. 13, 1
Reference numeral 301 denotes initialization processing for setting internal variables and the like of a CPU core unit and a cache memory unit of a processor model for simulating an instruction operation to initial values. Reference numeral 1302 denotes a program reading process for reading the program code given to the processor model to be simulated and setting the position of the instruction to start the simulation and the position of the instruction to end the simulation. Reference numeral 1303 denotes an instruction reading process for reading an instruction to be executed by the processor model in the current execution cycle from the given program code. Since the instruction is read from the CPU unit via the cache memory, the simulation of the operation of the cache unit is also performed here. 1304 is an instruction reading process 130
3 is a first cache unit operation saving process of outputting the simulated operation of the cache unit and the current current cycle to the storage unit 1504. Reference numeral 1305 denotes an instruction execution process for simulating the processor operation of the instruction read in the instruction reading process 1303. Reference numeral 1306 denotes a CPU unit operation storage process for outputting the type of the instruction simulated in the instruction execution process 1305 and the current cycle to the storage unit 1504. Reference numeral 1307 denotes a second cache unit operation storing process for outputting the generated cache operation and the current cycle to the storage unit 1504 when a bus access for data access occurs by an instruction simulated in the instruction execution process 1305. Reference numeral 1308 denotes a program code end determining process for determining whether the program code to be simulated has ended based on the end instruction position set by the program reading process 1302.
An execution cycle update process 1309 advances the execution cycle for performing the simulation by one when it is determined in the program code end determination process 1308 that the simulation of the program code has not been completed. Return The process of the next execution cycle is continued. Reference numeral 1310 denotes a first cache operation saving process 1304 and a CPU unit operation saving process 130 when the program code to be simulated by the program code end determining process 1308 has ended.
6 and the second cache operation storing process 1307, the CP for each cycle stored in the storage unit 1504
This is a power consumption calculation process for obtaining the power consumption when a given program code is executed from the operation of the U unit, the operation of the cache unit, the power consumption for each instruction, and the power consumption for each cache operation.

As the instruction set of the simulated processor, the same instruction set as that used in the first embodiment shown in FIG. 2 is used as an example.

As the power consumption information for each instruction of the processor, the same information as that used in the second embodiment shown in FIG. 8 is used as an example.

As the program executed by the processor to be simulated, the program used in the first embodiment shown in FIG. 4 is used as an example.

As power consumption information for each cache operation, the information used in the second embodiment shown in FIG. 9 is used as an example.

Hereinafter, a method of simulating power consumption according to the present embodiment will be described in detail by taking as an example a case where the program 401 is executed based on the follow-up of FIG.

In an initialization process 1301, initialization for executing a program is performed. Here, the CPU unit of the processor model and various registers of the cache memory unit are set. The contents of the memory are [80] = 2, [A0]
Is set to 5. In the program reading process 1302, the program code 401 is read into the storage means, and the program counter register is set so that the program execution is started from 411. Also, 42
It is set so that the execution of the program is terminated when it reaches 0. In the instruction reading process 1303, the instruction pointed to by the program counter register is fetched. in this case,
Although the LD instruction 411 is fetched via the cache, the cache accesses this address for the first time, so the cache misses. Then, in the first cache unit operation storage processing 1304, the fact that a read error occurred in the fetch in cycle 1 is stored in the storage unit 1504. Next, LD instruction 411 is executed by instruction execution processing 1305.
Is simulated, and the value 2 of the memory address [80] is read into the register reg0. Next, CPU
The execution of the LD instruction in cycle 1 is stored in the storage unit 1305 by the unit operation storage processing 1306. Next, when a bus access occurs in the instruction execution processing 1305, the cache operation generated by the second cache unit operation storage processing 1307 is stored in the storage unit.
In the LD instruction, a read bus access occurs, access to the address [80] is started from the start of the program, and a cache miss occurs. Therefore, cycle 1
The fact that the bus access of the data has occurred and a mistake has occurred is stored in the storage means 1504. Next, it is determined by the program code end determination processing 1308 that the code of the simulation end condition has been reached. In this case, however, the code has not been reached. Proceeded,
The next instruction code 412 is fetched in the instruction reading processing 1303. Hereinafter, the processing from the instruction reading processing to the execution cycle updating processing 1309 is repeated until the code of the end condition is reached.

FIG. 14 shows the calculation process. 1401 is the number of cycles, 1402 is CPU unit operation saving processing 1306
1403 is a cache operation in the fetch saved in the first cache unit operation saving process 1304, and 1404 is a read or write process of the data saved in the second cache unit operation saving process 1307. This is the operation of the cache. When it is determined in the program code end determination processing 1308 that the code of the simulation end condition has been reached, the data of the portion 1410 is stored in the storage unit 1504. This one
The power consumption calculation processing 1310 from the information of 410
402 executed instructions and power consumption table 8 for each instruction
CPU power consumption from 1 to 1405, cache operation at the time of fetch of 1403, and power consumption information at the time of instruction fetch from 1901 to 1406 from the power consumption information 901 for each cache operation,
The power consumption at the time of data access of 1407 is obtained from the cache operation at the time of data access at 1404 and the power consumption information 901 for each cache operation, and the total power consumption 1408 is obtained from the power consumption of 1405, 1406, and 1407. In power consumption calculation processing 1310, when these processings are performed for all cycles, calculation of 1411 is performed.

For example, in cycle 1, since the LD instruction is stored, the power consumption information
[ΜW / MHz], cache operation 1 at instruction fetch
Since an “R miss”, that is, a miss in reading is stored as 403, 100 [μW / MHz] is obtained from the power consumption information 901 for each cache operation, and an “R miss”, that is, a reading miss is stored as the cache operation 1404 during data access. Therefore, 100 [μW / MHz] is obtained from the power consumption information 901 for each cache operation.
[ΜW / MHz] is required. The obtained power consumption is output to the display device 1501 as a result of the simulation of the power consumption or to the storage unit 1504.

As described above, according to the embodiment of the present invention, by the power consumption simulation method according to the tenth aspect, each instruction and the cache unit which are obtained in advance before the simulation is executed. For the operation state, the power consumption information for each instruction and the power consumption information for each cache operation are stored, and during the simulation, the instruction and the cache operation executed in each cycle are stored in the storage unit. Dynamic power consumption during operation can be obtained from the operations of the CPU unit and the cache unit saved after the simulation, power consumption information for each instruction, and power consumption information for each cache operation. In the present invention, since the simulation process and the power consumption calculation process can be separated, a commercially available simulator or the like is used. Can be provided.

(Fifth Embodiment) In a fifth embodiment, a power consumption simulation method according to claims 5, 6, 7, and 8 will be described.

FIG. 20 is a flowchart showing a processing flow when executing the simulation of the power consumption simulation method according to the present embodiment. Reference numeral 2001 denotes initialization processing for initializing each unit in a circuit to be simulated. For the bus master unit, this is an initialization process for initializing an internal state for simulating an instruction operation and initializing means for storing power consumption calculated by simulation of the model. 2002 reads the program code given to the bus master to be simulated, and sets the position of the instruction to start the simulation and the position of the instruction to end the simulation. Reference numeral 2003 denotes processing for reading an instruction to be executed by the bus master model in the current execution cycle from a given program code. Reference numeral 2004 denotes a process of reading information on an address, a bit width, a transfer mode, and one of read and write accesses in the state of a bus model in reading an instruction. A power consumption calculation process 2005 calculates the power consumption from the parameters extracted from the simulation model in the above-described 2004 and stores the power consumption along with the execution cycle being executed. An execution process 2006 simulates the operation of the read instruction.
Is the address of the state of the bus model during instruction execution, bit
This is a process of reading information on the width, the transfer mode, and whether the access is read or write access. 2008
Is a power consumption calculation process of calculating the power consumption from the parameters extracted from the simulation model in 2007 and storing the calculated power consumption together with the execution cycle being executed. 2009 is an end determination process for determining whether the program code to be simulated has ended based on the end instruction position set by 2002.

FIG. 21 shows an example of a circuit to be simulated. In the figure, reference numerals 2101 and 2102 denote device bus masters 1 and 2 which can generate a read or write bus access process.
03 is a device bus adapter for connecting a plurality of buses.

Also, 2107 and 2108 are buses,
It is composed of control signal lines, address signal lines, and data signal lines. 2107 is a bus master 2101 or 21
02 is a main bus. Reference numeral 2108 denotes a sub-bus connected to the main bus via a bus adapter 2103. Bus slaves 2104, 2105, and 2106 are accessed by the bus master, and are connected to the main bus or the sub bus. 21
Reference numeral 04 denotes a storage device capable of storing a plurality of pieces of data distinguished by addresses.
07. Reference numerals 2105 and 2106 denote a functional block 1 and a functional block 2, which have a built-in storage circuit therein and can read and write data via a connected bus. Reference numeral 2109 denotes an external bus interface connected to the main bus, which is connected to an external storage device 2110 outside the chip.

FIG. 22 shows an example of an address configuration in the circuit example shown in FIG. In FIG. 22, an area indicated by 2202 is the entire address area in the present circuit example, and is constituted by address areas 2203, 2204, 2205, and 2206. Address area 2203 is bus master 2
The internal storage area 101 and the address area 2204 are a functional block 1 (2105) and a functional block 2 (2106).
The internal storage area and address area 2205 of the storage device 21
A storage area 04 and an address area 2206 indicate storage areas of the external storage device 2110, respectively. Reference numeral 2201 denotes a boundary of the storage area in the address number, and 0 to 100 indicates the storage area 2203, and 100 to 200
Is the storage area 2204, 200 to 300 is the storage area 2205, and 300 to 500 is the storage area 22.
06 is the address number.

FIGS. 23, 24 and 25 are diagrams showing an example of power consumption information for the circuit shown in FIG. 20 in the present embodiment. FIG. 23 shows the power consumption information of the address areas 2203, 2204, 2205, and 2206 in FIG.
02 is one bus cycle for write access, 8 bi
Power consumption information per t. FIG. 24 shows power consumption information consumed inside the bus master 1 and the bus master 2 in FIG. FIG. 25 shows power consumption information consumed inside the storage device 2104 which is a bus slave and the function blocks 1 and 2.

In this example, the first one in the continuous transfer is
The first transfer is equivalent to a single transfer.

These power consumptions are evaluated in advance by a gate level simulation or a circuit simulation based on data obtained by realizing each block at a gate level or a transistor level before the simulation, and the power consumption is obtained. Things.

FIG. 16 shows an example of the instruction set of the bus master 1 to be simulated. The instruction LDR is a data transfer instruction for single-transferring data with a 32-bit width from the data in the storage area specified by the address to the storage area specified by the address in the register a or the register b. A single transfer is a transfer in which access starts and ends without incrementing the address. The instruction LDRB is a data transfer instruction for single-transferring data in 8-bit width from data in a storage area specified by an address to a storage area specified by an address in a register a or a register b. Instruction L
This is a data transfer instruction for single-transferring data with a 16-bit width from the data in the storage area specified by the DRH address to the storage area specified by the address in the register a or the register b. The instruction STR stores data in the storage area specified by the address from the register a or the register b in 32 bits.
This is a data transfer instruction for single transfer in t width. The instruction STRB is a data transfer instruction for single-transferring data from a register a or a register b to a storage area specified by an address with a width of 8 bits. The instruction STRH stores data in the storage area specified by the address from the register a or the register b in 16 bits.
This is a data transfer instruction for single transfer in t width. The instruction LDM is a data transfer instruction for sequentially transferring data in a storage area starting with an address number designated by an address to a plurality of registers from a to a in a 32-bit width. The continuous transfer is a transfer in which the address is incremented from the start to the end of the transfer and data of a plurality of word lengths is transferred in one transfer. The instruction LDMB is a data transfer instruction for sequentially transferring data of a storage area starting from an address number designated by an address to a plurality of registers from a register a to a register b in an 8-bit width. Instruction L
DMH is a data transfer instruction for sequentially transferring data in a storage area starting from an address number designated by an address to a plurality of registers from register a to register b in a 16-bit width. The instruction STM is a data transfer instruction for sequentially transferring data at a 32-bit width from a plurality of registers from the register a to the register b to a series of storage areas starting from a storage area specified by an address. Instruction S
TMH is a data transfer instruction for sequentially transferring data with a 16-bit width to a series of storage areas starting from a storage area designated by an address from a plurality of registers from a register a to a register b. The instruction STMB is a data transfer instruction for sequentially transferring data with a 8-bit width from a plurality of registers from the register a to the register b to a series of storage areas starting from a storage area specified by an address. Instruction N
The OP does nothing.

FIG. 17 shows an example of a program executed by the bus master to be simulated.
, One column represents one instruction, and is described in order of the instruction, the destination, and the source from the left.

FIG. 18 shows addresses and instructions in which the program code shown in FIG. 17 is stored in the storage device 2104 of FIG.
The code corresponding to “RHreg # a 350” is stored, the line 1802 stores the code corresponding to “STRB 120 reg # a” at the address 201, and the line 1803 stores the code “LDM [reg # a]” at the address 202. reg # b] 250 "is stored.

Hereinafter, the method of simulating power consumption according to the present embodiment will be specifically described based on the flow of the processing shown in FIG. 20, using the case where the program shown in FIG. 17 is executed as an example. In this example, reg # a and reg # b
Is a 32-bit register, and reg # b is 4 words away from reg # a. It is assumed that the program code shown in FIG. 17 is executed by the bus master 1, and the instruction fetch from the bus master 1 and the bus master 2 is 32 bi.
Description will be made assuming that the transfer is performed by t single cycle transfer.

In the initialization processing of 2001, initialization for executing a program is performed. In the present embodiment, the register in the bus master 1 indicating the execution position of the instruction is set to a value indicating the address 200. In the program reading process of 2002, a program to be simulated is read, read into the storage device 2104, and the program code is stored at the address shown in FIG.

In reading the instruction of 2003, the storage device 2
The instruction code stored at address 200 is read from 104.

In step 2004, the state of the bus access in step 2003 is read. In this case, the address area 2204
, Which is a 32-bit width read, and a single access, and is read to be completed in one bus cycle.

In step 2005, the power consumption value is calculated from the bus access state read in step 2004 and the power consumption information shown in FIGS. Since the access of 0.3 μW / MHz / 8 bits and 32 bits was completed by one bus access from 2302 in FIG. 23, 1.2 μW, and the power consumption in the bus connection part of the bus master 1, 2 in FIG.
25 and 1 μW from 2501 in FIG.
W, a total of 2.3 μW.

In 2006, the instruction 1701 read in 2003 is executed.

In 2007, the bus state at the time of instruction execution is read from the simulation model, and the address area 220 is read.
It is calculated that the data is transferred from 6 to reg # a with a single 8-bit width and read.

In 2008, the power consumption in 2006 is calculated based on the bus information read in 2007, the power consumption information of 0.3 μW / Hz / 8 bits is read out from 2303 in FIG.
From 504, 0.1 μW is read as power consumption information, and is calculated as 0.5 μW as the total power consumption.

In 2009, the program code 170
Since 1 is not the end position, the instruction cycle is advanced by 1 to 20
Returning to 03, 2003 is processed as the second instruction cycle.

In the second execution cycle, 2
At 003, an instruction code corresponding to 1802 is read from the storage device 2104.

In 2004, the state of the bus access at the time of reading the instruction is read. In this case, it is read that the access to the address area 2204 is a 32-bit width read, a single access, and that the read is completed in one bus cycle.

In 2005, a power consumption value is calculated from the bus access state read in 2004 and the power consumption information shown in FIGS. Since the access of 0.3 μW / MHz / 8 bits and 32 bits has been completed by one bus access from 2301 in FIG.
25 and 1 μW from 2501 in FIG.
W, a total of 2.3 μW.

In 2006, the instruction 1702 read in 2003 is executed.

In 2007, the bus state at the time of executing the instruction is changed from the simulation model to the address area 220 from reg # a.
4 is read as a single transfer with a 16-bit width.

In 2008, the power consumption in 2006 is calculated based on the bus information read in 2007, the power consumption information of 0.6 μW / Hz / 8 bits is read from 2301 in FIG. 23, and 1 μW from 2401 is 25
02, 0.2 μW is read as power consumption information,
It is calculated as 2.4 μW as the total power consumption.

In 2009, the program code 170
Since 1 is not the end position, the instruction cycle is advanced by 1 to 20
Returning to 03, 2003 is processed as the third instruction cycle.

In the third execution cycle, 2
At 003, an instruction code corresponding to 1803 is read from the storage device 2104.

In 2004, the state of the bus access at the time of reading the instruction is read. In this case, it is read that the access to the address area 2204 is a 32-bit width read, a single access, and that the read is completed in one bus cycle.

In step 2005, the power consumption value is calculated from the bus access state read in step 2004 and the power consumption information shown in FIGS. Since the access of 0.3 μW / MHz / 8 bits and 32 bits has been completed by one bus access from 2301 in FIG.
25 and 1 μW from 2501 in FIG.
W, a total of 2.3 μW.

In 2006, the instruction 1702 read in 2003 is executed.

In 2007, the bus state at the time of executing the instruction is read from the simulation model. reg # a to r
A series of registers up to eg # b are four words, and four words are read out from the address number 250, that is, the address area 2005, by continuous transfer with a 32-bit width.

In 2008, the power consumption in 2006 is calculated based on the bus information read out in 2007. One transfer of 0.3 μW for single transfer and three transfers for 0.1 μW of continuous transfer are performed from 2302 in FIG. Multiplied by 4 for access. 1 μW from 2401 and 0.1 μW from 2501 are read as power consumption information, and are calculated as 5.7 μW as total power consumption information.

FIG. 19 shows the program 17 by the above method.
This is the result obtained by simulating the execution of S.01.

According to the above embodiment, claim 5
According to the power consumption simulation method of the present invention, before executing the simulation, a power value consumed when a bus access is performed to a predetermined address area is stored as power consumption information for each address area. In addition, at the same time as simulating the instruction operation for the program code given at the time of executing the simulation, a power consumption value corresponding to the bus access executed based on the power consumption information for each access address area is obtained and consumed in the simulated program. The power consumption value can be obtained for each cycle. Normally, the address area reaches 4 GB in a 32-bit processor, but the power consumption information for each address area can be easily searched by holding it in a table or the like in a computer, so that the power consumption can be estimated quickly. It can be carried out.

Further, when the simulated bus master according to the sixth aspect of the present invention can access a plurality of bit widths, the power consumption is calculated in consideration of the bit width at the time of the bus access. It is also possible to accurately estimate power consumption even for a bus master that can access with a plurality of bit widths.

In the simulated bus access according to the seventh aspect of the present invention, power consumption information for read access and write access is distinguished,
High-precision power consumption estimation can be performed for both read and write bus accesses.

In the simulated bus access according to the eighth aspect, by storing power consumption information for each transfer mode, a more accurate estimate can be made for a bus having a plurality of transfer modes. It is possible to do.

Furthermore, in this embodiment, for simplicity of explanation, an ordinary processor is merely used as a bus master. However, actually, the bus master is actually a processor.
It is needless to say that the power consumption can be estimated with higher accuracy by combining with the method in consideration of the cache described in the third embodiment, the third embodiment and the fourth embodiment.

[0115]

As described above, according to the first, second, third, fourth, ninth, and tenth aspects of the present invention, the instruction of the processor is executed before executing the simulation. For each instruction of the set and a plurality of operations of the cache memory, the power consumed when each instruction is executed is determined from the simulation result at the circuit level or the gate level or from the evaluation result of the actual chip actually manufactured for each instruction. Power consumption information and power consumption information for each cache operation, and simulates an instruction operation and a cache operation for a program code given during simulation execution, and a value of power consumption corresponding to the executed instruction. From the power consumption information for each instruction, the power consumption value corresponding to the executed cache operation is calculated based on the power consumption information for each cache operation. Retrieved from, by going aggregated at predetermined time intervals, determining the time transition of power processor unit consumes when operating in a given program code. Here, the number of cycles executed according to the program code is usually a huge number of thousands or millions of cycles or more, but the power consumption information for each instruction can be easily stored in a computer in a table format or the like. It is possible to search, and also to calculate the power consumption for each fixed time, it is possible to perform the calculation at high speed by simple integration and average calculation. Therefore, while simulating the circuit operation of a semiconductor integrated circuit including a processor having a cache memory,
A simulation method for quickly estimating the power consumption can be provided.

In particular, according to the second aspect of the present invention, since the power consumption is calculated by distinguishing between the operation when the cache hits and the operation when the cache misses, the optimum power consumption for the processor having the instruction cache is calculated. Simulation can be realized.

According to the third aspect of the present invention, it is possible to distinguish between a case where the cache operation is a write operation and a case where the cache operation is a read operation, and that the cache is hit for each of the write operation and the read operation. Since the power consumption is calculated by discriminating between the operation of (1) and the operation in the case of a mistake, an optimal power consumption simulation can be realized for a processor having a unified instruction / data cache.

Further, according to the present invention, power consumption information for instruction cache and data cache is provided.
In order to calculate the power consumption when the instruction cache hits and misses, and in the data cache, the write process and the read process are distinguished, and the cache hit and miss are distinguished for each.
An optimal power consumption simulation can be realized for a processor having a Harvard-type instruction / data cache.

According to the fifth, sixth, seventh, eighth, ninth, and tenth aspects of the present invention, the individual bus masters and buses in the circuit before the simulation is executed. For the slave and the bus unit, the power consumed per bus cycle is obtained from the circuit-level or gate-level simulation or the evaluation result of the actual chip actually produced, and the power consumption information for each bus master, The power consumption information for each bus slave and the power consumption information for each address area are stored in advance. During the simulation, the power consumption information for each bus master, the power consumption information for each bus slave, and the power consumption information for each address area are stored. Power consumption according to the operation state of each bus cycle is searched from the power consumption information, and the power consumption of the entire circuit is obtained from the searched power consumption. Here, the number of bus cycles executed in the simulation is usually a huge number of thousands or millions of cycles or more, but the above-mentioned power consumption information should be stored in a computer in a table format or a function format. Can be easily searched and calculated, and the power consumption for each fixed time can be calculated at high speed by simple integration and average calculation. Therefore, it is possible to provide a simulation method that simulates the circuit operation of a semiconductor integrated circuit in which a bus master and a bus slave are integrated by using a bus, and estimates the power consumption at high speed.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a flow of processing when a simulation is executed according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of an instruction set of a simulated processor according to the first, second, third, and fourth embodiments of the present invention;

FIG. 3 is a diagram showing power consumption information for each instruction of a processor to be simulated according to the first embodiment of the present invention;

FIG. 4 is a diagram illustrating an example of a program executed by a processor to be simulated according to the first, second, third, and fourth embodiments of the present invention;

FIG. 5 is a diagram illustrating an example of power consumption information for each cache operation according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a process and a result of power consumption calculation according to the first embodiment of the present invention.

FIG. 7 is a flowchart showing the flow of processing at the time of executing a simulation in the power consumption simulation method according to the second, third, and fourth embodiments of the present invention;

FIG. 8 is a diagram illustrating power consumption information for each instruction of a processor to be simulated in the second, third, and fourth embodiments of the present invention.

FIG. 9 is a diagram illustrating an example of power consumption information for each cache operation according to the second and fourth embodiments of the present invention.

FIG. 10 is a diagram showing a process and a result of power consumption calculation according to the second embodiment of the present invention.

FIG. 11 is a diagram illustrating an example of power consumption information for each cache operation according to the third embodiment of the present invention.

FIG. 12 is a diagram illustrating a process and a result of power consumption calculation according to the third embodiment of the present invention.

FIG. 13 is a flowchart showing the flow of processing when a simulation is performed in the power consumption simulation method according to the fourth embodiment of the present invention.

FIG. 14 is a diagram illustrating a process and a result of power consumption calculation according to the fourth embodiment of the present invention.

FIG. 15 is a diagram illustrating an example of a hardware configuration diagram of a computer that executes a simulation process according to the present embodiment;

FIG. 16 is a diagram showing an example of an instruction set of a bus master according to the fifth embodiment of the present invention.

FIG. 17 is a diagram showing an example of a program given to a bus master according to the fifth embodiment of the present invention.

FIG. 18 is a diagram illustrating an example of a form in which a program code is stored in a storage area according to the fifth embodiment of the present invention.

FIG. 19 is a diagram illustrating an example of an operation simulation result according to the fifth embodiment of the present invention.

FIG. 20 is a flowchart showing the flow of processing when executing a simulation according to the fifth embodiment of the present invention.

FIG. 21 is a diagram illustrating an example of a circuit to be simulated according to a fifth embodiment of the present invention.

FIG. 22 is a diagram illustrating an example of an address configuration of a circuit to be simulated according to the fifth embodiment of the present invention.

FIG. 23 is a diagram illustrating an example of power information for each address area according to the fifth embodiment of the present invention.

FIG. 24 is a diagram showing an example of power consumption information associated with bus access by a bus master according to the fifth embodiment of the present invention.

FIG. 25 is a diagram showing an example of power consumption information associated with bus access in each peripheral function block according to the fifth embodiment of the present invention.

[Explanation of symbols]

101, 701, 1301 Initialization processing 104, 704, 707, 1304, 1307 Cache part power consumption calculation processing 105, 705 Instruction execution processing 106, 706, 1306 CPU part power consumption calculation processing 107, 708 Power consumption calculation processing 301, 801 Power consumption information for each instruction 501, 901, 1101 Power consumption information for each cache operation 2001 Initialization processing 2002 Program reading processing 2003 Instruction reading processing 2004 Bus state reading processing 2005, 2007 Power consumption calculation processing 2006 Instruction execution processing 2301 Address area, Power consumption information depending on transfer mode and read / write 2302 Address area, transfer mode, power consumption information depending on read / write 2303 Address area, transfer mode, power consumption information depending on read / write

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B005 JJ00 MM01 VV24 5B046 AA08 BA02 JA04 JA05 5F064 AA04 BB09 BB12 HH09 HH12 HH14

Claims (11)

[Claims] 1. A method for simulating the instruction operation of a processor having a cache memory in a computer, wherein the instruction is consumed when each instruction is executed with respect to an instruction set of the processor before execution of the simulation. Power for each instruction, and store it as power consumption information for each instruction. For a plurality of operations of the cache memory, obtain the power consumed for each operation and store it as power consumption information for each cache operation. At the time of executing a simulation for a given program code, at the same time as simulating an instruction operation and a cache operation for each instruction, the CPU core unit corresponding to the instruction being executed based on the power consumption information for each instruction is described. From the power consumption information for each cache operation described above, The power consumption of the cache unit corresponding to the generated cache operation is determined, and the power consumption of the processor when executing the program code is determined from the power consumption of the CPU core unit and the power consumption of the cache unit. A simulation method, characterized in that: 2. The power consumption information for each cache operation is at least power consumption information that distinguishes between an operation when a cache hits and an operation when a cache miss occurs. For each instruction, when the cache hits for the generated bus access, the power consumption of the cache unit is obtained from the power consumption information for the hit operation in the power consumption information for each cache operation. 2. The simulation method according to claim 1, wherein when the cache misses, the power consumption of the cache unit is obtained from the power consumption information of the operation when the miss occurs. 3. The power consumption information for each cache operation is at least power consumption information that distinguishes between a case where a cache operation is a write operation and a case where a cache operation is a read operation, and a write operation and a read operation. Is the power consumption information that distinguishes between the operation when the cache hits and the operation when the cache misses, and the bus access generated for each instruction when the simulation is executed for the given program code. Is a read process or a write process, and determines whether the cache hits or misses, and calculates the power consumption of the cache unit from the corresponding power consumption information of the power consumption information for each cache operation. The simulation method according to claim 1, wherein 4. The power consumption information for each cache operation includes information for an instruction cache and data for a data cache. The power consumption information for each cache operation for an instruction cache includes at least an operation when a cache hit occurs. This is power consumption information that distinguishes the operation in the case of a miss, and the power consumption information for each cache operation for the data cache is at least consumption power that distinguishes between the case where the cache operation is a write operation and the case where the cache operation is a read operation. This is power information and power consumption information that distinguishes between an operation when a cache hits and an operation when a cache miss occurs for each of a write process and a read process. For each instruction, the generated bus access is In this case, it is determined whether or not a cache hit has occurred based on the power consumption information for each cache operation for the instruction cache, and the power consumption of the instruction cache unit is obtained. It is determined whether the generated bus access is a read process or a write process, and whether the cache has hit or missed. Based on the power consumption information for each cache operation for the data cache, the data cache 2. The simulation method according to claim 1, wherein the power consumption of the entire cache unit is obtained from the power consumption of the instruction cache unit and the power consumption of the data cache unit. 5. A method for simulating, in a computer, an architecture-level operation of a circuit in which one or more bus masters and bus slaves are connected by a bus, the method comprising: The consumed power is used as power consumption information for each bus master, the power consumed when the bus slave operates is used as power consumption information for each bus slave, and the address space of the bus is used for each address area. The power consumed by the bus unit at the time of bus access to the address area is stored as power consumption information for each address area, and the bus operation is simulated for each bus access at the time of executing the simulation for the circuit. At the same time as the power consumption information of each bus master. From the power consumption information for each bus slave, the power consumption of the bus slave is obtained.From the power consumption information for each address area, the power consumption of the bus unit corresponding to the address value of the generated bus access is obtained. A simulation method comprising: obtaining power consumption during operation of the circuit from power consumption of the bus master, power consumption of the bus slave, and power consumption of the bus unit. 6. The power consumption information for each address area is at least power consumption information in which a bit width of a bus access is distinguished. 6. The simulation according to claim 5, wherein when the power consumption occurs, the power consumption of the bus unit corresponding to the generated address value of the bus access and the bit width thereof is obtained from the power consumption information for each address area. Method. 7. The power consumption information for each address area is at least power consumption information that distinguishes between a case where a bus access is a read process and a case where a bus access is a write process. When a bus access occurs for each bus access, the address value of the generated bus access and the power consumption of the bus unit corresponding to the read processing or the write processing are obtained from the power consumption information for each address area. 6. The simulation method according to claim 5, wherein: 8. The power consumption information for each address area is at least power consumption information based on a bus transfer mode and a transfer word number. When a bus access occurs, the power consumption of the bus section corresponding to the address value of the generated bus access, the transfer mode, and the number of transfer words is obtained from the power consumption information for each address area. The simulation method according to claim 5. 9. A method in which a processor comprising a CPU core and a cache memory and a bus slave simulates, in a computer, an architecture-level operation of a circuit connected by a bus, wherein: The power consumption of the CPU core is obtained by the method according to claim 1, and the power consumption of the cache is obtained by the method according to any one of claims 2, 3, or 4. The power consumption of the bus unit and the power consumption of the bus slave unit are obtained by at least one of the methods described in claim 5, claim 6, claim 7, and claim 8. From the power consumption, the power consumption of the cache unit, the power of the bus slave unit, and the power consumption of the bus unit, Simulation method and obtains the power consumption during the program code execution. 10. The simulation method according to claim 1, 2, 3, 4, 5, 5, 6, 7, 8, or 9, wherein a simulation is performed. During the simulation, information necessary for the power consumption calculation is stored in the storage device, and after the simulation is performed, the information is obtained by the simulation based on the information necessary for the power consumption calculation stored in the storage device. A simulation method characterized by determining the power consumption of a circuit during circuit operation. 11. The simulation method according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8, claim 9, or claim 10. Recording medium on which is recorded.