JP2000286902A - Signal quality monitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To widen the frequency band of jitter, which can be measured, without adjusting it without using a special device by extracting a clock component from an input signal, distributing a clock, comparing the phase of the clock with that of a clock where a jitter component contained in the clock is suppressed and inputting the output signal level of a phase comparison result. SOLUTION: BPF 23 extracts the clock component of a frequency similar to a signal and a distributor 24 distributes the clock component into two. PLL 25 outputs the clock component of a waveform where the jitter component is suppressed. A mixer 26 compares the phases of the clock components from the distributor 24 and PLL 25. A capacitor 27 removes a DC component from the output signal of the mixer 26 and a peak detector 28 detects a peak. LPF 29 executes integration. The output of LPF 29 is inputted to a comparator 30, it is compared with proper reference voltage Vref and therefore the jitter component can be estimated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit technique for estimating a jitter component contained in a main signal in a communication system, particularly a long-distance transmission system, and monitoring the quality of the main signal from the estimated amount.

[0002]

2. Description of the Related Art In order to measure and detect a jitter component contained in a signal, a conventional example 1 is disclosed, for example, in JP-A-8-2620.
84. FIG. 8 is a diagram showing a configuration of a jitter measuring apparatus having a PLL (Phase Locked Loop) circuit 7 shown in the above-mentioned document. 1 is an input terminal, 2 is a sampler, 3 is an A / D converter, 4 is a memory, 5 is an operation unit, 6 is a display unit, 7 is a PLL circuit, 8 is a phase comparator, 9 is a loop filter, and 10 is a VCO. (Voltage controlled oscillator), 11 is an N frequency divider, 12 is a voltage adder, 13 is a harmonic elimination filter, 1
4 is a phase offset voltage generator.

First, the configuration and operation of a PLL will be briefly described. A PLL generally uses a phase comparator that compares the phases of two input signals, a loop filter that removes unnecessary noise contained in the output voltage, determines the dynamic characteristics of the PLL such as the natural frequency, and oscillates with the output voltage of the loop filter. It is composed of a VCO (Voltage Controlled Oscillator) that oscillates a sine wave signal whose frequency and phase are corrected, and an N divider that outputs a VCO output signal, divides the signal by N, and feeds it back to the phase comparator You. When the jitter measurement signal is input to the phase comparator, the jitter component appearing in the VCO output signal is lower than the natural frequency of the loop filter. Therefore, the PLL has a function of suppressing the jitter component.

Next, the operation of FIG. 8 will be described. The feature of Conventional Example 1 is that a PLL is used as a lamp circuit. One of the two periodic signal waveforms of the jitter measurement signal is input to the phase comparator. The jitter component contained in the output signal of the VCO is suppressed to a natural frequency or lower by the loop filter.

[0005] An output signal of a VCO having very small jitter is input to a sampler, and the input signal is sampled by a signal to be measured. The sampled voltage of the sampler is A / D converted by an A / D converter, and a series of A / D converted digital voltage values are stored in a memory. When a sampling value for a certain period is obtained, an arithmetic unit calculates the jitter component based on this data. In order to measure the jitter with high accuracy, increase the frequency division ratio N of the N frequency divider and set the sampling phase so that the phase of the sine wave becomes ± nπ (n: any integer) by the phase offset voltage generator. Need to adjust.

A conventional example 2 is disclosed, for example, in Japanese Unexamined Patent Application Publication No.
5350. FIG. 9 is a diagram showing a configuration of a jitter detection device having a PLL circuit disclosed in the above document. 10 is a VCO (voltage controlled oscillator), 16 is a frequency multiplier, 17 is a frequency converter, 18 is a mixer,
9 is a filter, 20 is a phase frequency comparator, 21 is a filter for jitter detection, 9 is a loop filter, and 22 is a branch circuit.

Next, the operation of FIG. 9 will be described. The features of the conventional example 2 are that the pull-in range of the PLL can be widened and the jitter can be measured with high sensitivity while using the digital phase frequency comparator for the low frequency band. This is a signal obtained by multiplying the output signal of the VCO by M, and converts the jitter measurement signal to a lower frequency. M
By multiplying, the pull-in range of the PLL circuit 2 is expanded to M-1 times or M + 1 times the frequency variable width of the VCO.

[0008] The output of the frequency conversion circuit and the output signal of the VCO are input to a digital phase comparator for a low frequency band, and a loop is controlled so that the phase of the output signal of the VCO is locked to the phase of the output of the frequency conversion circuit. I do. Since there is no frequency divider at the input of the phase comparator, jitter can be measured with high sensitivity. The measurable jitter frequency band is equal to or higher than the natural frequency of the loop filter and equal to or lower than the input frequency of the phase comparator.

[Problems to be solved by the invention]

The conventional example 1 has a problem that a high-speed sampler is required, and a phase offset adjustment is required for high-accuracy measurement of jitter. In Conventional Example 2, since a digital phase comparator for a low frequency band is used,
The problem is that the measurable jitter frequency band is narrow. An object of the present invention is to extend a measurable jitter frequency band without adjustment without using a special device.

[0010]

A signal quality monitor according to a first aspect of the present invention includes a clock extracting unit that extracts a clock component from an input signal, a clock distribution unit that distributes a clock output from the clock extracting unit, A jitter suppressing unit that suppresses jitter included in the clock output from the clock distribution unit, a phase comparator that receives as input the clock output from the clock distribution unit and the clock output from the jitter suppression unit, Signal quality determining means for receiving the output signal level of the phase comparator as an input.

According to a second aspect of the present invention, there is provided a signal quality monitor for distributing an input signal, a clock extracting means for extracting a clock component included in a signal output from the signal distribution means, A jitter suppressing means for suppressing jitter contained in a signal output from a clock extracting means, a phase comparator receiving a signal output from the signal distributing means and a clock output from the jitter suppressing means as inputs, Signal quality determining means for receiving the output signal level of the device as an input.

According to a third aspect of the present invention, there is provided a signal quality monitor for distributing an input signal, and a frequency multiplier for multiplying the frequency of the signal output from the signal distributor by K (K is an arbitrary natural number). A clock extracting means for extracting a clock component included in a signal output from the signal distribution means, a jitter suppressing means for suppressing a jitter included in a signal output from the clock extracting means, and a frequency multiplier. A phase comparator that receives the output signal and the clock output from the jitter suppression unit, and a signal quality determination unit that receives the output signal level of the phase comparator as an input.

A signal quality monitor according to a fourth aspect of the present invention is a variable gain amplifier for amplifying an input signal by an amplifier having a variable gain, and extracts a clock component included in the signal output from the variable gain amplifier. Clock extraction means, clock distribution means for distributing the clock output from the clock extraction means, jitter suppression means for suppressing jitter contained in the clock output from the clock distribution means, and output from the clock distribution means A phase comparator that receives the output clock and the clock output from the jitter suppression unit, a level detector that detects the level of the signal output from the clock distribution unit, and an output signal level of the phase comparator. Signal quality determining means, wherein the variable gain amplifier responds to a signal output from the level detector. And it is controlled.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 shows the configuration of the signal quality monitor of the present embodiment.
PF (Band Pass Filter), 24 is Distirbutor, 25 is PL
L, 26 are Mixer, 27 is a condenser, 28 is Peak Detec
tor, 29 is LPF (Low Pass Filter), 30 is Comparator
It is. As the BPF 23, the Q value is 1 at the same frequency as the signal.
Distirbutor 24 is a digital I
C, a power divider or a coupler, a PLL 25 having a Q value of the output signal of about 800, a mixer 26 having a maximum operating frequency of about twice the signal frequency,
As the Peak Detector 28, a peak detector whose operating maximum frequency is about the same as the signal frequency, an LPF 29 having a cutoff frequency of several MHz can be used, and the Comparator 30 can be an operational amplifier. The signal waveform is, for example, as shown in FIG. 5 (a), and the signal format is RZ (Return
to Zero).

FIGS. 5 and 6 show waveforms at respective points in the configuration diagrams of the embodiments of FIGS. In the figure, the thick line indicates that the jitter component is large. In FIG.
(a) is a jittered RZ format signal waveform, (b) is a waveform obtained by extracting the clock frequency from (a), (c) is a signal distributor output waveform, (d)
Shows a clock waveform in which jitter is suppressed, (e) shows a mixer output waveform, (f) shows a capacitor output waveform, (g) shows a peak detector output waveform, and (h) shows an integrator output waveform. (I) is a comparator output waveform. For example, when the signal is at the High level, it is estimated that the jitter component is large. (j) is a reference waveform of the comparator. In FIG. 6, (k) is a main signal waveform modulated by the comparator output signal, (l) is a multiplier output waveform,
(m) shows the jittered NRZ format signal waveform, and (n) shows the signal distributor output waveform.

Next, the operation will be described. The center frequency of the BPF 23 to which the signal shown in FIG. 5A is input is equal to the frequency of the signal. Therefore, the BPF 23 extracts a clock component having the same frequency as the signal, and the output waveform is as shown in FIG. However, the Q value of the BPF 23 is set so that the jitter component included in the output signal of the BPF 23 is larger than the jitter component included in the output signal of the PLL 25 described later.

Disti inputting the signal shown in FIG.
The rbutor 24 splits the input signal into two, and the output waveform is as shown in FIG.

A PLL 2 having the signal shown in FIG.
The output waveform of 5 is obtained by the operation to suppress the jitter component of PLL.
The waveform has a jitter component suppressed as shown in FIG.
(The thin line waveform in FIG. 5 represents a waveform having a small jitter component.) Here, a BPF may be used instead of the PLL 25. However, the Q value of the BPF must be sufficiently larger than that of the BPF 23.

The output signal of the mixer 26 which receives the signal shown in FIG. 5 (c) and the signal shown in FIG. 5 (d) is expressed as follows. Here, both inputs of the mixer 26 are clocks.

The output signal of the distirbutor 24 is changed to Asin (ω ₁ + Cs
_{inω J t) t (ω 1} : primary signal frequency, Csinω _J t: jitter frequency contained in the output signal of the BPF 23), when the _{Bsin (ω 1 + Dsinω S t} ) t The output signals of the PLL25, (Dsinω _S t : P
Jitter frequency included in output signal of LL25) Mixer26
Output signal is Asin (ω ₁ + Csinω _J t) t × Bsin (ω ₁ + Ds
_{inω S t) t = AB /} 2 cos (Csinωjt - Dsinω S t) t - AB / 2 c
os the _{(2ω i + Csinω j t +} Dsinω S t) t. Here, since it is Dsinω _S t ≒ 0 than operation with PLL, Output signal of Mixer26 the _{AB / 2 cos (Csinω j t} ) t - the _{AB / 2 cos (2ω 1 +} Csinω j t) t (1) .

However, actually, as shown in FIG.
The output signal of 26 is considered to include a DC component. Since this DC component becomes noise when the signal quality is determined by the comparator 30 described later, it is removed by the capacitor 27. Therefore, the output signal of the capacitor 27 is
An unnecessary DC component included in the output signal is removed, and the output waveform is as shown in FIG.

The output signal of the capacitor 27 is input to a peak detector 28 for peak detection. The peak detector output signal can be expressed by the following equation: AB / 2 from which high-frequency components in equation (1) have been removed.
cos (Csinω _j t) t. The output waveform of the peak detector 28 is shown in FIG. Here, square detection may be performed instead of peak detection.

In order to take the time average of the output signal of the peak detector 28, the signal is integrated by an LPF (Low Pass Filter) 29. Here, the integration may be performed by protecting the front and rear using a counter or the like. The output waveform of the LPF 29 is shown in FIG.

The output of the LPF 29 is input to a comparator 30 and is compared with an appropriate reference voltage to estimate a jitter component contained in the signal. FIG. 5 (j) shows a reference voltage waveform, and FIG. 5 (I) shows an output waveform of the comparator 30. Here, for example, it is assumed that the low level in FIG. 5 (I) has good signal quality and the high level has bad signal quality. By performing the phase comparison between the clocks by the mixer 26 as described above, the measurable jitter frequency band included in the input signal whose signal format is RZ can be expanded without adjustment.

Embodiment 2 FIG. 2 shows the configuration of the signal quality monitor of the present embodiment. The difference from FIG. 1 is the input waveform at the input point 2 of the mixer 26. This difference is that the BPF 23 in FIG. 1 extracts the clock from the received signal and distributes the clock, while FIG. 2 directly distributes the received data. In this embodiment, the mixer
The waveform at the input point 2 at 26 is data. Mixer2
6 performs the phase comparison between the clock and the data, as described above, and is included in the input signal whose signal format is RZ.
The measurable jitter frequency band can be expanded without adjustment.

Embodiment 3 FIG. FIG. 3 shows the configuration of the signal quality monitor of the present embodiment. The difference from FIG. 2 is the input signal format. In FIG. 3, the signal format is NR
Z and its waveform is shown in FIG. The distorbutor 24 which receives the signal shown in FIG.
The output waveform is as shown in FIG. 6 (n).

As shown in FIG. 7, since the main signal having the signal format of NRZ contains almost no ω1 component, it is necessary to double the frequency. Therefore, the multiplexer 34 sets the output frequency to twice the input frequency, and the output waveform is as shown in FIG. As described above, the mixer 26 performs the phase comparison between the clock and the data, so that the signal format becomes N.
The measurable jitter frequency band included in the input signal of RZ can be expanded without adjustment.

Embodiment 4 FIG. 4 shows the configuration of the signal quality monitor of the present embodiment. The difference from FIG. 1 is that the input signal is divided into three by the distributor 24 and one of its outputs is input to the level detector 36. , Level Detector
That is to adjust the output power of the variable gain amplifier 35 so that the input power to the BPF 23 becomes constant using the signal detected at 36. By performing the phase comparison between the clock and the data by the mixer 26 as described above, the measurable jitter frequency band included in the input signal whose signal format is RZ can be expanded without adjustment. Further, by monitoring the distribution signal power, the input signal power can be varied.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a signal quality monitor according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a signal quality monitor according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a signal quality monitor according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a signal quality monitor according to a fourth embodiment of the present invention.

FIG. 5 is a waveform chart at each point of the configuration diagram (1/2) showing the first to fourth embodiments of the present invention.

FIG. 6 is a waveform chart at each point of the configuration diagram (2/2) showing the first to fourth embodiments of the present invention.

FIG. 7 is a spectrum diagram when the signal format is NRZ and RZ.

FIG. 8 is a configuration diagram of Conventional Example 1.

FIG. 9 is a configuration diagram of a second conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Sampler 3 A / D converter 4 Memory 5 Operation part 6 Display part 7 PLL circuit 8 Phase comparator 9 Loop filter 10 VCO (voltage controlled oscillator) 11 N divider 12 Voltage adder 13 High frequency removal filter 14 Phase offset voltage generator 16 Multiplier circuit 17 Frequency conversion circuit 18 Mixer circuit 19 Filter 20 Phase frequency comparator 21 Jitter detection filter 23 BPF1 (Band Pass Filter) 24 Distibutor 25 PLL 26 Mixer 27 Capaciotr 28 Peak Detector 29 LPF (Low Pass) Filter) 30 Comparator 31 Modulator 34 Multiplexer 35 Variable Gain Amprifier 36 Level Detector 37 Output terminal

Claims (4)

[Claims] A clock extraction unit for extracting a clock component from an input signal; a clock distribution unit for distributing a clock output from the clock extraction unit; and a jitter included in the clock output from the clock distribution unit. A phase comparator that receives a clock output from the clock distribution unit and a clock output from the jitter suppression unit, and a signal quality that receives an output signal level of the phase comparator as an input. A signal quality monitor comprising: a determination unit. 2. A signal distribution means for distributing an input signal; a clock extraction means for extracting a clock component included in a signal output from the signal distribution means; and a signal output from the clock extraction means. Jitter suppressing means for suppressing jitter to be applied, a phase comparator which receives a signal output from the signal distributing means and a clock output from the jitter suppressing means, and a signal which receives an output signal level of the phase comparator as an input. A signal quality monitor comprising: a quality determination unit. 3. A signal distributing means for distributing an input signal, a frequency multiplier for multiplying the frequency of a signal output from the signal distributing means by K times (K is an arbitrary natural number), and an output from the signal distributing means. Clock extracting means for extracting a clock component included in the signal obtained from the signal, jitter suppressing means for suppressing jitter contained in the signal output from the clock extracting means, and a signal output from the frequency multiplier and the jitter suppressing means. A signal quality monitor comprising: a phase comparator receiving an output clock; and a signal quality determining unit receiving an output signal level of the phase comparator as an input. 4. A variable gain amplifier for amplifying an input signal by an amplifier having a variable gain, a clock extracting unit for extracting a clock component included in a signal output from the variable gain amplifier, and a clock extracting unit. Clock distribution means for distributing the output clock; jitter suppression means for suppressing jitter included in the clock output from the clock distribution means; clock output from the clock distribution means and output from the jitter suppression means. A phase comparator that receives the input clock, a level detector that detects a level of a signal output from the clock distribution unit, and a signal quality determination unit that receives an output signal level of the phase comparator as an input. The variable gain amplifier is controlled according to a signal output from the level detector. Quality monitoring device.