JP2000286695A - Divider circuit, serial-parallel conversion circuit using the divider circuit and serial data transmitting and receiving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a divider circuit which is suitable to divide a reference clock into the one-over-integer value that is not equal to the n-th power of 2 by feeding the output of a logical gate that provides AND between this output and a reset signal back to a data input terminal and outputting the clock obtained by dividing the reference clock into the specific value from an output terminal. SOLUTION: A 2-divider DVD1 divides a reference clock CK into two clocks by feeding the output of an inverter INV5 back to the data input terminal of a flip-flop F/F-5. In other words, the clock CK is once divided into 1/2 by the divider DVD1 and then into 1/n and outputted so that (n-1) pieces of flip- flops and the logical gates are alternately arranged and cascaded together and also the output of a multi-input logical gate using the outputs of those logical gates and a reset signal as inputs is fed back to the input terminal of the F/F-5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technology and a technology effective when applied to a frequency divider circuit of a clock signal, for example, for forming a timing signal in a serial / parallel conversion circuit used for a serial communication interface. The present invention relates to an effective technique used in a frequency dividing circuit.

[0002]

2. Description of the Related Art Conventionally, in a clock synchronous system, a frequency divider has been widely used to obtain a clock having a desired frequency from a reference clock. A conventional general frequency dividing circuit generally divides the frequency of a reference clock by a factor of 2 to the nth power. On the other hand, for example, in a serial-parallel conversion circuit used for a serial communication interface, for converting serial data into parallel data in units of 10 bits, a synchronizing signal for giving a data conversion timing is formed from a clock signal. / 10
A divider circuit that is not a power of 2 such as a divider may be required. The inventor has come up with a circuit as shown in FIG. 6 as a circuit for performing 1/10 frequency division.

[0003] The frequency dividing circuit shown in FIG.
Nine D-type flip-flops F / F-1 to F / F-9 which perform a latch operation in synchronization with each other are provided in cascade to divide the frequency, and the output side of each flip-flop is controlled by a reset signal. NAND gates G1 to G9 are provided and input to the flip-flops of the next stage.
There is provided a 10-input NAND gate G0 for calculating the logical product of the outputs of the D gates G1 to G9 and the reset signal, and outputs the output of the 10-input NAND gate G0 to the first stage flip-flop F
/ F-1 is fed back to the data input terminal, and the output signal of the first-stage flip-flop F / F-1 is divided by the frequency-divided clock BCK.
, The reference clock CK is frequency-divided by 1/10.

[0004]

The frequency dividing circuit shown in FIG. 6 has a reset signal RESET as shown in FIG.
, The frequency division operation starts, and the reference clock CK is set to 1
An output clock BCK divided to / 10 is obtained. Further, by using the output of the flip-flop, which takes in the received serial data signal in synchronization with the reference clock, as a reset signal, the frequency dividing circuit can be synchronized with the received data.

However, as shown in FIG. 6, a 10-input NAND gate G0 which takes the logical product of the outputs of the NAND gates G1 to G9 and the reset signal to form a signal to be fed back to the first stage flip-flop F / F1. And the 10-input NAND gate is a CMOS
In general, a circuit includes ten parallel p-channel MOSFETs connected between a power supply voltage and an output node, and ten series n-channel MOSFETs connected between an output node and the ground.

Therefore, ten n-channel MOSFEs
The resistance value when the output changes to the low level when T is all turned on increases, and the change in the output V0 of the NAND gate G0 becomes slow as indicated by reference numerals A and B in FIG. As a result, when the frequency of the reference clock is very high, it becomes clear that there is a problem that the frequency division cannot be performed accurately due to the bottleneck of the multi-input NAND gate.

An object of the present invention is to set a reference clock to 2 n
It is an object of the present invention to provide a frequency dividing circuit suitable for dividing a frequency by a non-power integer.

Another object of the present invention is to provide a frequency dividing circuit which can operate at high speed and consumes less current.

Another object of the present invention is to provide a serial-parallel conversion circuit and a serial data transmission / reception circuit suitable for serial communication conforming to the Fiber Channel standard.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, when a frequency dividing circuit for obtaining a frequency-divided clock obtained by dividing the reference clock by ｎn (n is an odd number) is constructed, first, the reference clock is once divided by 1 by the frequency-dividing circuit.
/ 2, (n-1) flip-flops and logic gates are alternately arranged and connected in cascade, and a multi-input logic having the output of the logic gate and a reset signal as inputs The output of the logic gate is further divided into 1 / n by a frequency divider configured to be fed back to the input terminal of the first-stage flip-flop, and is output.

According to the above-mentioned means, it is possible to obtain a frequency dividing circuit which can perform a high-speed operation for forming a clock signal obtained by dividing a reference clock of 1 GHz or more by 1/10 and has a small occupation area and a small current consumption. Note that the present invention is not limited to frequency division by 10, but can be applied to the case where the frequency of a clock is divided by a non-n power of 2 (especially, an integer of 3 or more and 2 times an odd number).

[0014] Further, a set of shift registers into which the input serial data is sequentially taken, a decision circuit for judging which of these shift registers takes the first bit, and a decision circuit based on an output signal of the decision circuit A selector circuit capable of selectively transmitting the data held in the shift register, and a data register for capturing the data selected by the selector circuit, and alternately capturing the input serial data into the pair of shift registers. In the serial / parallel conversion circuit configured to convert the clock extracted from the input serial data into a serial / parallel conversion circuit configured to convert the clock extracted from the input serial data by appropriately selecting the data by the selector circuit and supplying the data to the data register, and converting the data into parallel data. hand,
It is configured to form a signal for giving a data fetch timing to the data register. As a result, it is possible to obtain a serial-parallel conversion circuit that consumes less current and that can perform a serial-parallel conversion operation at high speed.

Further, the serial / parallel conversion circuit is used as a serial / parallel conversion circuit for converting received serial data into parallel data, and a parallel / serial conversion circuit for converting parallel data to be transmitted into serial data. A first clock forming circuit for forming a transmitting clock signal used in the circuit; and a second clock forming circuit for forming a receiving clock signal synchronized with the received serial data, the second clock forming circuit being formed by the second clock forming circuit. The serial-parallel conversion circuit is configured to operate based on a clock signal. This makes it possible to obtain a serial data transmitting / receiving circuit capable of performing serial communication with a high bit rate.

Further, the second clock forming circuit is configured to form a receiving clock synchronized with the received serial data based on the transmitting clock signal formed by the first clock forming circuit. Thereby, the frequency of the operation clock signal of the parallel-to-serial conversion circuit on the transmission side and the frequency of the operation clock signal of the serial-to-parallel conversion circuit on the reception side can be completely matched, and a highly reliable serial data transmission / reception circuit is obtained. be able to.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows that the frequency of the reference clock CK is 1
One embodiment of a divide-by-10 circuit that divides frequency by a factor of 0 is shown.

The divide-by-10 circuit in the circuit of this embodiment is
A frequency divider DVD1 for dividing the reference clock CK by 2;
And a five-divider DVD2 that divides the divided clock by five. Among them, the frequency divider DVD1 includes a D-type flip-flop F / F-5 in which a reference clock CK is input to a clock terminal, and an output Q (V) of the F / F-5.
5) and an inverter INV5 for inverting the flip-flop F / F-5.
Of the reference clock CK
Is divided by two.

On the other hand, in the 5 divider DVD2, the output Q (V5) of the flip-flop F / F-5 is input to each clock terminal, and the output Q (V5) of the flip-flop F / F-5 rises. , Four D-type flip-flops F / F-1 to F / F-4 which perform a latch operation of a data signal input to the data terminal in cascade are provided, and each flip-flop F / F- i (i = 1, 2,
3) Output terminal and next stage flip-flop F / F- (i + 1)
Of the preceding stage flip-flop F / F
A NAND gate Gi having an output signal of -i and a reset signal RESET as input signals and an inverter INVi having an output signal of the NAND gate Gi as an input signal are provided.

Further, among the flip-flops, F / F
-4, the output terminal of the flip-flop F / F-4 and the reset signal RESET are used as input signals.
A D gate G4 is connected, and the output signals of the NAND gate G4 and the NAND gates G1, G2, G3 are input to a 4-input NAND gate G5, and the output signal V0 is applied to the data terminal of the first-stage flip-flop F / F-1. The feedback input is The output signal of the first-stage flip-flop F / F-1 is supplied to the NAND gate G1 via the inverter INV0.
Has been entered.

Next, the operation of the divide-by-10 circuit of this embodiment will be described with reference to the timing chart of FIG.

In the circuit of this embodiment, when the reset signal RESET changes to low level (timing t1),
The outputs of the NAND gates G1 to G4 of the subsequent five-frequency divider DVD2 are set to the high level, and the output V0 of the four-input NAND gate G5 which receives those output signals changes to the low level and is reset to the five-frequency divider DVD2. It takes. The former-stage frequency divider DVD1 operates regardless of the reset signal.

Next, in response to the reset signal RESET changing to the high level, the NAND gates G1 to G4 are activated, and the reset of the five-frequency divider DVD2 is released, whereby the flip-flops F / F-1 to F / F-1 are released. The F / F-4 starts the frequency dividing operation. Then, after the reset signal RESET changes to the high level, first, at the timing t2 when the output signal V5 of the frequency divider 2 changes to the high level, the flip-flop F
/ F-1 takes in the output V0 (low level) of the NAND gate G5, and the output V1 of the NAND gate G1 changes to low level.

Subsequently, at a timing t3 when the output signal V5 of the frequency divider DVD1 changes to the high level, the flip-flop F / F-1 switches the output V0 of the NAND gate G5.
(High level), the output V1 of the NAND gate G1 changes to high level. Then, in response to the change of V1 to the high level, the output V2 of the next stage NAND gate G2 changes to the low level. Thereafter, by repeating the above operation, a negative pulse is transmitted to the NAND gates G3 and G4, and the output of the final-stage NAND gate G5 again changes to low level. As a result, the reference clock CK is reduced to 1/1.
The clock BCK divided to 0 is used as the flip-flop F / F
Obtained from -1. The clock BCK can be taken out from the other flip-flops F / F-2 to F / F-4. However, since the output of the first-stage flip-flop F / F-1 is the earliest, this is used as the output clock BCK. Is desirable.

FIG. 3 shows a serial / parallel conversion circuit for converting serial data into parallel data. The clock SCK synchronized with the serial data is frequency-divided, and the serial data taken into the shift register is converted into parallel data and output. FIG. 4 shows an embodiment in which the divide-by-10 circuit of the above-described embodiment is used in a circuit for forming a clock for giving the timing to perform the operation and a byte aligning clock RBC, and FIG.

The serial / parallel conversion circuit shown in FIG. 3 converts 10-bit input serial data into parallel data and outputs the parallel data. In this embodiment, even and odd bits are fetched, that is, each bit of the serial data is converted. To take in alternately, a pair of shift registers SFRA,
A two-frequency divider DVD1 that provides an SFRB, first divides the frequency of the synchronous clock SCK by half to form shift clocks ODCK and EVCK whose phases are shifted from each other by 180 °, and the divided clock. A circuit provided with a divide-by-five divider DVD2 for further dividing EVCK by ５ and a divide-by-2 divider DVD3 for further dividing the divided-by-5 clock to form a byte-aligned clock RBC It is configured. Divider 2 DVD1 and Divider 5 D
VD2 is the divide-by-10 circuit shown in FIG.

As described above, the shift register SFR for separately capturing even and odd bits of serial data
A, SFRB provides data transfer speed of 1
Even if the frequency is as high as 062.5 MHz, each shift register only needs to take in data at half the speed, which facilitates the design of the internal circuit.

The serial-to-parallel conversion of 10-bit data is performed in the asynchronous data transfer by, for example, a start bit and a stop bit in 1-byte (8-bit) data which is a data processing unit by a microcomputer or the like. And converted to a 10-bit code (8
This is to support a protocol for performing (b / 10b conversion) and transmitting. The synchronous clock SCK supplied to the serial-parallel conversion circuit of this embodiment is, for example, a clock extracted from received serial data in a PLL circuit (not shown).

In this embodiment, a pair of shift registers SFRA and SFR which take in even-numbered bits and odd-numbered bits respectively, that is, take in each bit of serial data alternately.
B, the input data to the shift register SFRA is determined in order to determine in which shift register the first bit is taken and to determine whether the input data is a header consisting of a predetermined code. COMM that compares data held in shift register SFRB with data
An A detection circuit COM-X and a COMMA detection circuit COM-Y for comparing data held in the shift register SFRA with data input to the shift register SFRB are provided. A signal obtained by logically ORing the detection signals of these circuits by the OR gate G10 is supplied as a data input signal TD to a flip-flop F / F-6 constituting a circuit CKG forming a byte alignment clock RBC. The output of the flip-flop F / F-6 is supplied to the five-frequency divider DVD2 as a reset signal RESET.

Further, these COMMA detection circuits COM
/ Reset flip-flop R set or reset by output signals of -X and COM-Y
S / F / F and the data held in the shift registers SFRA and SFRB are appropriately selected based on the output state of the flip-flop, that is, the detection results of the COMMA detection circuits COM-X and COM-Y, and input serial data SD.
A selector circuit SEL is provided to supply each bit of T to the data register REG at the last stage as a signal in which the bits are arranged in a correct order.

The shift register SFRA, S of this embodiment
The FRB takes in 10-bit serial data for both, so in principle, it should have five stages each, but each has eight stages. This takes into account the time required for the COMMA detection circuits COM-X and COM-Y to determine which shift register has taken the first bit of the received data, and thereby takes in the shift registers SFRA and SFRB. While outputting 10-bit data and performing serial-parallel conversion, the next 10-bit data can be fetched.

The signal RSD input to the set / reset flip-flop RS-F / F is a control signal indicating whether or not to enable the function of the selector circuit SEL, and is usually fixed at a high level. You. Further, the circuit of this embodiment is provided with a power-on reset control circuit PWC for resetting the frequency dividing circuit when the power is turned on. This power-on reset control circuit PWC receives a reset signal PWRS supplied from an upper layer when power is turned on.

In FIG. 3, the portion surrounded by the symbol CKG forms the frequency-divided output of the frequency divider DVD1, the data input signal DT and the data detection signal COMDET, and also includes the data detection signal COMDET. This is a signal forming circuit that forms a byte-aligned clock signal RBC with a duty of 50% specified by the Fiber Channel standard FC-PH Rev4.3 FC-0 based on the divided output.

That is, the signal forming circuit CK of this embodiment
G is a data latch flip-flop F / F-6 which takes in the 5 frequency divider DVD2 and the data input signal DT in synchronization with the output clock EVCK of the 2 frequency divider DVD1.
And the flip-flop F / F-7 which takes in the output signal of the flip-flop F / F-6 in synchronization with the output clock EVCK of the frequency divider DVD1 and the output of the frequency divider DVD2 which is divided by two. F / F-8 taken in synchronism with the output clock ODCK, and the output of the flip-flop F / F-7 using the output signal of the flip-flop F / F-8 as a clock to generate the data detection signal COMDET. Output flip-flop F
/ F-9.

At the same time, the signal forming circuit CKG shown in FIG.
Divides the output clock BCK of the divide-by-five divider DVD2 by 2 to form a byte-aligned clock signal RBC with a duty of 50%, and outputs the divide-by-two divider DVD3. The clock EVCK is used for the byte alignment clocks RBC and RBCN of the normal phase and the negative phase.
Flip-flop F / F which latches and outputs in synchronization with
-10 and F / F-11.

Further, in FIG. 3, the output signal of the flip-flop F / F-8 which latches the output BCK of the ５ frequency divider DVD2 in synchronization with the clock ODCK is latched with respect to the data register REG. Alternatively, it is also supplied as a signal indicating output timing.

In the serial-to-parallel conversion circuit of this embodiment, the received serial data SDT is input in frame units with 4 bytes (1 byte being 10 bits) as one frame. When a detection signal is output from X or COM-Y, that is, when the first header byte enters for each frame, a data detection signal COMDET is formed and output. Then, as shown in FIG. 4, the data A0 to A9 of the first one-byte serial-parallel converted data are output from the data register REG almost simultaneously with the timing when the data detection signal COMDET changes.

The symbols A and B shown in FIG.
It is different from reference numerals A and B shown in FIG. That is, codes A and B shown in FIG. 3 are codes added to distinguish output signals of shift registers SFRA and SFRB, whereas codes A and B shown in FIG. C is a code assigned to distinguish the bit of each byte in one frame of the received serial data SDT. In FIG. 4, reference symbol Trxlat denotes the latency of received data, that is, the time from reception of one byte of data to output, and Tbeforf denotes a byte alignment clock R.
The setup time of the data detection signal COMDET for the BC, Tafter is the hold time of the data detection signal COMDET for the byte alignment clock RBC, T
srbc is the synchronous clock SC caused by the jitter of the PLL circuit.
K is the clock skew.

FIG. 5 shows a configuration example of a transmission / reception LSI for serial communication using the serial / parallel conversion circuit of the embodiment of FIG. In FIG. 5, a portion surrounded by a broken line 100 is a transmission / reception LSI, and this LSI 100 is an upper layer logical LSI 200 having a signal encoding / decoding function and the like.
And the transmission serial data output terminal O
The UT has a driver IC (not shown) for driving a transmission line such as an optical fiber, a coaxial cable, or a twisted pair line, and the reception serial data input terminal IN receives a signal transmitted via the transmission line. Receiver ICs (not shown) for amplification are respectively connected.

The above-mentioned transmission / reception LSI 100 for serial communication
Is a PLL that multiplies, for example, a 106.25 MHz system clock TBC supplied in common with the upper-layer logical LSI 200 to generate a transmission clock TXC having a 10-fold frequency (1.0625 GHz) required for transmission inside the LSI. (Phase Locked Loop) transmission clock generation circuit 110 using a circuit, and transmission parallel data TX supplied from upper layer logical LSI 200
A serial-to-serial conversion circuit 120 for converting D into serial data in synchronization with the transmission clock TXC, and a transmission buffer 130 for outputting the converted serial data to the outside of the LSI
And the serial data received from the input terminal IN
Receive buffer 14 for converting to an internal suitable level
0 and the same frequency as the received data (1.0625) in synchronization with the received serial data based on the transmission clock TXC generated by the transmission clock generation circuit 110.
(GHz) receiving clock RXC, and a serial-parallel conversion circuit 160 for converting the receiving serial data RSD received by the receiving buffer 140 into receiving parallel data RXD using the receiving clock RXC. , The upper layer logical LSI 20
The control circuit 170 includes a control circuit 170 that controls the reception clock generation circuit 150 in response to the reset signal LCKREF supplied from 0.

In FIG. 5, reference numeral 160 denotes a serial-parallel conversion circuit having a configuration as shown in FIG. Further, the transmission / reception LSI 10 of this embodiment
0 is not particularly limited, but the logical LSI 2 of the upper layer
The transmission serial data after the transmission parallel data TXD output from 00 has been subjected to serial / parallel conversion is converted to the upper layer logic L.
In order to return to the SI 200 and check transmission serial data (loopback mode), the output signal (transmission serial data) of the parallel / serial conversion circuit 120 and the reception signal (reception serial data) from the transmission buffer 130 are transmitted. A selection circuit 180 is provided for selecting and supplying the data to the serial-parallel conversion circuit 160. The selection circuit 180 is configured to be controlled by a loop back mode selection signal EWRAP supplied from the upper layer logic LSI 200.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the above-described embodiment, the D / 2 flip-flop F1 and the feedback inverter INV5 have been described as the frequency divider DVD1, but the output is inverted every time a pulse is input. The frequency divider may be configured using a type-type, ie, trigger-type flip-flop.

In the above description, the invention made by the inventor has been mainly described with respect to the serial / parallel conversion circuit in the transmission / reception LSI for serial communication, which is the application field in which the invention is based, but the invention is not limited thereto. , Can be widely used when forming a clock obtained by dividing a reference clock to an integer fraction other than 2 to the power of n.

[0045]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to form a clock signal obtained by dividing the reference clock of 1 GHz or more into 1/10 and to realize a high-speed frequency dividing circuit which occupies a small area and consumes less current. By using the circuit, it is possible to realize a serial-parallel conversion circuit and a serial data transmission / reception circuit capable of performing serial communication conforming to the Fiber Channel standard.

[Brief description of the drawings]

FIG. 1 shows that the frequency of a reference clock CK according to the present invention is 10
FIG. 4 is a circuit diagram showing an example of a frequency dividing circuit that divides frequency by 1;

FIG. 2 is a timing chart showing operation timings of the circuit of FIG.

FIG. 3 is a circuit diagram showing an embodiment of a serial-parallel conversion circuit for converting serial data into parallel data, and a circuit in which the frequency dividing circuit according to the present invention is applied to a circuit for forming a timing signal used in the serial-parallel conversion circuit; Diagram.

FIG. 4 is a timing chart showing operation timings of the serial-parallel conversion circuit of FIG. 3;

5 is a block diagram showing a configuration example of a transmission / reception LSI for serial communication using the serial / parallel conversion circuit of FIG. 3;

FIG. 6 is a circuit configuration diagram showing a configuration example of a divide-by-10 circuit studied prior to the present invention.

FIG. 7 is a timing chart showing the operation timing of the circuit of FIG. 6;

[Explanation of symbols]

 SFRA, SFRB shift register COM-X, COM-Y COMMA detection circuit SEL selector REG data register CKG signal formation circuit DVD1 2 frequency divider DVD2 5 frequency divider DVD3 2 frequency divider 100 Serial communication transmission / reception LSI 200 Upper layer logic LSI 110 transmission clock generation circuit 120 parallel-to-serial conversion circuit 130 transmission buffer 140 reception buffer 150 reception clock generation circuit 160 serial-parallel conversion circuit 170 control circuit 180 selection circuit

Claims (7)

[Claims] 1. A first frequency dividing circuit for dividing a reference clock by １ ／, and (n−1) latching operations performed in synchronization with the clock divided by the first frequency dividing circuit Are provided in cascade, the output of each flip-flop is input to the next flip-flop via a logic gate controlled by a reset signal, and the logical product of the output of these logic gates and the reset signal Is output to the data input terminal of the first-stage flip-flop, and a divided clock obtained by dividing the reference clock to 1 / 2n (n is an odd number of 3 or more) is output from the output terminal of one of the flip-flops. A second frequency dividing circuit configured to output the signal. 2. The frequency dividing circuit according to claim 1, wherein said n is 5. 3. The output of the frequency-divided clock outputted from the output terminal of the first-stage flip-flop of the cascade-connected flip-flop. Divider circuit. 4. The frequency dividing circuit according to claim 1, 2 or 3, a set of shift registers in which input serial data is sequentially taken, and the first bit is taken into any of these shift registers. A determination circuit for determining whether or not the selector circuit can selectively transmit data held in the shift register based on an output signal of the determination circuit;
A data register for taking in the data selected by the selector circuit, and sequentially taking the input serial data into the set of shift registers, selecting the appropriate serial data as appropriate, and supplying the data to the data register. And the frequency divider is configured to divide a clock extracted from the input serial data to form a signal for giving a timing of taking data into the data register. A serial-to-parallel conversion circuit characterized in that: 5. A signal forming circuit for forming a detection signal indicating that serial data has been received based on an output signal of the frequency dividing circuit and an output signal of the determining circuit. The described serial-parallel conversion circuit. 6. A serial-parallel conversion circuit according to claim 4, wherein said serial data is converted into parallel data, a parallel-serial conversion circuit which converts parallel data to be transmitted into serial data, and said parallel-serial conversion circuit. A first clock generation circuit for generating a transmission clock signal used for
A second clock generation circuit for generating a reception clock signal synchronized with the reception serial data, wherein the serial / parallel conversion circuit is operated based on the clock signal generated by the second clock generation circuit; A serial data transmitting / receiving circuit, comprising: 7. The first clock generation circuit according to claim 1, wherein
7. The serial data transmission / reception circuit according to claim 6, wherein a reception clock synchronized with the reception serial data is generated based on a transmission clock signal generated by the clock generation circuit.