JP2000286499A - Iii nitride compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the concentration of current and to drop the operation voltage of an element by forming a substrate and a base layer formed of conductive metallic nitride on the substrate, forming III nitride compound semiconductor layers on the base layer and installing an electrode on the base layer. SOLUTION: In a III nitride compound semiconductor device, a base layer 14 formed of metallic nitride, TiN, for example, is formed on a substrate 11. III nitride compound semiconductor layers 16, 17 and 18 are formed on the base layer 14. An n-electrode 21 is installed on the base layer 14. Since the thickness of the n-layer becomes uniform, electricity is prevented from being concentrated. Since metallic nitride touching the n-electrode 21 is superior to a semiconductor in electric conduction, low operation voltage can be realized. Then, light in the direction of the substrate 11, which is generated in a light emitting layer, can efficiently be reflected and the luminance of a light emitting diode can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a group III nitride compound semiconductor device.

[0002]

2. Description of the Related Art In a group III nitride compound semiconductor device 1 in which a group III nitride compound semiconductor layer is grown on a sapphire substrate, as shown in FIG.
And a part of the n-layer 4 are removed by etching. Then, an n-electrode 9 is connected to the exposed portion of the n-layer 4.
In FIG. 1, reference numerals 2, 3, 7, and 8 denote a substrate, a buffer layer, a light-transmitting electrode, and a p-electrode, respectively.

[0003]

SUMMARY OF THE INVENTION The inventors of the present invention have studied the light emitting device having such a configuration and found the following problems to be solved. That is, n of the portion in contact with the light emitting layer 3
The layer 4A and the portion 4B of the n-layer forming the n-electrode 6 have different thicknesses. Therefore, current concentration occurs at the boundary between the thick portion 4A and the thin portion 4B, and as a result, the operating voltage of the element increases. In addition, there is also a problem that the concentration of the current deteriorates the electrostatic withstand voltage characteristics. Further, such a configuration may be replaced by a conventional electronic device, such as a rectifier, a thyristor,
When applied to transistors, FETs, and the like, there is a problem that the operating voltage increases and the allowable current cannot be increased.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has the following configuration. A substrate, a base layer made of conductive metal nitride formed on the substrate, and a group III nitride compound semiconductor layer formed on the base layer; A group III nitride-based compound semiconductor device, comprising: an electrode;

[0005] According to the group III nitride compound semiconductor device constructed as described above, the underlying layer is made conductive, and
A group III nitride-based compound semiconductor layer is formed, and an electrode is provided on the underlying layer. Therefore, it is not necessary to provide a thick portion and a thin portion in the n-layer as in the conventional example. Therefore, current concentration at the boundary between the thick part and the thin part is eliminated, and the operating voltage of the element can be reduced.

In the above, the material of the substrate is not particularly limited as long as it is suitable for the group III nitride compound semiconductor. Sapphire, silicon, silicon carbide, zinc oxide,
Gallium phosphide, gallium arsenide, magnesium oxide, manganese oxide, and the like can be given as examples of the material of the substrate. In particular, the present invention is useful for insulating substrates such as sapphire and zinc oxide.

As the conductive metal nitride, titanium nitride,
Hafnium nitride, zirconium nitride or tantalum nitride is selected. The method for growing these metal nitrides on the substrate is not particularly limited, but includes MOCVD, plasma C
CVD (Chemica) such as VD, thermal CVD, optical CVD, etc.
1 Vapor Deposition), sputtering, reactive sputtering, laser ablation, ion plating, vapor deposition, ECR method, etc. (Physi
cal Vapor Deposition). The thickness of the underlayer is preferably 0.3 to 10 μm. The reason why the thickness of the underlayer is 0.3 μm or more is that when the group III nitride-based compound semiconductor layer is etched to expose the underlayer, an electrode is formed on the underlayer even if the etching affects the underlayer. This is for securing a film thickness that can be formed. The reason why the thickness of the underlayer is set to 10 μm or less is solely for economic reasons.

Another layer can be interposed between the underlayer and the substrate. According to the study of the present inventors, when titanium nitride is grown on the (111) plane using silicon as a substrate, the film formation is performed at a high temperature of 500 ° C. or more. In addition, between the (111) plane and the titanium nitride layer, A
When a layer of 1 is interposed, a titanium nitride single crystal can be formed even at a temperature as low as about 300 ° C. The thickness of the Al layer is not particularly limited, but is set to approximately 100 °. The method for forming the Al layer is not particularly limited, but is formed by, for example, vapor deposition or sputtering. After forming the base layer on the substrate, it is preferable to heat-treat the base layer. The heat treatment is performed in a hydrogen atmosphere or a vacuum atmosphere (more preferably, a hydrogen atmosphere) at 600 to 1200 ° C. (more preferably 800 to 12 ° C.).
00 ° C).

The group III nitride-based compound semiconductor is a general formula of Al _X Ga _Y In _1-XY N (0 ≦ X ≦ 1, 0
≦ Y ≦ 1, 0 ≦ X + Y ≦ 1),
Furthermore, boron (B) and thallium (Tl) as Group III elements
And part of nitrogen (N) may be replaced with phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). The group III nitride compound semiconductor may contain any dopant. II
The method of forming the group I nitride-based compound semiconductor layer is not particularly limited, but is formed by, for example, a well-known organic metal compound vapor deposition method (hereinafter, referred to as “MOCVD method”). Also, it can be formed by a well-known molecular beam crystal growth method (MBE method).

[0010] Between a metal nitride as an underlayer and a group III nitride-based compound semiconductor layer (generally a GaN layer in many cases) constituting an element structure, the lattice constant is substantially intermediate between the two. It is preferable that another group III nitride compound semiconductor layer having a lattice constant is interposed as a buffer layer. This is to reduce the influence of the lattice of the underlayer on the lattice of the group III nitride compound semiconductor layer constituting the element structure. When titanium nitride is selected as the base layer and the GaN clad layer of the light emitting element is formed thereon, it is preferable to form an AlN layer (about 150 °) as a buffer layer on the titanium nitride layer. The formation method is such that the underlayer is heat-treated in a hydrogen atmosphere (1000 ° C., 5 minutes),
At 0 ° C., a group III nitride compound semiconductor layer is grown by MOCVD. Alternatively, a group III nitride compound semiconductor layer is grown on the titanium nitride underlayer by a sputtering method without performing heat treatment. Al used as a buffer layer
N is preferably doped with Si or the like to form an n-type semiconductor.

After laminating the group III nitride compound semiconductor layer, a predetermined portion thereof is removed by etching to expose the underlying layer. Alternatively, it is also possible to mask a predetermined portion of the underlayer in advance so that the group III nitride-based compound semiconductor layer does not grow in the portion, and remove the mask to expose the underlayer. Silicon oxide and silicon nitride are available as mask materials. The position and shape of the exposed portion in the underlayer are not particularly limited, but the peripheral portion of the underlayer is preferable from the viewpoint of forming an electrode there. When the element, that is, the underlying layer is viewed as a plane, and this is a rectangular quadrangle, it is preferable to expose the corners of the underlying layer. The material of the electrode connected to the underlayer is
There is no particular limitation as long as ohmic contact can be obtained between the underlayer and the electrode. Considering wire bonding, an alloy of Al and Au, an alloy of Ti and Au, or the like can be used as a material for the electrode.

Next, an embodiment of the present invention will be described with reference to the drawings. As an example of the element, the light emitting diode 10 of FIG. 2 is employed. The specifications of each layer are as follows. Layer: Composition: Dopant (thickness) P-cladding layer 18: p-GaN: Mg (0.3 μm) Emitting layer 17: Superlattice structure Quantum well layer: In _0.15 Ga _0.85 N (35 °) Barrier layer: GaN (35 °) Number of repetitions of quantum well layer and barrier layer: 1 to 10 n cladding layer 16: n-GaN: Si (4 μm) buffer layer 15: n-AlN: Si (150 °) TiN layer 14 (underlying layer): TiN Single crystal (3000mm) substrate 11: Sapphire (300μm)

In the above, the buffer layer 15 is doped with an n-type dopant such as silicon to secure conductivity. The n-cladding layer 16 can have a two-layer structure including a low electron concentration n− layer on the light emitting layer 17 side and a high electron concentration n + layer on the buffer layer 15 side. The light emitting layer 17 is not limited to the superlattice structure, but may be a single hetero type, a double hetero type, a homo junction type, or the like. A wide band gap A doped with an acceptor such as magnesium between the light emitting layer 17 and the p cladding layer 18
l _X Ga _Y In _1-XY N (0 ≦ X ≦ 1, 0 ≦ Y ≦
1, 0 ≦ X + Y ≦ 1) layer can be interposed. This is because the electrons injected into the light emitting layer 17 are
This is to prevent diffusion into the p cladding layer 18
Can have a two-layer structure including a low hole concentration p− layer on the light emitting layer 17 side and a high hole concentration p + layer on the electrode side.

The TiN layer is formed by a general reactive sputtering method. Thereafter, the TiN / sapphire sample is transferred from the sputtering apparatus into the chamber of the MOCVD apparatus. While flowing hydrogen gas into the chamber, the sample is heated to 1000 ° C. and maintained for 5 minutes.

Thereafter, a buffer layer 15 made of AlN is grown at a growth temperature of 1000 ° C., and the temperature is kept at 1000 ° C. to form the n-cladding layer 16 and thereafter according to a conventional method (MOCVD method). In this growth method, ammonia gas and
Group III element alkyl compound gas such as trimethylgallium (TMG), trimethylaluminum (TMA)
Or trimethylindium (TMI) is supplied to a substrate heated to an appropriate temperature to cause a thermal decomposition reaction, thereby growing a desired crystal on the substrate. Each group III nitride-based compound semiconductor layer can be formed by MBE.

After forming each group III nitride compound semiconductor layer, the underlying layer 14 made of titanium nitride is etched.
Is expressed. Thereafter, a translucent electrode 19 is formed on substantially the entire surface of the p-cladding layer 18 by vapor deposition. The translucent electrode 19 is a thin film containing gold. The p-electrode 20 is also made of a material containing gold, and is formed on the translucent electrode 19 by vapor deposition. Then, an n-electrode 21 made of an alloy of Al and Au is formed on the exposed portion of the underlayer 14 by vapor deposition.

The light emitting diode 1 thus obtained
0 is shown in FIG. As shown in FIG. 3, when the element is viewed as a plane, when the element is a right quadrangle (preferably a square), the n-electrode 21 and the p-electrode 20 are preferably on a diagonal line. More preferably, each electrode is arranged so as to be sandwiched between two sides forming diagonally opposite corners.

According to the light emitting diode having such a configuration, the concentration of the current, which is a problem in the conventional example, does not occur because the thickness of the n layer is uniform. In addition, metal nitride in contact with an electrode is superior to a semiconductor in electric conduction. Therefore, a low operating voltage can be achieved. In addition, since metal nitrides such as titanium nitride generally have a metallic color, they also have an effect of efficiently reflecting light generated in the light emitting layer toward the substrate and improving the brightness of the light emitting diode. Further, since metal nitrides such as titanium nitride generally have high thermal conductivity, it is possible to efficiently radiate heat from the exposed portions of the underlayer.

The group III nitride compound semiconductor layer formed on the underlayer may be a p-layer, while the uppermost group III nitride compound semiconductor layer may be an n-layer. in this case,
The translucent electrode (see 19 in FIG. 2) can be omitted.

The devices to which the present invention is applied are not limited to the above-mentioned light emitting diodes, but include optical devices such as light receiving diodes, laser diodes and solar cells, as well as bipolar devices such as rectifiers, thyristors and transistors, and FETs.
And the like, and electronic devices such as microwave devices. The present invention is also applicable to a laminate as an intermediate of these elements.

The present invention is not limited to the description of the above-described embodiments and examples, but includes various modifications that can be made by those skilled in the art without departing from the scope of the claims.

The following matters are disclosed. (11) a substrate, an underlayer made of conductive metal nitride formed on the substrate, and an underlayer formed on the underlayer.
A group III nitride-based compound semiconductor layer, and the underlayer is coated with the group III nitride-based compound semiconductor layer on the same surface as the surface on which the group III nitride-based compound semiconductor layer is formed. A laminate, having no zones. (12) The laminate according to (11), wherein the metal nitride is made of one or more of titanium nitride, zirconium nitride, hafnium nitride, and tantalum nitride. (13) The base layer is a quadrangle in plan view, and a portion sandwiched between two sides constituting one corner is an area not covered with the group III nitride-based compound semiconductor layer.
The laminate according to (11) or (12), wherein (14) The laminate according to any one of (11) to (13), wherein an area not covered with the group III nitride-based compound semiconductor layer is exposed. (21) An underlayer made of a conductive metal nitride is formed on a substrate, a group III nitride compound semiconductor layer is formed on the underlayer, and the group III nitride compound semiconductor layer is partially A method for manufacturing a group III nitride-based compound semiconductor device, comprising: removing the underlayer to expose the underlayer; and connecting an electrode to the underlayer in the exposed portion. (22) The method according to (21), wherein the metal nitride is made of one or more of titanium nitride, zirconium nitride, hafnium nitride, and tantalum nitride. (23) The base layer has a rectangular shape in a plan view, and the group III nitride compound semiconductor layer is formed on the entire surface thereof,
(21) or (22), wherein the group III nitride-based compound semiconductor layer is etched so that one corner of the right quadrangular shape is exposed to expose the underlying layer at that portion. The production method described in 1. (31) An underlayer made of a conductive metal nitride is formed on a substrate, a group III nitride compound semiconductor layer is formed on the underlayer, and the group III nitride compound semiconductor layer is partially A method for manufacturing a laminate, comprising removing the underlayer to expose the underlayer. (32) The method according to (31), wherein the metal nitride is made of one or more of titanium nitride, zirconium nitride, hafnium nitride, and tantalum nitride. (33) The base layer has a rectangular shape in a plan view, and the group III nitride-based compound semiconductor layer is formed on the entire surface thereof,
(31) or (32), wherein the group III nitride-based compound semiconductor layer is etched so that one corner of the right quadrangular shape is exposed, and the underlying layer is exposed at that portion. The production method described in 1.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a conventional light emitting diode.

FIG. 2 is a sectional view showing a light emitting diode according to an embodiment of the present invention.

FIG. 3 is a plan view of the light emitting diode of the embodiment.

[Explanation of symbols]

1, 10 light emitting diode 2, 11 substrate 3, 15 buffer layer 4, 5, 6, 16, 17, 18 group III nitride compound semiconductor layer 7, 19 translucent electrode 8, 20 p electrode 9, 21 n electrode

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Daishi Watanabe 1 Ochiai Nagahata, Kasuga-machi, Nishi-Kasugai-gun, Aichi Prefecture Inside Toyoda Gosei Co., Ltd. No. 1 Toyoda Gosei Co., Ltd. (72) Inventor Jun Ito Nagahata 1 Ochiai, Kasuga-machi, Nishikasugai-gun, Aichi Prefecture No. 1 Toyoda Gosei Co., Ltd. Synthetic Co., Ltd. F-term (reference) 4M104 AA04 BB09 BB30 CC01 DD33 DD34 DD37 DD43 GG02 GG04 GG06 GG07 GG08 GG11 GG12 GG19 HH15 5F041 CA05 CA34 CA40 CA46 CA82 CA91 CA98 5F073 AA61 AA74 CA02 CA07 CB05 CB07 DA07

Claims (4)

[Claims] 1. A semiconductor device comprising: a substrate; an underlayer made of a conductive metal nitride formed on the substrate; and a group III nitride compound semiconductor layer formed on the underlayer. Wherein an electrode is provided on the underlayer.
Group III nitride compound semiconductor device. 2. The device according to claim 1, wherein the metal nitride is made of one or more of titanium nitride, zirconium nitride, hafnium nitride, and tantalum nitride. 3. The base layer has a rectangular shape in a plan view.
The device according to claim 1, wherein the electrode is provided so as to be sandwiched between two sides forming one corner. 4. A sapphire substrate, an underlayer made of metal nitride formed on the substrate, a first electrode connected to the underlayer, and an underlayer in an area other than the area where the electrode is provided. III-nitride compound comprising a plurality of III-nitride compound semiconductor layers formed thereon and a second electrode connected to the uppermost layer of the III-nitride compound semiconductor layer Semiconductor element.