JP2000284873A - Memory circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory circuit board which operates fast and stably and does not cause increase in power consumption. SOLUTION: This memory circuit board on which plural memory elements 11 to 14 are mounted connects a termination circuit 20 consisting of serial circuits of resistances 21 and capacitors 22 at the ends of connection lines 16 which start at prescribed terminals of a connector 10 and connect prescribed terminals of the elements 11 to 14 in turn. It is possible to suppress waveform disturbance, e.g. of overshoot and undershoot within an allowable value without increasing delay and also to prevent power consumption from being increased by adopting a termination circuit for wiring in the board as well in the same manner with a transmission line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit board, and more particularly to a memory circuit board capable of operating at high speed.

[0002]

2. Description of the Related Art Conventionally, in a personal computer or the like, a CPU is mounted on a main board, and a memory bus exits from the CPU via a memory bus control LSI, and is connected in parallel to a plurality of memory circuit board connectors. Was connected. The memory is mounted by attaching a desired number and capacity of memory circuit boards to the memory circuit board connector. The operating speed of the memory bus is 50
MHz or 66 MHz, and it has not been so difficult to create a memory circuit board that operates at such a speed using existing circuit technology.

FIG. 2 is an explanatory diagram for explaining a wiring structure in a conventional memory circuit board. A connection line 16 starting from the connector 10 is connected via a resistor 15 to a plurality of memory elements 11.
To 14 were sequentially connected. The resistor 15 is a resistor inserted to suppress the disturbance of the waveform, for example, overshoot or undershoot, within an allowable value. For example, about 10Ω is used.

[0004]

In recent years, the speed of the CPU has been remarkably increased, and accordingly, the speed of the memory bus has been increased to 100 MHz.
Alternatively, the speed is being increased to 133 MHz. In addition, there is a demand for increasing the capacity and miniaturization of the memory circuit board, and it is necessary to increase the number of elements and reduce the wiring width. However, in the case where the circuit configuration of the conventional memory circuit board as described above is adopted, the disturbance of the waveform falls within an allowable value unless the value of the resistor 15 is increased due to an increase in the capacitance and inductance in the board. On the other hand, if the resistance value is increased, the delay amount of the signal waveform of RAS (low address select) or CAS (column address select) exceeds the allowable value, and high-speed operation cannot be performed. SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory circuit board which solves the above-mentioned problems of the prior art, operates stably at high speed, and does not increase power consumption.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a memory circuit board on which a plurality of memory elements are mounted, starting from predetermined terminals of a connector means and connecting predetermined terminals of the plurality of memory elements in order. It is characterized in that a terminating circuit is connected to the end of the line, and that a series circuit of a resistor and a capacitor is adopted as the terminating circuit. Advantageous Effects of Invention According to the present invention, by adopting a termination circuit in the same manner as a transmission line for wiring in a substrate, it is possible to suppress waveform disturbance such as overshoot or undershoot to within an allowable value without increasing delay. And power consumption does not increase.

[0006]

Embodiments of the present invention will be described below in detail. FIG. 1 is an explanatory diagram showing a wiring structure of a memory circuit board to which the present invention is applied. A connection line 16 starting from the connector 10 is sequentially connected to a plurality of memory elements 11 to 14 via a resistor 15. The resistor 15 is a resistor inserted to suppress the disturbance of the waveform, for example, overshoot or undershoot, within an allowable value.

[0007] A terminal circuit 20 is connected to the terminal of the connection line 16. Each termination circuit is composed of a series circuit of a resistor 21 and a capacitor 22. The resistance value is determined by the connection line 16
Is selected to be equal to the characteristic impedance of, for example, about 65Ω. The capacitor is determined experimentally so that the signal waveform disturbance at the terminal end, that is, overshoot or undershoot is minimized and the signal delay is equal to or less than an allowable value, for example, about several tens picofarads. A capacitor is selected.

This terminating circuit can be easily constructed with inexpensive components and performs the same function as a terminating resistor in terms of high frequency.
DC or low frequency is equivalent to open. Therefore,
The terminal effectively functions as an overshoot or undershoot, which is a transient signal waveform disturbance at the end, but consumes no power in a steady state.

As a signal line to which a termination circuit is added, for example, it may be added to all signal lines. However, only control signals such as RAS, CAS, and WE (write enable) signal lines having the most critical timing, or control signals Only the signal line and the address signal line may be added. When the terminating circuit 20 is added, the resistor 15 near the connector is not required, but may be left as required by the standard.

FIG. 4 is a circuit diagram showing an example of a memory circuit board to which the present invention is applied. In this memory circuit board, eight DRAM memory elements 41 to 48 are used,
The clock signal is driven via a known clock driver IC 49 having a built-in PLL circuit. Connector 40
Is connected to one end of the above-described distortion preventing resistor 50, and the other end is connected as an address signal line 52 to the address terminals of the eight memory elements 41 to 48. The data input / output signal terminal of the connector 40 is not connected to the above-described distortion prevention resistor, but is directly connected to the data terminals of the eight memory elements 41 to 48 as the data signal line 53.

RAS, CAS, WE, C of connector 40
One end of a distortion prevention resistor 50 is also connected to a control signal terminal such as S (chip select), and the other end is connected as a control signal line 54 to control signal terminals of eight memory elements 41 to 48. Each of the control signal lines 54 is branched into two on the way corresponding to the two memory element groups 41 to 44 and 45 to 48. Further, in the memory elements 44 and 48 at the ends of the respective branched signal lines, a terminating circuit 6 comprising a series circuit of a resistor and a capacitor is provided for each signal line.
0 is connected.

One end of a distortion preventing resistor 50 is connected to the clock signal terminal of the connector 40, and the other end is connected to a clock driver IC 49. One end of a distortion prevention resistor 51 is connected to each of the four output terminals of the driver 49, and the other end is connected as a clock signal line 55 to clock terminals of two memory elements in parallel.
A terminal circuit 61 composed of a series circuit of a resistor and a capacitor is connected to each clock terminal of the eight memory elements.

In this embodiment, the address signal line 5
2 and the data signal line 53 are not provided with a terminating circuit, but these signal lines may be provided with a terminating circuit if necessary.

FIG. 3 is a circuit diagram showing examples of various termination circuits. FIG. 3A shows an example in which a pull-up resistor 30 and a pull-down resistor 31 are used. Since this termination circuit always consumes power, power consumption and heat generation of the substrate increase. FIG. 3B shows two diodes 3 as a termination circuit.
2, 33 are used. In this termination circuit, a current flows only at the time of overshoot or undershoot, and does not consume power in a steady state. FIG. 3 (c) omits the resistance of the terminal circuit composed of the series circuit of the resistor and the capacitor shown in FIG.
Is connected. In addition, as the termination circuit 20 of the present invention, only a pull-down resistor or the like can be used.

Although the embodiment of the present invention has been disclosed above, the present invention may have the following modifications. In the embodiment, the example in which the memory bus is connected via the connector 10 (40) is disclosed. However, the present invention can be applied to wiring to a memory element mounted on a main board.

[0016]

As described above, in the present invention,
In a memory circuit board on which a plurality of memory elements are mounted,
Starting from a predetermined terminal of the connector means, a terminating circuit is connected to an end of a connection line connecting the predetermined terminals of the plurality of memory elements in order. Waveform disturbances such as shoot and undershoot can be suppressed to within an allowable value, and there is an effect that power consumption hardly increases.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a wiring structure of a memory circuit board to which the present invention is applied.

FIG. 2 is an explanatory diagram illustrating a wiring structure in a conventional memory circuit board.

FIG. 3 is a circuit diagram showing examples of various termination circuits.

FIG. 4 is a circuit diagram showing an example of a memory circuit board to which the present invention is applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Connector, 11-14 ... Memory element, 15 ... Resistance, 16 ... Connection line, 20 ... Terminal circuit, 21 ... Resistance, 22
... capacitor, 30 ... pull-up resistor, 31 ... pull-down resistor, 32, 33 ... diode, 34 ... capacitor,
40 connector, 41 to 48 memory element, 49 clock driver IC, 50, 51 resistor, 52 address signal line, 53 data signal line, 54 control signal line, 55
... Clock signal line, 60, 61 ... Terminal circuit

Claims (3)

[Claims] In a memory circuit board having a plurality of memory elements mounted thereon, starting from a predetermined terminal of a connector means, a terminating circuit is connected to an end of a connection line connecting the predetermined terminals of the plurality of memory elements in order. A memory circuit board, comprising: 2. The memory circuit according to claim 1, wherein the connection lines are branched on the memory circuit board, and the terminal circuits are all connected to the ends of the respective branched connection lines. substrate. 3. The memory circuit board according to claim 1, wherein said termination circuit comprises a series circuit of a resistor and a capacitor having a value substantially equal to a characteristic impedance of said connection line on said board.