JP2000278648A - Signal processing unit and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably convert scanning lines with a small capacity line memory. SOLUTION: This signal processing unit A is provided with a plurality of line memories 11, a crystal oscillator 34 that generates the reference clock of an output side, an input side horizontal frequency generating section 25 to measure the input horizontal frequency of image information on the basis of the reference clock, a section 24 for generating the output side reference frequency signal OH-PLL to generate a signal on the basis of the reference clock, and a controller 31 that sequentially writes the scanning lines of the image information to the line memories 11, decides the output side horizontal reference frequency signal OH-PLL generated on the basis of the measured input horizontal frequency IH and the magnification factor of the image information in a vertical direction, and controls the sequential read of the scanning lines from a plurality of the line memories 11 on the basis of the output side horizontal reference frequency signal OH-PLL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a signal processing apparatus and method for converting a scanning line of image information.

[0002]

2. Description of the Related Art Conventionally, there has been provided a signal processing apparatus for performing image processing of scanning line conversion between image signals of different formats. The configuration of a conventional signal processing device will be described with reference to FIG. This signal processing device converts a scanning line using only a line memory.
electronics standards association) It cannot respond to signals other than the standards.

A conventional signal processing device has an image processing device 10 for performing a scanning line conversion process, a control pulse generating device 20 for generating a control pulse, and a control device 31 for controlling each part of the signal processing device. ing.

[0004] The image processing apparatus 10 has a plurality of line memories, performs scanning line processing on input image data, and outputs converted image data. Image processing device 10
Is the IIC (I ² C) _BU connected to the control device 31
S sets the vertical and horizontal conversion rates of the image. The image processing apparatus 10 includes an input-side horizontal frequency signal IH
The image is sequentially written to the line memory according to the cycle of
Images are sequentially read from the line memory in accordance with the cycle of the output side horizontal frequency signal OH.

The image processing apparatus 10 has input image data,
The input side dot clock ICLK synchronized with the input horizontal frequency signal IH, the write pulse WE synchronized with the input side horizontal frequency signal IH, the output side horizontal reference frequency signal OH_PL
An output side dot clock OCLK synchronized with L (phase locked loop) is input. The image processing apparatus 10 outputs the converted image data. Image processing device 1
0 is a bus I that sets the vertical and horizontal conversion rates of the image.
It is connected to the control device 31 by IC_BUS.

The control pulse generator 20 generates a control pulse, and is constituted by a logic circuit. The control pulse generator 20 creates the write pulse WE based on the input side dot clock ICLK synchronized with the input side horizontal frequency signal IH in the write pulse WE creation unit 21. The control pulse generator 20 uses the output-side dot clock OCLK synchronized with the output-side horizontal reference frequency signal OH_PLL in the read pulse RE creating unit 22.
Based on the read pulse RE,
The output side horizontal frequency signal OH and the output side vertical frequency signal OV are generated by the output side horizontal frequency signal OH and the output side vertical frequency signal OV. The control pulse generator 20 generates the output-side horizontal reference frequency signal OH_PLL by dividing the frequency of the output-side reference clock from the crystal oscillator 34 in the output-side horizontal reference frequency signal OH_PLL generation unit 24. The output horizontal frequency signal OH, output vertical frequency signal OV, and output horizontal reference frequency signal OH_PLL generated by the control pulse generator 20 are forcibly reset by the input vertical frequency signal IV. The creation unit 21 for the write pulse WE, the creation unit 22 for the read pulse RE, the creation unit 23 for the output-side horizontal frequency signal OH and the output-side vertical frequency signal OV, and the creation unit 24 for the output-side horizontal reference frequency signal OH_PLL The function of the pulse generator 20 is represented as a functional block.

The control pulse generator 20 includes an input-side horizontal frequency signal IH, an input-side vertical frequency signal IV, an input-side dot clock ICLK, and an output-side dot clock OCLK.
Is entered. The control pulse generator 20 outputs a write pulse W synchronized with the input-side horizontal frequency signal IH.
E, a read pulse RE synchronized with the output horizontal frequency signal OH, an output horizontal frequency signal OH, an output vertical frequency signal OV, and an output horizontal reference frequency signal OH_PLL are output. The write pulse WE and the read pulse RE are input to the image processing device 10. The control pulse generation device 20 includes a bus PULSE_B for setting each pulse.
It is connected to the control device 31 by US. A crystal oscillator 34 is connected to the control pulse generator 20 and supplies an output-side reference clock.

The control device 31 controls each part of the signal processing device, and is constituted by, for example, a microcontroller having a CPU, a ROM, a RAM and the like.

The control unit 31 receives an input-side vertical frequency signal IV. The control device 31 uses the bus IIC_BUS to set the vertical and horizontal directions of the image to the image processing device 10, the bus PULSE_BUS to set each pulse, the control pulse generator 20 to the control pulse generator 20, and the bus PLL_BUS to set the frequency division ratio of the PLL. The input PLL 32 and the output PLL 33 are connected to an input discriminating device (not shown) by a bus for transmitting input signal discrimination data.

The conventional signal processing device comprises an input PLL 32 synchronized with an input horizontal frequency signal IH and an output PLL synchronized with an output horizontal reference frequency signal OH_PLL.
L33 and a crystal oscillator 3 for generating an output-side reference clock
And 4.

The input PLL 32 generates an input dot clock ICLK synchronized with the input horizontal frequency signal IH based on a bus PLL_BUS connected to the control device 31 and setting a frequency division ratio and the like. Input side dot clock IC
LK is an image processing device 10 and a control pulse generator 2
Enter 0.

The output PLL 33 generates an output dot clock OCLK synchronized with the output horizontal reference frequency signal OH_PLL based on a bus PLL_BUS connected to the control device 31 and setting a frequency division ratio and the like. The output side dot clock OCLK is input to the image processing device 10 and the control pulse generator 20.

[0013]

Conventionally, in a signal processing device, an output-side horizontal reference frequency signal OH_PLL is
It is obtained from the signal standard value determined from the input signal determination result and the vertical conversion rate. This output-side horizontal reference signal OH_P
LL is created by dividing the output-side reference clock from the crystal oscillator 43, and the writing and reading phases of the line memory indicate the non-standard signals to be obtained from the table data and the temperature of the input signal. Depending on the variation in characteristics, a shift occurs between the write timing and the read timing. If the shift does not fit in the internal line memory, the converted image is broken.

As described above, the conventional signal processing apparatus that performs scanning line conversion using only a line memory can handle only a signal of the so-called VESA standard. That is,
When the signal processing for converting the scanning line using only the line memory corresponds to a signal other than the so-called VESA standard,
A large amount of line memory is required to stably perform scan line conversion according to the difference between the input frequency and the output frequency for one screen. On the other hand, by synchronizing the input side dot clock ICLK and the output side dot clock OCLK in the vertical (V) cycle, a system for converting scanning lines with a small amount of line memory can be constructed. Operation was unstable.

A signal which is proposed in view of the above-mentioned circumstances of the present invention and which performs a scanning line conversion using only a plurality of line memories so as to operate stably without requiring a large amount of line memories. It is an object to provide a processing device and method.

[0016]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention has a plurality of line memories and converts and outputs scanning lines of input image information.
A reference clock on the output side is generated, an input horizontal frequency of the image information is measured based on the reference clock, an output horizontal frequency is generated based on the reference clock, and scanning of the image information is performed on the plurality of line memories. Lines are sequentially written, and an output frequency generated from the frequency generation step is determined based on the input horizontal frequency measured in the measurement step and a vertical enlargement ratio of the image information. The scanning lines are controlled so as to be sequentially read from the line memory.

More specifically, the present invention performs signal processing for converting a scanning line of image information using only a line memory, real-time measurement of horizontal frequency of input image information, hysteresis processing, and output side. To measure the input horizontal frequency and generate the output horizontal frequency. As a result, it is possible to generate a frequency for generating the timing of writing and reading of the scanning line that does not break down in the line memory.

Further, the memory of the line memory is full (full).
By detecting the write start position and the read start position based on the information of the memory empty (empty), it is possible to create a write and read phase state that does not break down in the line memory. here,
Memory full refers to a state in which image information written in all of the plurality of line memories has not been read, and memory empty refers to a state in which all image information in the plurality of line memories has been read and not written.

By creating these two states, it is possible to perform scanning line conversion that does not break down even in image information outside the so-called VESA standard.

According to the present invention, real-time measurement of input horizontal frequency of input image information, calculation and generation of output horizontal frequency, and full / empty line memory information are performed.
The writing and reading points of the scanning line can be detected, and frequency fluctuations due to temperature characteristics and the like can be dealt with.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a signal processing apparatus and method according to the present invention will be described in detail with reference to the drawings.

As shown in FIG. 1, the signal processing device includes an image processing device 10 for performing a scanning line conversion process, a control pulse generating device 20 for generating a control pulse, and a control device for controlling each part of the signal processing device. 31.

As shown in FIG. 2, the image processing apparatus 10
A plurality of line memories 11 are provided to perform scanning line processing on input image data and output converted image data. The image processing apparatus 10 is connected to the I
The conversion ratio in the vertical and horizontal directions of the image is set by IC_BUS. In the image processing apparatus 10, images are sequentially written to the line memory 11 in accordance with the cycle of the input-side horizontal frequency signal IH, and images are sequentially read from the line memory 11 in accordance with the cycle of the output-side horizontal frequency signal OH.

The image processing apparatus 10 has input image data,
The input side dot clock ICLK synchronized with the input horizontal frequency signal IH, the write pulse WE synchronized with the input side horizontal frequency signal IH, the output side horizontal reference frequency signal OH_PL
The output side dot clock OCLK synchronized with L is input. The image processing apparatus 10 outputs the converted image data, an error flag mem_full which becomes a high (H) level when the built-in line memory 11 is full,
When the built-in line memory 11 becomes empty, an error flag mem_empty which becomes high level is output. The error flag mem_full and the error flag mem_empty are output to the control device 31. The image processing device 10 is connected to the control device 31 via a bus IIC_BUS that sets a conversion ratio in the vertical and horizontal directions of an image. In the image processing apparatus 10, the error flag mem
_Full and the error flag mem_empty are
It is generated by a state discriminator (not shown) including first detection means for detecting a memory full state and a memory empty state and second detection means for detecting an error flag mem_empty.

The control pulse generator 20 generates a control pulse and is constituted by a logic circuit. The control pulse generator 20 creates the write pulse WE based on the input side dot clock ICLK synchronized with the input side horizontal frequency signal IH in the write pulse WE creation unit 21. The control pulse generator 20 outputs the output-side dot clock OCLK synchronized with the output-side vertical reference frequency signal OH_PLL by the read pulse RE generator 22.
Based on the read pulse RE,
The output side horizontal frequency signal OH and the output side vertical frequency signal OV are generated by the output side horizontal frequency signal OH and the output side vertical frequency signal OV. The control pulse generator 20 divides the frequency of the output-side reference clock from the crystal oscillator 34, which is the reference clock generation means, in the input-side horizontal frequency signal IH measuring unit 25 to divide the input-side horizontal frequency signal IH.
Is measured. In the control pulse generator 20, the output side horizontal reference frequency signal OH_OLL is generated by the output side horizontal reference frequency signal OH_PLL generation unit 24 by dividing the frequency of the output side reference clock from the crystal oscillator. Output-side horizontal frequency signal OH, output-side vertical frequency signal OV, output-side horizontal reference frequency signal OH generated by control pulse generator 20
_PLL is forcibly reset by the input side vertical frequency signal IV. Note that the write pulse WE generating unit 21, the read pulse RE generating unit 22, the output horizontal frequency signal OH and the output vertical frequency signal OV generating unit 23, the output horizontal reference frequency signal OH_PLL generating unit 24, and the input side The measurement unit 25 of the horizontal frequency signal IH
2 shows the functions of the control pulse generator 20 as functional blocks. In this specification, the input-side vertical frequency signal IV may be referred to as an input-side vertical (V) pulse, and the output-side vertical frequency signal OV may be referred to as an output-side vertical (V) pulse.

The control pulse generator 20 includes an input-side horizontal frequency signal IH, an input-side vertical frequency signal IV, an input-side dot clock ICLK, and an output-side dot clock OCLK.
Is entered. The control pulse generator 20 outputs a write pulse W synchronized with the input-side horizontal frequency signal IH.
E, a read pulse RE synchronized with the output horizontal frequency signal OH, an output horizontal frequency signal OH, an output vertical frequency signal OV, and an output horizontal reference frequency signal OH_PLL are output. The write pulse WE and the read pulse RE are input to the image processing device 10. The control pulse generation device 20 includes a bus PULSE_B for setting each pulse.
It is connected to the control device 31 by US. A crystal oscillator 34 is connected to the control pulse generator 20 and supplies an output-side reference clock.

The control device 31 controls each part of the signal processing device, and is constituted by, for example, a microcontroller including a CPU, a ROM, a RAM and the like.

The controller 31 receives an input-side vertical frequency signal IV and an error flag from the OR circuit 35. The error flag from the OR circuit 35 is interrupted at the rising edge. The control device 31 transmits a pulse PULSE_BU to the image processing device 10 via the bus IIC_BUS for setting the vertical and horizontal directions of the image.
In S, the control pulse generator 20 is connected to an input discriminator (not shown) by a bus for sending input signal discrimination data to the input PLL 32 and output PLL 33 by a bus PLL_BUS for setting the frequency division ratio of the PLL and the like.

The signal processing device comprises an input PLL 32 synchronized with the input horizontal frequency signal IH, and an output PLL 33 synchronized with the output horizontal reference frequency signal OH_PLL.
A crystal oscillator 34 that supplies an output-side reference clock;
An OR circuit 35 for generating an error flag.

The input PLL 32 generates an input dot clock ICLK synchronized with the input horizontal frequency signal IH based on a bus PLL_BUS that is connected to the control device 31 and sets a frequency division ratio and the like. Input side dot clock IC
LK is an image processing device 10 and a control pulse generator 2
Enter 0.

The output-side PLL 33 generates an output-side dot clock OCLK synchronized with the output-side horizontal reference frequency signal OH_PLL based on a bus PLL_BUS that is connected to the control device 31 and sets a frequency division ratio and the like. The output side dot clock OCLK is input to the image processing device 10 and the control pulse generator 20.

The OR circuit 35 outputs an error flag mem_full from the image processing apparatus 10 that goes high when the line memory 11 is full, and an error flag that goes high when the line memory 11 becomes empty. Perform an OR operation on mem_empty. The results of these calculations are input to the control device 31 as error flags.

The signal processing device converts signals by using only the line memory 11 provided in the image processing device 10 to cope with signals other than the so-called VESA standard. The signal processing apparatus of the present embodiment is different from the conventional signal processing apparatus shown in FIG. 16 in that an input horizontal frequency signal IH that measures an input horizontal frequency signal IH based on an output reference clock from a crystal oscillator 34 is output. The IH measuring unit 25, an error flag mem_full indicating that the line memory 11 is full, and an error flag mem_empty indicating that the line memory 11 is empty.
Is different. Note that the error flag m
em_full and error flag mem_empty
An OR circuit 35 for performing an OR operation is also provided. In FIGS. 1 and 2, parts corresponding to those shown in FIG. 1 are denoted by the same reference numerals in order to facilitate comparison with FIG.

In the signal processing device, the input side horizontal frequency signal IH is measured in real time by the input side horizontal frequency signal IH measuring section 20 of the control pulse generator 20 based on the output side reference clock from the crystal oscillator 34. The output-side horizontal reference frequency signal OH_PLL is determined by calculation of the input-side horizontal frequency signal IH and the vertical conversion rate obtained from the signal determination result of the measurement unit 20. The output side horizontal reference frequency signal OH_PLL is
4 is generated by dividing the output-side reference clock. Output side horizontal frequency signal OH at output side PLL 33 and PL at output side horizontal reference frequency signal OH_PLL
L, the output side dot clock OCL
K changes and the image processing apparatus 10 can perform vertical enlargement and reduction processing of the image. This input / output relationship is based on the line memory 1 built in the image processing apparatus 10.
This is a frequency ratio within which scanning line conversion can be performed without failure within 1. In addition, a write start position and a read start position are detected from the full and empty information of the line memory 11. These input / output relationships are phase relationships in which scanning line conversion can be performed without failure in the line memory 11. From these information, the so-called VESA
Image processing for converting a scanning line is realized using only a few line memories that can respond to input of a video signal other than the standard.

Next, the scanning line conversion processing in the image processing apparatus 10 will be described. The image processing apparatus 10 calculates an output-side horizontal frequency signal OH from the input-side horizontal frequency signal IH according to the vertical conversion rate or the enlargement rate. The image processing apparatus 10 writes the data into the built-in line memory 11 according to the input-side horizontal frequency signal IH,
Scan line conversion is performed by reading image data from 1 in accordance with the output side horizontal frequency signal OH. The output-side vertical frequency signal OV is the same as the input-side vertical frequency signal IV, but the output-side horizontal frequency signal OH changes with respect to the input-side horizontal frequency signal IH according to the vertical conversion rate or magnification of the image.

In the case where the image data is enlarged 1.25 times in the vertical direction, the image processing apparatus 10 supplies the vertical period within the period in which the input-side vertical frequency signal IV indicated by A in FIG. As shown in FIG. 3B, an input video signal having 480 lines in one cycle is input as input image data. This input video signal is enlarged 1.25 times in the vertical direction by the image processing device 10. The video signal enlarged in the vertical direction is an output video having 600 lines in one cycle as converted image data as shown in D in FIG. 3 within a period in which the output side shown in C in FIG. 3 is at a high level. Output as a signal.

As for the horizontal period, the image processing apparatus 10 supplies the input-side horizontal frequency signal IH as shown at A in FIG.
Is entered. As a result of the scanning line processing in the field increase processing apparatus 10, as shown in FIG.
The output horizontal frequency signal OH in which the period of the four horizontal cycles of the input-side frequency signal IH corresponds to the five horizontal cycles,
Is output.

When the image data is to be enlarged 1.5 times in the vertical direction, the image processing apparatus 10 requires the input side vertical frequency signal IV indicated by A in FIG.
As shown in B in FIG.
An input video signal having 0 lines is input. This input video signal is enlarged 1.5 times in the vertical direction by the image processing device 10. The video signal enlarged in the vertical direction is supplied to the D signal in FIG. 5 during the period when the output side indicated by C in FIG.
As shown in FIG.
It is output as an output video signal having a line.

As for the horizontal period, the image processing apparatus 10 supplies the input-side horizontal frequency signal IH as shown at A in FIG.
Is entered. As a result of the scanning line processing in the image processing apparatus 10, as shown by B in FIG. 6, the four horizontal periods of the input-side frequency signal IH are changed to six horizontal periods in accordance with the 1.5-fold enlargement in the vertical direction. Output horizontal frequency signal OH corresponding to
Is output.

FIGS. 3 and 5 described above are timing charts when viewed in a vertical cycle. By changing the conversion rate in the vertical direction, the output-side horizontal reference frequency signal OH_PL
L is changed. Although the input and output signal valid periods are the same, the number of output lines included therein changes. In this way, vertical enlargement and reduction of the image are realized.

FIGS. 4 and 6 are timing charts when FIGS. 3 and 5 are viewed in a horizontal cycle. This shows that the number of lines included in the same time changes in the vertical direction depending on the conversion rate.

Next, the input side PLL 32 and the output side PL
The configuration of L33 will be described with reference to FIG.

The input-side PLL 32 compares the phase of the input-side horizontal frequency signal IH with the divided frequency and outputs an input-side dot clock ICLK. The input-side PLL 32 converts the signal output from the phase comparator 41 into a signal. And a frequency divider 42 which divides the frequency by 1 / N and supplies it to the phase comparator 41. The input-side PLL 32 receives the input-side horizontal frequency signal IH and outputs the input-side dot clock ICLK.

The output-side PLL 33 compares the output-side horizontal reference frequency signal OH_PLL with the frequency-divided phase and outputs the output-side dot clock OCLK, and the signal output from the phase comparator 43. Is divided into 1 / L and given to the phase comparator 43. The output side PLL 33 receives the output side horizontal reference frequency signal OH_PLL from the frequency divider 45, the PLL_RESET which is a reset control signal and the PHASE_EN which is an enable control signal from the logic unit, and outputs the output side dot clock OCLK. Have been.

The frequency divider 45 generates an input-side horizontal frequency signal IH based on the output-side reference clock from the crystal oscillator 34.
Under the control of the control signal calculated from the input horizontal frequency and the vertical conversion rate or enlargement rate according to the above and the reset control signal from the logic unit 46, the output-side reference clock is set to 1
/ M and output-side horizontal reference frequency signal OH_PLL
Output as The frequency divider 45 corresponds to the output side horizontal reference frequency signal OH_PLL creating unit 24, which is a functional block of the control pulse generator 20, for example.

The logic unit 46 outputs a reset control signal PLL_RESET for forcibly resetting the internal divider to the output PLL 33 and an enable control signal PHASE_EN for enabling the phase comparator in accordance with the input-side vertical frequency signal IV. And a reset control signal to the frequency divider 45. The logic unit 46 is provided, for example, in the control pulse generator 20.

In the signal processing device, an error occurs in the input / output relationship due to the bit precision and calculation precision of hardware. In order to absorb the error, the input-side vertical frequency signal I
Force reset with V. Input side vertical frequency signal IV
As a result, the phase comparator 43 of the output PLL 33 is disabled, and at the same time, the frequency divider 44 of the output PLL 33 is reset. As a result, even when the output-side horizontal reference frequency signal OH_PLL becomes discontinuous, the phenomenon that the output-side dot clock OCLK, which is the data read clock generated by the output-side PLL 33, is disturbed is prevented.

The waveform of each part of the circuit shown in FIG. 7 is as shown in FIG. This waveform corresponds to the timing of enabling the phase comparator 43 and the frequency divider 4 of the output PLL 33.
4 shows the timing of resetting.

That is, as shown at A in the figure, the output-side horizontal reference frequency signal OH_PLL shown at B in the figure is disturbed by the input-side V pulse IV, and the periodicity is broken. An enable control signal P for the phase comparator indicated by C in FIG.
During a period when HASE_EN is at a high level, a reset control signal P for forcibly resetting the internal divider shown by D in FIG.
At the timing of the edge t ₁ of the pulse of LL_RESET, the frequency divider 44 of the output PLL 33 is forcibly reset. Due to the forced reset of the frequency divider 44 of the output-side PLL 33, the output-side dot clock OCL
Internal divider output signal OCLK / L obtained by dividing K by 1 / L
Is obtained.

Next, the input waveform when the pulse of the input horizontal frequency signal IH is processed and measured by a counter based on the output reference clock by the crystal oscillator 34 is shown in FIG.
This will be described with reference to FIG. At the rising edge of the waveform of the input side horizontal frequency signal IH, the output value is latched by an internal counter, read out to the control device 31, and the horizontal cycle of the input side horizontal frequency signal IH is measured. The timing of the time point t ₂ at which the register value is read out to the control device 31 is based on the input-side horizontal frequency signal IH.
Is performed outside the range of the section Ta between the rising edges of the pulse in the vertical (V) cycle of the pulse of the signal IHD in which the line other than the line to be measured is masked. The output-side horizontal frequency signal OH is calculated and generated from the vertical conversion rate determined from the measurement result and the signal determination result. This input / output result is a frequency relationship that allows the line memory 11 incorporated in the image processing device 11 to perform scanning line conversion without failure.

The measurement of the pulse of the horizontal cycle of the input-side horizontal frequency signal IH is performed by the measurement block 5 shown in FIG.
Performed at 0. The measurement block 50 latches the first frequency divider 26 and the second frequency divider 27 for dividing the output-side reference clock from the crystal oscillator 34, and the frequency divided by the first frequency divider 26. And a comparator 29 for comparing a signal from the latch unit 28 with a frequency from the second frequency divider 27, and a delay unit 30 for delaying the signal.

The first frequency divider 26 receives the output-side reference clock from the crystal oscillator 34, outputs the frequency-divided signal to the latch 28, and is reset at the rising edge of the pulse from the delay 30. The second frequency divider 27 includes the crystal oscillator 3
4 outputs an output-side reference clock, outputs a frequency-divided signal to the comparator 29, and outputs the input-side vertical frequency signal IV or the output-side horizontal reference frequency signal OH_PL from the comparator 29.
Reset at the rise of L. The latch 28 receives the frequency-divided signal from the first frequency divider 26, latches it at the rising edge of a signal IHD that masks a line other than the line measured by the input horizontal frequency signal IH, reads out the latch data, and outputs the latched data. A control signal for setting the horizontal reference frequency signal OH_PLL frequency division ratio is output to the control device 31. Comparator 2
In 9, a signal that is frequency-divided from the second frequency divider 27 and a signal that is latched from the latch 28 are input, and the output-side horizontal reference frequency signal OH_PLL is supplied to the frequency divider 27 and output to the outside.

In the measurement block 50, a signal IHD obtained by masking a line other than the line on which the input-side horizontal frequency signal IH is measured.
The value of the counter is latched at the rising edge of the counter, and the measurement counter is reset one clock after that. The measurement block 50 corresponds to the input side horizontal frequency signal IH generation section 25 and the output side horizontal reference frequency signal OH_PLL measurement section 24, which are functional blocks of the control pulse generation device 20.

Next, a processing procedure in which the control device 31 reads the result from the measurement block 50, performs a hysteresis process, and calculates the division ratio of the output-side reference clock will be described with reference to FIG.

The controller 31 inhibits the interrupt routine in step S11, performs initialization processing in step S12, and permits the interrupt routine inhibited in step S11 in step S13.

In step S14, the control device 31 sets a V pulse flag indicating the state of the vertical (V) pulse,
At step S15, the counter register value is read. The V pulse flag is cleared by an interrupt process described later.

In step S16, the control device 31 branches the process depending on whether or not the counter register value is the same as the counter value one frame before. If the error between the counter register value read in step S15 and the counter value one frame before is within ± 3, it is determined that they are the same, and the process proceeds to step S17 as “YES”.
O ”and the process proceeds to step S19.

The control device 31 branches the processing in step S17 depending on whether or not the counter register value is the same as the counter value two frames before. If the error between the counter register value read in step S15 and the counter value two frames before is within ± 3, it is determined that they are the same, and the process proceeds to step S18 as "YES".
O ”and the process proceeds to step S19.

In step S18, the control device 31 substitutes the counter register value read in step S15 for the counter value of the current frame. Step S16,
Step S17 and step S18 are performed in step S1.
By comparing the counter register value read out in step 5 with the counter values of one frame before and two frames before, the hysteresis processing is performed by the twice matching and error range processing.

The control device 31 updates the counter values of one frame before and two frames before in step S19, and outputs the horizontal reference frequency signal OH_PLL on the output side in step S20.
Is calculated, and the output-side horizontal reference frequency OH_PLL is set in the control pulse generator 20 in step S21. The frequency division ratio at step S20 is obtained by calculating as follows: output frequency division ratio = current frame counter value × vertical conversion ratio.

The control device 31 branches the processing depending on whether or not the V pulse flag is set in step S22. That is, if the V pulse flag has been reset, “NO” is returned to step S15, and if not, “YES” is returned to step S22. The V pulse flag is cleared by the interrupt processing described below.

As shown in FIG. 12, the interruption of the V pulse flag is interrupted by the edge of the pulse of the input-side vertical frequency signal IV. In step S31, the V pulse flag is cleared. Then, the interrupt routine ends.

Next, the scanning line conversion processing in the signal processing device will be described with reference to FIG. This scanning line conversion process converts a so-called VGA (video graphics array) signal into a so-called SVGA (super video graphics array).
This is converted into a signal.

The input-side vertical frequency signal IV indicated by A in FIG.
An input video signal having 240 lines in one cycle indicated by B in the figure is written to the line memory 11 of the image processing device 10 from a write start position t _W after a predetermined period has elapsed since the signal has risen from a low level to a high level. 240 lines of the input video signal are half of 480 lines of the VGA.

As to reading of the image data of the video signal written in the line memory 11 of the image processing apparatus 10, three cases will be exemplified below based on the reading start position t _R.

The first reading start position t _R1 is indicated by C in FIG.
Is an edge at which the output side vertical frequency signal OV rises from a low level to a high level. The output video signal indicated by D in the figure is obtained by magnifying the input video signal indicated by B in the figure by 1.25 times in the vertical direction, and has 300 lines in one cycle. 300 lines of the output video signal
It is half of VGA 600 lines. Since the first read start position t _R1 is temporally before the write start position t _{W, the} error flag mem_ which becomes a high level when the line memory 11 becomes empty as shown by F in the figure.
There is a section where empty is at a high level. The error flag mem_full, which goes high when the line memory 11 is full, is low, as indicated by E in the figure. Thus, the first read start position t
_{Since R1} is positioned before the writing start position t _{W in} time, there is a period during which the line memory 11 becomes empty and the scanning line conversion process fails. During this period, the error flag mem_e is set.
mpty goes high.

The second reading start position t _R2 corresponds to D in FIG.
Write start position t indicated by the output side vertical frequency signal OV
It is at a position delayed by a predetermined period from _W. The output video signal shown by H in the figure is obtained by magnifying the input video signal shown by B in the figure by 1.25 times in the vertical direction, and has 300 lines in one cycle. The second read start position t _R2 is at a position delayed by a predetermined period from the write start position t _W , and both the error flag mem_full shown by I in the figure and the error flag mem_empty shown by J in the figure are at the low level. As described above, when the read position t _R is gradually moved backward from the first read start position t _R1, the second read position t which does not have any of the error flags mem_full and mem_empty. _R2 exists. The second reading position t _R2 is a position where the processing of the video signal can be processed only by the line memory 11 provided inside the image processing apparatus 10. That is, the second read start position t at which the image processing for scanning line conversion can be performed only by the internal line memory 11 without the line memory becoming full or empty
_R2 exists.

The third reading start position t _R3 is equal to K in FIG.
As shown by the output-side vertical frequency signal OV, the second read start position t _R2 indicated by the G-side output vertical frequency signal OV in FIG. The output video signal shown by L in the figure is obtained by magnifying the input video signal shown by B in the figure by 1.25 times in the vertical direction.
One cycle has 300 lines. Since the third read start position t _R3 is at a position delayed by a predetermined period from the second read start position t _R2 , the line memory 11 becomes full, and there is a period during which the scanning line conversion process breaks down. The error flag mem_full becomes high level.
The error flag mem_empty is at a low level as indicated by N in the figure. As described above, since the third read start position t _R3 is located before the write start position t _{W in} time, there is a period in which the line memory 11 is full. In this period, the error flag mem_full is set to the high level. Become.

Referring to FIG. 14, a description will be given of a processing procedure of scanning line conversion that does not break down the line memory as in the above-described second reading start position t _R2 . This processing procedure is performed when the input-side vertical frequency signal IV changes.
The determination result of the error flag mem_full and the error flag mem_empty is received from the signal determination device of 0, and the input / output relationship of the write start position t _W and the read start position t _R is searched. This input / output relationship is a phase relationship in which the line memory 11 included in the image processing apparatus 10 can perform scan line conversion without failure.

The control device 31 inhibits the interrupt routine in step S41, performs initialization processing in step S42, permits the interrupt routine in step S43, and in step S44, the V pulse indicating the state of the input-side vertical frequency signal IV. Set a flag.

At step S45, the control device 31 outputs an error flag mem_full that outputs a high level when the line memory 11 of the image processing device 10 is full.
The process branches depending on whether or not to initialize an error flag mem_empty that outputs a high level when the line memory 11 becomes empty. The initialization of the error flag is executed, for example, when the input horizontal frequency IH changes. The control device 31 sets the error flag mem_f
If the "ull" and the error flag mem_empty are to be initialized, the process proceeds to step S46 as "YES", and if not, the process proceeds to step S50 as "NO".

In step S46, the control device 31 initializes a search frame counter for counting the read start position to be searched for on a frame basis to the first frame.
In step S47, a write start position (line) is initialized and a write period is set. In step S48, a read start position (line) is initialized and a read period is set. In step S49, an error flag holding area is initialized. The control device 31 sets the write period to half of the normal operation in step S47, and sets the read period to half of the normal operation in step S48.

Here, the search frame counter is
This is a counter that counts two frames. A set value (register value) for detecting an error frame is set in the first frame, and an error is detected in the second frame.
That is, the error is detected as one time over two frames of the register setting period and the error detection period. This is used to prevent malfunction due to multiple interrupts.

At step S50, the control device 31 sets the error flag mem_full and the error flag mem_
Based on the empty, the process branches depending on whether or not the optimum read start position (line) is being searched. When the search is being performed, the control device 31 outputs “YE
The process proceeds to Step S51 as “S”, and proceeds to Step S60 when “NO” when the search is not being performed.

In step S51, the control device 31 branches the process depending on whether or not the search frame counter is the first frame. Control device 31 determines “YES” when the search frame counter is the first frame.
The process proceeds to step S52, and when the frame is not the first frame, “NO” is determined and the process proceeds to step S56.

The controller 31 prohibits the interruption by the error flag in step S52, increments and sets the read start line in step S53, sets the subframe counter to 2 in step S53, and sets the subframe counter to 2 in step S55. Enable the disabled error flag interrupt.

The control device 31 initializes the error flag of the current frame in step S56. The control device 31 branches depending on whether or not the V pulse flag has been reset in step S57. When the V pulse flag has been reset, the control device 31 proceeds to step S58 with “NO”, and when not reset, returns “Y”.
The process returns to step S57 as "ES". In step S57, an interrupt for an error flag is awaited. The V pulse flag is cleared by the interrupt, which will be described with reference to the flowchart of FIG. did.

The control device 31 updates the error flag holding area in step S58, and sets the search frame counter to 1 in step S59. The update of the error flag area in step S58 is performed by a bit shift.

The control device 31 determines in step S60 that the error flag mem_full and the error flag mem_e
Based on mpty, the process branches depending on whether or not the search for the optimum read start position (line) has been completed. When the search for error flag mem_full and error flag mem_empty is completed, control device 31 proceeds to step S61 as “YES”, and when not completed, proceeds to step S64 as “NO”. Search completion is determined by the fact that the read start line has reached 64 lines.
If "NO", it is in the normal operation state.

The control device 31 sets “00” in step S61.
1 is detected, and “10” is determined in step S62.
The line that becomes "0" is detected, and the center value of the detected line is calculated and detected in step S63. The line that becomes "001" in step S61 is obtained by detecting the line that changes from the normal operation area to the error occurrence area. The line that becomes "100" in step S62 is performed by detecting a line that changes from the error occurrence area to the normal operation area.

The control device 31 branches the process depending on whether or not the V pulse flag has been reset in step S64. When the V pulse flag has been reset, control device 31 determines that the determination is "NO" and proceeds to step S44.
If not, the process returns to step S64 as "YES". The V pulse flag is
It is cleared by the V pulse flag interrupt, which has been described with reference to the flowchart of FIG.

Next, the interruption of the error flag mem_full and the error flag mem_empty will be described.

As shown in FIG. 15, the interrupts of the error flag mem_full and the error flag mem_empty are interrupted at the rising edge of the error flag. In step S71, the current frame error flag is set. Then, the interrupt routine ends.

As described above, the signal processing apparatus of the present embodiment writes in the line memory 11 inside the image processing apparatus 10 in synchronization with the input-side horizontal frequency signal IH, converts the scanning line, and then converts the input-side horizontal frequency signal Reading is performed using the output-side horizontal frequency signal OH calculated from the IH and the magnification in the vertical direction.

The signal processing apparatus of the present embodiment measures the input-side horizontal frequency signal IH in real time using the output-side reference clock from the crystal oscillator 34 provided on the output side. The read clock on the output side is calculated from the value and the conversion rate in the vertical direction, and the ratio of the write clock to the line memory 11 and the read clock is obtained. By generating this read clock by dividing the output side reference clock,
This realizes a write and read frequency relationship that does not cause a breakdown in the internal line memory 11.

The signal processing device according to the present embodiment has a line memory 11 in an image processing device 10 on a writing side.
A means for indicating whether the line memory 11 is full and a means for indicating whether or not the line memory is empty are provided on the read side, and a write start position t such that they do not fail.
By detecting _W and the read start position t _R ,
Writing and reading without failure in the line memory 11 are realized.

The signal processing apparatus according to the present embodiment performs a forced reset of the read-side horizontal reference frequency signal OH_PLL calculated from the input-side horizontal frequency signal IH and the vertical conversion rate with an input vertical pulse. In addition, the error due to the bit length of the configuration hardware and the accuracy of calculation is absorbed to reduce the amount of line memory used.

The signal processing device of the present embodiment uses the internal divider 4 of the output-side PLL 34 synchronized with the read-side horizontal reference frequency signal OH_PLL in the above case.
4 and the phase comparator 43 are disabled, and the output side PLL is disturbed by the disturbance of the output side horizontal reference frequency signal OH_PLL on the read side due to the forced reset.
The data read clock generated at 34 is prevented from being disturbed.

The signal processing apparatus according to the present embodiment measures the input-side horizontal frequency signal IH in real time using the output-side reference clock from the crystal oscillator 34 provided on the output side, and gives the result a hysteresis characteristic to reduce noise, An output-side horizontal reference frequency signal OH_PLL that is stable against a measurement error is generated.

[0090]

As described above, according to the present invention,
Scanning line conversion can be performed stably even when a signal outside the VESA standard is input using only a small number of line memories. Further, it is possible to cope with temperature characteristic fluctuation of the input signal frequency. Further, it is not necessary to synchronize the data write clock on the output side with the data write clock on the input side in a vertical cycle, and the operation is stabilized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a signal processing device according to an embodiment.

FIG. 2 is a block diagram illustrating a configuration of an image processing apparatus.

FIG. 3 is a timing diagram viewed in a vertical cycle when an image is enlarged 1.25 times in the vertical direction.

FIG. 4 is a timing diagram viewed in a horizontal cycle when an image is enlarged 1.25 times in the vertical direction.

FIG. 5 is a timing diagram viewed in a vertical cycle when an image is enlarged 1.5 times in the vertical direction.

FIG. 6 is a timing diagram viewed in a horizontal cycle when an image is enlarged 1.5 times in the vertical direction.

FIG. 7 is a block diagram illustrating a configuration of an input-side PLL and an output-side PLL.

FIG. 8 is a diagram showing waveforms in an input PLL and an output PLL.

FIG. 9 is a diagram showing a signal obtained by masking a line other than a line to be measured of an input horizontal frequency signal.

FIG. 10 is a block diagram illustrating a configuration of a measurement block.

FIG. 11 is a diagram illustrating a process of determining a frequency division ratio of an output-side reference clock.

FIG. 12 is a diagram showing a V-pulse interruption process.

FIG. 13 is a diagram showing a waveform when a VGA standard scanning line is converted into an SVGA standard scanning line.

FIG. 14 is a flowchart illustrating a process of converting a scanning line.

FIG. 15 illustrates an error flag interrupt process.

FIG. 16 is a diagram showing a schematic configuration of a conventional signal processing device.

[Explanation of symbols]

Reference Signs List 10 image processing device, 20 pulse generator, 31 controller, 33 input side PLL, 34 output side PLL

Claims (6)

[Claims] 1. A signal processing apparatus for converting a scanning line of input image information and outputting the converted line, comprising: a plurality of line memories; a clock generating means for generating a reference clock on an output side; Measuring means for measuring an input horizontal frequency of the image information based on a clock; frequency generating means for generating an output horizontal frequency based on a reference clock from the clock generating means; and The scanning lines are sequentially written, and the output frequency generated from the frequency generation unit is determined based on the input horizontal frequency measured by the measurement unit and the magnification ratio of the image information in the vertical direction. Control means for controlling the scanning lines to be sequentially read from the line memory. 2. The apparatus according to claim 1, further comprising: first detection means for detecting that the plurality of line memories are in a memory full state; and second detection means for detecting that the plurality of line memories are in a memory empty state. The control means includes: a controller that controls the plurality of line memories to be in a memory full state and a memory empty state based on detection results from the first detection means and the second detection means. 2. The signal processing device according to claim 1, wherein timing of writing and reading of the scanning line to the plurality of line memories is controlled. 3. The signal processing apparatus according to claim 1, wherein said control means controls the output horizontal frequency generated by said frequency generation means to be initialized by a vertical synchronization signal of said image information. apparatus. 4. The frequency generating means includes: phase comparing means for comparing the phase of a reference clock from the clock generating means with another signal; and dividing the signal from the phase comparing means as the other signal. 4. A frequency dividing means for inputting to the phase comparing means, wherein the control means controls the phase comparing means and the frequency dividing means to be initialized by the vertical synchronizing signal. A signal processing device according to claim 1. 5. The signal processing apparatus according to claim 1, wherein said measurement means has a hysteresis characteristic with respect to the measurement of said input horizontal frequency. 6. A signal processing method having a plurality of line memories and converting and outputting scanning lines of input image information, comprising: a clock generating step of generating a reference clock on an output side; A measuring step of measuring an input horizontal frequency of the image information based on the reference clock of; a frequency generating step of generating an output horizontal frequency based on the reference clock from the clock generating step; Write the scanning lines of information in order, determine the output frequency generated from the frequency generation step based on the input horizontal frequency measured in the measurement step and the vertical magnification of the image information, the output frequency A control step of controlling the scanning lines to be sequentially read from the plurality of line memories. .