JP2000270207A - Image processor and display device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize miniaturization and cost-reduction for an image processor that applies resolution conversion through parallel processing attended with a prescribed interpolation arithmetic operation. SOLUTION: A data latch 2 selects all original pixel data that can be required for each one processing for resolution conversion through parallel processing attended with a prescribed interpolation arithmetic operation on the basis of a data read control signal DRC generated in response to the result of a sum using a magnification M in a constant adder circuit 6, and then a selector 4 selects the original pixel data required for each of output pixel data (pixel data of a picture after resolution conversion) on the basis of a selection signal C generated in response to the result of addition.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing apparatus for converting the resolution of an image.

[0002]

2. Description of the Related Art Conventionally, input pixel enlargement processing has been performed for each pixel. However, in recent years, when a resolution conversion of an image to a higher resolution is required or a real-time resolution conversion process is required as in a computer display using a liquid crystal display, a plasma display (PDP), etc. A method of obtaining a plurality of pixel data of an image in parallel (hereinafter referred to as “perform resolution conversion by parallel processing”) has been adopted.

When performing resolution conversion by parallel processing, especially when performing resolution conversion at an image magnification ratio of a rational number,
The process of selecting pixel data (hereinafter, referred to as “original pixel data”) of an input image to be subjected to resolution conversion becomes complicated. Japanese Patent Application Laid-Open No. 10-63827 discloses a parallel processing method in which it is determined whether or not original pixel data is repeatedly used depending on whether a carry occurs when a constant is added. There is disclosed an image processing apparatus that performs resolution conversion according to.

[0004]

Here, each pixel data of the image after the resolution conversion is performed with a predetermined interpolation calculation process, that is, by performing a predetermined interpolation calculation using a plurality of original pixel data. In order to perform the resolution conversion by the parallel processing after obtaining the above, it is necessary to read more original pixel data from the data latch in each processing, but this is disclosed in the above publication. In the image processing apparatus, each necessary original pixel data is selected by an individual selector, and it is necessary to specify addresses by the number of necessary original pixel data, so that the number of buses greatly increases. For example, the configuration becomes complicated. as a result,
There is a great possibility that the size and cost of the image processing apparatus will increase.

Accordingly, an object of the present invention is to provide an image processing apparatus which performs resolution conversion by parallel processing with a predetermined interpolation operation, and which is easy to reduce in size and cost. I do.

[0006]

In order to achieve the above object, an image processing apparatus according to the present invention sequentially holds a plurality of input pixel data and sequentially changes a read address which changes according to a data read control signal. Has a pointer,
First data holding means for simultaneously outputting pixel data held at a plurality of addresses satisfying a predetermined relationship with an address corresponding to the read address pointer; and a plurality of data output from the first data holding means. Selecting means for selecting pixel data according to a selection signal from the pixel data;
A predetermined interpolation operation is performed using the pixel data selected by the selection unit, an interpolation operation unit that outputs the calculation result, and an addition using a previous addition result and a constant are sequentially performed,
The data read control signal and the constant addition means for generating the selection signal in accordance with whether or not a carry has occurred in the addition result.

With the above arrangement, all the original pixel data which may be required in each processing for performing resolution conversion by parallel processing with a predetermined interpolation operation is selected by the first data holding means. Then, original pixel data required for each output pixel data (pixel data of the image after the resolution conversion) is selected by the selection unit.

According to a second aspect of the present invention, there is provided the image processing apparatus according to the first aspect, further comprising:
A second data holding means for holding a plurality of input pixel data, and a sub-scan interpolation for performing a predetermined interpolation operation using the pixel data output from the second data holding means and outputting the calculation result Calculating means, and pixel data necessary for causing pixel data of an image whose resolution has been converted in the sub-scanning direction by performing a predetermined interpolation calculation to be sequentially output from the sub-scanning interpolation calculating means in the main scanning direction. And means for controlling the data to be sequentially output from the second data holding means, and inputting the data output from the sub-scanning interpolation means to the first data holding means.

With the above arrangement, pixel data of an image whose resolution has been converted in the sub-scanning direction by performing an interpolation operation is sequentially input to the first data holding means in the main scanning direction. In performing the resolution conversion by the parallel processing after performing the interpolation operation in both the direction and the sub-scanning direction, it is not necessary to increase the number of data holding units for holding the pixel data.

According to a third aspect of the present invention, in the image processing apparatus according to the first or second aspect,
The interpolation calculation means performs a linear interpolation calculation,
An interpolation coefficient generation means for generating an interpolation coefficient for a linear interpolation operation performed by the interpolation operation means using the addition result of the constant addition circuit.

With the above configuration, it is necessary to generate a data read control signal and a selection signal when generating an appropriate interpolation coefficient according to the positional relationship between the original pixel data and the output pixel data for each process. Since the result of addition performed by the constant adding means is used, it is not necessary to provide another means for generating the interpolation coefficient.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an image processing apparatus according to a first embodiment of the present invention. Although not shown in the figure, the same clock is supplied to each block, and each block operates in synchronization with the clock.

Pixel data of an input image is held in a data latch 1. The data latch 1 outputs the pixel data held at the address indicated by the read address signal RA output from the address counter 3.

The pixel data output from the data latch 1 is sequentially input to the data latch 2. The data latch 2 has a data write address pointer, and holds input pixel data at an address indicated by the data write address pointer. The data write address pointer sequentially counts up.

The data latch 2 has a read address pointer, and pixel data held at three consecutive addresses starting from the address indicated by the read address pointer are arranged in order from the pixel data held at the youngest address. The data is output as data OUT ₀ , OUT ₁ , and OUT ₂ . The read address pointer changes in synchronization with the clock in accordance with the 2-bit data read control signal DRC output from the constant addition circuit 6.

Specifically, the read address pointer is:
Assuming that the bit data is written from the left in order from the most significant bit, if the data read control signal DRC is (00), it does not increase and the data read control signal DRC becomes (0).
If it is 1), it is increased by one, and if the data read control signal DRC is (10), it is increased by two.

Thus, A, B, C, D, E, F,...
Is stored in the data latch 2 in the order described, the three pixel data OU being output
In the state where T ₀ , OUT ₁ , and OUT ₂ are the three pixel data A, B, and C, respectively, at the next timing synchronized with the clock, the output state changes if the data read control signal DRC is (00). In the case of (01), the three pixel data of B, C, and D are shifted by one, and in the case of (10), the three pixel data of C, D, and E are shifted by two, respectively. The state changes to the state of being output as OUT ₀ , OUT ₁ , and OUT ₂ .

The address counter 3 sequentially counts up the output read address signal RA, but does not perform the count operation while the 1-bit full signal F output from the data latch 2 is (1). . That is, the full signal F is a disable signal for the count operation of the address counter 3. Note that data latch 2
Performs a counting operation with the full signal F being (0), but when it becomes impossible to hold data any more, the full signal F is set to (1) and the counting operation is stopped.

The selector 4 has three input terminals I ₀ , I ₁ , I
₂ and two output terminals O ₁ and O _{2. If} the 1-bit selection signal C is (0), pixel data input from the input terminals I ₀ and I ₁ are output to the output terminals O ₁ and O ₁ , respectively. Output from O ₂ , while if the selection signal C is (1), the pixel data input from the input terminals I ₁ and I ₂ are output from the output terminals O ₁ and O ₂ , respectively. Note that three pixel data OUT ₀ , OUT ₁ , and OUT ₂ output from the data latch 2 are input to input terminals I ₀ , I ₁ , and I ₂ of the selector 4, respectively.

The linear interpolation operation circuit 5-1 includes a data latch 2
Using the pixel data OUT ₀ and OUT ₁ output from the
The linear interpolation operation circuit 5-2 outputs 2
Pixel data (OUT ₀ and OUT ₁ or OUT ₁ and O
Using UT ₂ ), a linear interpolation operation is performed, and the operation result is output.

The constant addition circuit 6 sequentially performs an addition operation using the input enlarged value M, and generates and outputs a data read control signal DRC and a selection signal C according to the operation result. The control circuit 7 controls the operation of each block.

FIG. 2 shows the configuration of the constant adding circuit 6. The input of the multiplier 61 is provided with the enlarged value M,
1 outputs the enlarged value M twice. The output of the multiplier 61 is input to an (n + 2) -bit adder 63 via a switch 62 that is turned ON / OFF by a control circuit 67. The output of the lower n bits of the output of the adder 63 and the initial value S are input to the selector 64. Adder 6
The upper 2 bits of the output of 3 are the data read control signal DRC
Is output as

The selector 64 outputs one of two inputs, and the switching is performed by the control circuit 67. The output of the selector 64 is provided to the input of the latch circuit 65, and the output of the latch circuit 65 is input to the adder 63. The adder 66 is an (n + 1) -bit adder, and receives the upper n bits of the output of the adder 63 and the enlarged value M. The upper one bit of the output of the adder 66 is output as the selection signal C.

The control circuit 67 switches the switch 62 from OFF to ON after the pixel data is read from the data latch 2 and before the next pixel data is read. The selector 64 is switched from outputting the initial value S to outputting the upper n bits of the output of the adder 63.

In the above configuration, the control circuit 7 performs initialization before starting the processing. Specifically, initialization of the count value of the address counter 3, initialization of the read and write address pointers of the data latch 2, and erasure of the data held in each of the data latch 1 and the data latch 2 are performed. Further, the switch 62 of the constant adding circuit 6 is turned off, and the selector 64 is switched to a state in which the initial value S is output from the selector 64 so that the latch circuit 65 holds the initial value S.

When the data processing is started, the operation of the circuits subsequent to the data latch 2 is stopped until the required amount of data is held in the data latch 2, and the pixel data necessary for the linear interpolation operation is stopped. The process is started after waiting for (specifically, the first three pixel data).

The original pixel data held in the data latch 1 is sequentially read from the first data and written to the data latch 2. When the full signal F is output from the data latch 2, data cannot be written to the data latch 2. However, when the full signal F is not output, the data is sequentially written to the data latch 2. This is realized by an address counter 3 that specifies an address from which data is read from the data latch 1 and sequentially adds the addresses while disabling the full signal F.

The pixel data OUT ₀ , OUT ₁ , and OUT ₂ output from the data latch 2 carry the result obtained by adding twice the enlargement value M in the constant addition circuit 6 as the data read control signal DRC, and thereby carry. Does not change unless a digit occurs, and 1 when a digit occurs.
The original pixel data is shifted, and when a carry occurs by two digits, the original pixel data is shifted by two.

Then, the pixel data OUT ₀ , OUT ₁ , OUT outputted from the data latch 2 changing in this manner.
For the _2, linear interpolation using the pixel data OUT ₀ and OUT ₁ is performed by the linear interpolation operation circuit 5-1,
The constant addition circuit 6 adds the enlarged value M to the previous addition result.
As a result, if no carry occurs, the same pixel data OUT ₀ used in the linear interpolation operation circuit 5-1 is used.
And the linear interpolation operation using the OUT _1, whereas, the linear interpolation operation using pixel data OUT ₁ and OUT ₂ upon failure carry is performed respectively by linear interpolation calculation circuit 5-2.

As described above, the resolution conversion is performed by the parallel processing of two pixels with the linear interpolation operation.
The resolution of the image is converted at an enlargement ratio of 2 ⁿ / M (enlargement value). In the present embodiment, first, all the original pixel data which may be used for the linear interpolation operation in one process is selected by the data latch 2, and then the linear interpolation operation is performed for each output pixel data. The selector 4 selects the original pixel data used in the data latch 2 and the selector 4 to select the original pixel data necessary for performing the resolution conversion by the parallel processing with the linear interpolation operation.
The original pixel data can be selected using only the carry signal indicating whether a carry has occurred by adding the enlargement value M. As a result, the configuration is simplified, for example, by suppressing an increase in the number of buses, and the size and cost of the device can be reduced.

When the simultaneity of the processing is required as in the case of a computer display, the processing after the data latch 2 may be performed for each parallel pixel. Since control is performed by the signal F, control is facilitated. Further, in the first embodiment, since processing is not performed between the data latch 1 and the data latch 2, it is not necessary to define the data transfer mode between them as long as the output pixel data throughput condition is satisfied. Absent. Further, the switch 62 can be omitted by considering the timing problem.

FIG. 3 is a block diagram showing an image processing apparatus according to a second embodiment of the present invention. The same parts as those in FIG. 1 which is a block diagram of the first embodiment are denoted by the same reference numerals, and description thereof is omitted. Reference numeral 8 denotes a linear interpolation operation circuit that performs an interpolation operation using the pixel data output from the data latch 1,
The operation result is output to the data latch 2. Further, the linear interpolation operation circuit 8 operates using the full signal F output from the data latch 2 as a disable signal, similarly to the address counter 3.

The data latch 1 outputs pixel data based on the read address signal RA output from the address counter 3. As a result, the pixel data of the image whose resolution has been converted in the sub-scanning direction by performing the linear interpolation operation The address counter 3 generates a read address signal RA such that are sequentially output from the interpolation calculation means 8 in the main scanning direction.

With the above configuration, the input image is subjected to the linear interpolation operation by the linear interpolation operation circuit 8 to convert the resolution in the sub-scanning direction.
A linear interpolation operation is performed by 1 and 5-2 to convert the resolution in the main scanning direction, and a resolution conversion is performed by parallel processing. Thus, in the second embodiment,
The resolution conversion can be performed by parallel processing after performing the linear interpolation operation in both the main scanning direction and the sub-scanning direction.

Here, in the first embodiment, when pixel data of an image to be subjected to resolution conversion is sequentially input to the data latch 2 in the main scanning direction, the linear interpolation operation means 5-
From 1 and 5-2, pixel data of an image whose resolution has been converted in the main scanning direction is sequentially output in the main scanning direction. By performing a linear interpolation operation using these pixel data, the sub-scanning is performed. If the resolution is to be converted in the direction, the pixel data is sequentially output in the main scanning direction from the linear interpolation calculation means 5-1 and 5-2, so that a data latch for holding the pixel data is additionally required. .

On the other hand, in the second embodiment, by providing the linear interpolation operation means 8 between the data latch 1 and the data latch 2, the data latch 2 performs the linear interpolation operation to Since pixel data of an image whose resolution has been converted in the scanning direction is sequentially input in the main scanning direction,
A data latch for holding data is not required except for the data latch 1 and the data latch 2, so that the size and cost of the device can be reduced.

In the second embodiment, the input enlargement value is sequentially added to the previous addition result, and the data output from the data latch 1 is selected using the carry signal generated by this addition. If so, the magnification in the sub-scanning direction can be made variable. Further, an interpolation coefficient of the linear interpolation operation performed by the linear interpolation operation circuit 8 may be generated using the result of the addition.

FIG. 4 is a block diagram of an image processing apparatus according to a third embodiment of the present invention. The same parts as those in FIG. 3 which is a block diagram of the second embodiment are denoted by the same reference numerals, and description thereof is omitted. 9 is an interpolation coefficient generation circuit, and generates an interpolation coefficient of the linear interpolation operation performed by a linear interpolation operation circuit 5-1 using a lower n bits A ₁ of the output of the adder 63 of the constant addition circuit 6, Adder 66 in constant addition circuit 6
Linear interpolation operation circuit 5 with the lower n bits A ₂ of the output of the
Generate an interpolation coefficient for the linear interpolation operation performed in -2.

With the above-described configuration, an appropriate interpolation coefficient corresponding to the positional relationship between the original pixel data and the output pixel data is generated for each processing, and a linear interpolation operation is performed using the generated interpolation coefficient. Therefore, the resolution-converted image becomes more faithful to the original image. In the third embodiment, the addition performed by the constant addition circuit 6, which is necessary for generating the data read control signal DRC and the selection signal C, is not necessary to separately provide a circuit for generating the interpolation coefficient. Since the interpolation coefficient of the linear interpolation operation is generated by using the operation result of the operation, it is possible to reduce the size and cost of the device.

In each of the above embodiments, resolution conversion is performed by parallel processing of two pixels, but the present invention can be easily applied to parallel processing of three or more pixels. For example, 3
In order to perform resolution conversion by parallel processing of k pixels where ≤k, a block diagram of the entire apparatus may be as shown in FIG.

In the figure, the data latch 2 starts at the address indicated by the read address pointer (k +
1) The pixel data stored in the consecutive addresses is sequentially stored in the pixel data O in order from the pixel data stored in the youngest address.
UT ₀ , OUT ₁ , OUT ₂ ,..., OUT _k are output. The data latch 2 has a data read control signal DR
The operation of increasing C by a numerical value when C is considered as a binary number is performed in synchronization with a clock.

The selectors 4-1, 4-2,..., 4- (k-
1) has the same configuration as the selector 4. The input terminals I ₀ , I ₁ , and I ₂ include pixel data OUT ₀ , OUT ₁ , and OUT ₂ for the selector 4-1 and the selector 4-2.
, The pixel data output from the output terminal O ₁ of the selector 4-1, the pixel data output from the output terminal O ₂ , the pixel data OUT ₃ ,..., The selector 4- (k−
Regarding 1), the output terminal O ₁ of the selector 4- (k-2)
Pixel data output from the pixel data output from the output terminal O _2, pixel data OUT _k is inputted. The selector 4-1,4-2, ..., 4- (k- 1) each selection signal C _1, C _2, ..., to switch the pixel data output by C _k. Selectors 4-1 and 4-2,
, 4- (k-1) are output from the linear interpolation operation circuits 5-2, 5-3,.
Is input to

If processing delays become a problem by increasing the number of pixels to be processed in parallel, it is better to increase the speed by pipelining or the like.

The configuration of the constant addition circuit 6 may be as shown in FIG. The same parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. In the figure, an adder 63 is set to (n
+ Α) bits, and outputs the higher α bits of the output as a data read control signal DRC. here,
α is an integer part of (1 + log ₂ k).

Adders 66-1, 66-2,..., 66-
(K-1) is an adder of (n + 1) bits. The upper n bits of the output of the adder 63 and the expanded value M are input to the input of the adder 66-1, and the input of the adder 66-2 is Adder 66-
.., The adder 6
The higher n bits of the output of the adder 66- (k-2) and the enlarged value M are input to the input of 6- (k-1). The adders 66-1, 66-2, ..., 66-
The upper one bit of the output of (k-1) is the selection signal C
_1, C _2, ..., a C _k-1.

The adders 63, 66-1, 66-2,
.., 66- (k-1) output lower n bits A ₁ , A ₂ ,
A _3, ..., respectively by using A _k linear interpolation operation circuit 5
It is possible to generate interpolation coefficients for linear interpolation operations performed in 1, 5-2, 5-3,..., 5-k.

FIG. 7 is a block diagram of a display device according to an embodiment of the present invention. In the figure, 101 is an A / D converter, 102 is a switch, 103 is an image processing device, 104 is an image display device such as an LCD panel,
105 is a timing signal generation circuit, and 106 is a control circuit.

The A / D converter 101 converts an externally input analog image signal (such as analog RGB) into a digital image signal and outputs it. The switch 102 receives the digital image signal converted by the A / D converter 101 and the digital image signal input from the outside, and selects and outputs one of them according to an instruction from the control circuit 106. The image signal output from the switch 102 is input to the image processing device 103. The image processing device 103 is any one of the image processing devices according to the above-described embodiments, and converts an image resolution at a predetermined magnification and outputs the image.

The image display device 104 is an image processing device 103
An image is formed from the image signal output from the device and displayed.
The timing signal generation circuit 105 generates a timing signal based on a horizontal / vertical synchronization signal of an externally input image signal. Each circuit block operates in synchronization with the timing signal and a clock supplied from a clock signal supply circuit (not shown). The control circuit 106
The operations of the A / D converter 101, the switch 102, and the image processing device 3 are controlled so that the display device operates smoothly.

According to the above-described display device, since any one of the above embodiments is employed as the image processing device 103, the resolution of the input image is converted while the size and cost are reduced. It can be enlarged and displayed.

[0051]

As described above, according to the image processing apparatus of the first aspect, it is possible to select all the original pixel data which may be used for the interpolation operation in one process and to select each output pixel data. The selection of the original pixel data used for the interpolation operation is separated for each case, whereby the selection of the original pixel data is performed using only the carry signal indicating whether a carry has occurred by adding the enlarged value. As a result, the configuration is simplified, for example, the increase in the number of buses is suppressed, so that when performing resolution conversion by parallel processing with interpolation operation, it is possible to reduce the size and size of the device. Cost reduction can be realized. This effect becomes more remarkable as the number of pixels to be processed in parallel increases.

According to the image processing apparatus of the present invention, when the resolution conversion is performed by parallel processing after performing the predetermined interpolation calculation in both the main scanning direction and the sub-scanning direction, the interpolation calculation is performed. By doing so, the pixel data of the image whose resolution has been converted in the sub-scanning direction is sequentially input to the first data holding means in the main scanning direction, so that it is not necessary to increase the number of means for holding the pixel data. And cost reduction can be realized.

Further, according to the image processing apparatus of the third aspect, when performing a linear interpolation operation with an interpolation coefficient corresponding to an enlargement factor, the carry processing can be performed without providing a separate circuit for generating an interpolation coefficient. Since the operation result of the addition operation required to generate a signal is used to generate an interpolation coefficient, downsizing and cost reduction can be realized.

According to the display device of the fourth aspect, the size of the input image can be converted and the image can be enlarged and displayed while realizing miniaturization and cost reduction.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a constant adding circuit.

FIG. 3 is a block diagram of an image processing apparatus according to a second embodiment of the present invention.

FIG. 4 is a block diagram of an image processing apparatus according to a third embodiment of the present invention.

FIG. 5 is a block diagram of an image processing apparatus when performing parallel processing of three or more pixels.

FIG. 6 is a block diagram of a constant adding circuit in FIG. 5;

FIG. 7 is a block diagram of a display device according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data latch 2 Data latch 3 Address counter 4 Selector 5-1 and 5-2 Linear interpolation operation circuit 6 Constant addition circuit 7 Control circuit 8 Linear interpolation operation circuit 9 Interpolation coefficient generation circuit 61 Multiplier 62 Switch 63 Adder 64 Selector 65 Latch circuit 66 Adder 67 Control circuit 101 A / D converter 102 Switch 103 Image processing device 104 Image display device 105 Timing signal generation circuit 106 Control circuit

Claims (4)

[Claims] 1. A read address pointer which sequentially holds a plurality of input pixel data and sequentially changes according to a data read control signal, and satisfies a predetermined relationship with an address corresponding to the read address pointer. First data holding means for simultaneously outputting pixel data held at a plurality of addresses; and selecting pixel data from a plurality of pixel data output from the first data holding means in accordance with a selection signal. Selecting means, performing a predetermined interpolation operation using the pixel data selected by the selection means, outputting an operation result, and sequentially performing addition using a previous addition result and a constant, Constant addition means for generating the data read control signal and the selection signal depending on whether a carry has occurred in the addition result. Image processing device. 2. A second data holding means for holding a plurality of input pixel data, and a predetermined interpolation operation using the pixel data output from the second data holding means, A sub-scanning interpolation operation means for outputting, and a pixel data of an image whose resolution has been converted in the sub-scanning direction by performing a predetermined interpolation operation so as to be sequentially output from the sub-scanning interpolation operation means in the main scanning direction. Means for controlling the pixel data necessary for the image data to be sequentially output from the second data holding means, and inputting the data output from the sub-scanning interpolation means to the first data holding means. The image processing apparatus according to claim 1, wherein: 3. An interpolation coefficient generating means for performing a linear interpolation operation, wherein an interpolation coefficient of a linear interpolation operation performed by the interpolation operation means is performed using an addition result of the constant adding circuit. The image processing apparatus according to claim 1, further comprising: 4. An image processing apparatus for performing predetermined processing on an externally input image signal, an image display apparatus for forming and displaying an image from an image signal transmitted through the image processing apparatus, and the display apparatus And a control circuit that controls to operate smoothly, a display device comprising:
A display device, wherein the image processing device is the image processing device according to any one of claims 1 to 3.