JP2000268007A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To guarantee the consistency of cache data based on a directory system in simple configuration without lowering the performance of a multiprocessor system concerning the system in which plural processors and a shared memory are mutually coupled and the respective processors locally have cache memories. SOLUTION: Plural cache memories 2 broadcast memory access requests, which are transmitted by the respective cache memories, for accessing a shared memory 5 also to a directory memory 6 together with the shared memory 5 through an optical transmission medium 4 and the directory memory 6 broadcasts the internal states of all the plural cache memories 2 recorded in that directory memory 6 to these plural cache memories.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared memory type multiprocessor system connected by an interconnection network, and more particularly to a multiprocessor system capable of simultaneously transmitting a plurality of data.

[0002]

2. Description of the Related Art Recent advances in processor technology have
While the processing speed inside the processor has been dramatically improved, the improvement in the operating speed of the memory and bus is lower than the improvement in the performance of the processor, and the data transfer speed between the processor and the memory has reduced the performance of the entire computer system. It is starting to affect. In addition, with the recent demand for higher speed and more multifunctional computer systems, it is essential to use a multiprocessor configuration as the system configuration. In a multiprocessor system, processes are executed in parallel while communicating data between processors. The method of using a shared memory referred to by all processors for data communication is often used because the system configuration is relatively simple. The multiprocessor system using the shared memory is described in detail in, for example, the document “Parallel Computer” (Hideharu Amano, Shokodo, 1996). In this method, a plurality of processors, a shared memory, and other I / O devices are connected to a shared bus. A plurality of processors and I / O devices perform parallel processing while appropriately reading and writing data on the shared memory. With such a shared bus configuration,
The processing capacity of the system is influenced by the transfer bandwidth of the bus, the frequency of bus traffic occurring in the system, or the access latency of the memory.

As one method for solving the bottleneck of the memory access, a high-speed local cache is added to each processor, and as much memory access as possible is processed locally between the processor and the cache memory.
Methods to reduce the use of shared buses are widely used. By doing so, the probability of having to access a shared memory having a long access time is greatly reduced, and the average latency time of memory access can be improved.

When using such a cache memory, it is necessary to consider maintaining data consistency. That is, when a plurality of cache memories corresponding to a plurality of processors hold data in the same area in the shared memory, when one processor updates data in this area in the shared memory, a cache of another processor is updated. This means that it is necessary to invalidate the pre-update data of this area held by the memory. In order to invalidate the data held in the cache memory of the other processor, the other processor holding the data of the shared memory to be updated may be instructed to invalidate the data. Invalidating the data in the cache memory in this way is called invalidation processing. To perform the invalidation process, it is necessary to know which processor's cache holds the data in the shared memory to be updated, and there are a snoop method and a directory method for obtaining this information.

[0005] The snoop method is a method used in a system in which a plurality of processors and a shared memory are connected to a single bus. Each cache monitors memory access information flowing on the bus, and as necessary, This is to invalidate the cache. On the other hand, the directory system shown in FIG. 7 is used when the number of connected processors is large, or in an interconnection network connected by a plurality of buses or a plurality of switches.

FIG. 7 includes a plurality of processors 1, a cache memory 2 corresponding to each of the plurality of processors 1, and a shared memory 5. The cache memory 2 and the shared memory 5 are connected to a bus 26. 1 shows a multiprocessor system. Here, the directory method is a method in which, for example, a directory memory area 5 is allocated to a part of the shared memory 5 and information on which data is held in which cache is recorded therein.

The invalidation processing in the directory method is as follows.
The procedure is outlined below. That is, a processor that attempts to update certain data specifies a processor that holds the relevant data in the cache, and then issues a request to invalidate the specified data in the cache to the specified processor. Sent together with data address. This series of processing is caused by interrupting the write operation of the processor, and results in increasing the idle time of the processor. Also, the signal flowing for the invalidation process increases the traffic on the bus or interconnection network connecting the processor and the shared memory, and lowers the performance of the entire system. In order to solve this problem, for example, a "data processing device" disclosed in Japanese Patent Application Laid-Open No. 7-319769 has been proposed. According to the present invention, an invalidation request to be sent to each processor is notified to all processors, and each of the processors receiving the request performs invalidation processing by judging from the address information. Then, the invalidation receiving signal is returned through a signal line different from the common bus. However, according to the present invention, there is a drawback that a processing time for referring to directory information every time reading or writing is required, and mounting another signal line increases a mounting cost.

On the other hand, an "information processing system and method" disclosed in JP-A-8-83227 has been proposed as an example in which coupling between processors is performed by optical transmission. In the present invention, simultaneous multiplex communication is performed between the processors using light of a plurality of wavelengths, and the cache management information is sent using an arbitration signal path for arbitration of connection path use. In the present invention, cache management is realized by a system having a plurality of connection paths.However, in order to send information using an arbitration signal path, is it necessary to prepare another connection path such as an optical fiber? However, wavelength multiplexing must be performed in the same fiber, which causes a problem that the system becomes complicated.

[0009]

However, a problem to be solved by the present invention is to provide a directory system in a multiprocessor system in which a plurality of processors and a shared memory are mutually connected and each processor has a cache memory locally. It is to guarantee the consistency of cache data by a simple configuration without deteriorating the performance of the system.

[0010]

According to the present invention, there is provided a multiprocessor system comprising: a plurality of processors; a cache memory provided for each of the plurality of processors and connected to the corresponding processor; An optical interconnection network in which the plurality of cache memories are connected, and a shared memory for communicating with the plurality of cache memories via the optical interconnection network;
A cache memory management unit that records the internal state of all of the plurality of cache memories and communicates with the plurality of cache memories via the optical interconnection network; A memory access request transmitted by the memory for accessing the shared memory is also broadcast to the cache memory management unit together with the shared memory via an optical interconnection network, and the cache memory management unit includes the cache memory management unit. , And broadcasts the internal state of all of the plurality of cache memories recorded to the plurality of cache memories to the plurality of cache memories.

Here, in the multiprocessor system according to the present invention, the optical interconnection network includes a light diffusing unit for diffusing and propagating light incident from the light incident unit on a light incident unit to which an optical signal is incident. Preferably, the optical interconnection network is capable of transmitting a plurality of types of optical signals simultaneously.

Further, in the multiprocessor system according to the present invention, the cache memory management unit transmits the optical signal transmitted from the cache memory management unit via the optical interconnection network from the plurality of cache memories. It is preferable that a type of optical signal different from the type of the optical signal transmitted and transmitted via the optical interconnection network is assigned.

[0013]

Embodiments of the present invention will be described below.

FIG. 1 is a schematic configuration diagram of an embodiment of a multiprocessor system according to the present invention. In this figure, a plurality of processors 1 each have a cache memory 2 which can copy and store a part of data in a shared memory 5. The shared memory 5 and the processor 1 are connected through the optical transmission medium 4, and the processor obtains data that does not exist on the cache through the optical transmission medium. An electric signal output from the processor or the shared memory is converted into an optical signal through an interface 3 including an optical-electrical converter and an electrical-optical converter, and is incident on an optical transmission medium.

A more detailed view of interface 3 is shown in FIG.
It was shown to. The electric signal sent to the optical transmission medium is shifted in signal level by the level shifter 13 constituting the electric-optical conversion unit 22, and is converted into an optical signal by driving the laser diode 15 by the laser diode driver 14. Conversely, the optical signal emitted from the optical transmission medium 4 is transmitted to the photodiode 1
9, the light is amplified by the amplifier 18, and the level shifter 1
The signal is converted into a predetermined electric signal by shifting the level at 7.

Returning to FIG. 1, the description will be continued.

The interface 3 shown in FIG. 6 includes a light diffusion unit (specifically, described later with reference to FIG. 6).
The diffusing section 16 has an effect of expanding the traveling direction of the optical signal converted from the electric signal before the optical signal is incident on the optical transmission medium to diffuse the optical signal widely. In this application,
For example, a diffusion sheet used for a liquid crystal or the like can be used. The optical signal that has passed through the light diffusion unit propagates while spreading in the optical transmission medium, is received at many positions facing each other, and is converted into an electric signal. Therefore, if the optical transmission medium is spread over a surface, for example, in a sheet shape, it becomes possible to broadcast an optical signal from one end face to the other end. Therefore, if the connection port of the shared memory and the connection port of the directory memory are arranged on the surface where the optical signal reaches, the memory access signal from the processor reaches both ports almost simultaneously. According to this method, the configuration is simpler than that of connecting all the ports using an optical fiber or the like, and the system can be easily changed.

The optical signal that has propagated in the optical transmission medium 4 is converted into an electric signal again by the interface 3 in the emitting section, and sent to a memory or a processor connected to the interface. At this time, the optical signal sent from the processor 1 is
At the same time, it is sent to the emission unit connected to the shared memory 5 and also to the emission unit connected to the directory memory 6 that records information of data stored in the cache connected to the plurality of processors. Sent.
Here, the optical transmission medium 4 has a function of connecting between a plurality of ports on the processor side and a plurality of ports on the shared memory and directory memory sides facing each other in FIG.
For example, it can be realized by connecting each port with an optical fiber or the like. Here, the optical transmission medium is shown as a rectangle for the sake of convenience. However, the optical transmission medium is not limited to this shape, but may be any shape as long as the above function is satisfied.

Next, the function of the multiprocessor system shown in FIG. 1 will be described. The present invention is a system that guarantees data consistency among a plurality of caches in a directory system. When performing read access to the shared memory, each processor first gives priority to reading from its own cache memory. The cache memory includes a cache controller 7, a memory table 8, and a memory cell 9 as shown in FIG.
Determines whether valid data at the requested address exists in the cache memory. If a valid memory exists, the cache controller 7 reads data from the memory cell 9 with reference to the memory table 8, and
Send to processor. Here, the cache memory 2 is often configured by an SRAM (static random access memory) capable of high-speed reading. On the other hand, when there is no valid data in the cache memory, the shared memory 5 is accessed through the optical transmission medium 4 (see FIG. 1). Generally, the shared memory 5 can easily be increased in capacity, but the SRAM
In many cases, a DRAM (Dynamic Random Access Memory), which requires a long time to read data, is used. At this time, the processor sends a read control signal and an address of data on the shared memory to be read. The control signal and the address are stored in the directory memory 6.
Also reach the port. The directory memory 6 stores information on which address data in the shared memory 5 is stored in which cache and the state of the data. Here, the data state means whether the data stored in the cache is clean (has the same value as the shared memory), dirty (has a different value from the shared memory), or shared (has been shared by a plurality of caches). ) Or exclusive (not shared elsewhere). Although this directory memory is often realized by using a part of the shared memory, in the present embodiment, it is provided as a separate module as shown in FIG. 1, and as shown in FIG. 4 is connected. In addition to updating the directory information in the memory cell 11, the directory controller 10 may transmit a cache invalidation request to the processor as needed. The directory memory according to the present embodiment is characterized in that the original memory access and the update of the directory information can be simultaneously performed by receiving a signal from the processor and the shared memory at the same time. In particular, in the case of the write-through method, which is one of the cache control methods, read access does not make invalidation requests or write-back requests to other caches. Therefore, according to the present embodiment, overhead for updating directory information is eliminated, which leads to improvement in system performance.

Next, a case where each processor performs write access to the shared memory will be described. When a certain processor 1 attempts to update data in the shared memory, the control signal of the write request and the address of the data are usually transmitted to the shared memory 5 first. Then the actual data is sent,
The data in the shared memory 5 is updated. The control signal and the address of the write request are also sent to the directory memory 6 to update the cache state for the address to be updated. If another processor has stored data at the same address in its own cache, it issues an invalidation request to that processor.
By transmitting the invalidation information during the write waiting time of the DRAM, useless idle time can be reduced.

FIG. 5 is a schematic diagram of a multiprocessor system according to an embodiment of the present invention. In this figure, a plurality of processors 1 have a cache memory 2 which can copy and store a part of data in a shared memory 5. The shared memory 5 and the processor 1 are connected to the optical transmission medium 4
, And the processor obtains data not existing in the cache through the optical transmission medium 4. An electric signal output from the processor or the shared memory is converted into an optical signal through an interface 3 including an optical-electrical converter and an electrical-optical converter, and is incident on an optical transmission medium.
The optical signal that has propagated in the optical transmission medium is converted into an electric signal again at the interface of the emission unit, and sent to a memory or a processor connected to the electric signal. At this time,
The optical signal sent from the processor is sent to the emission unit to which the shared memory 5 is connected, and the directory memory 6 that records information of data stored in the cache connected to the plurality of processors is connected. It is also sent to the emitting section that is being used. Here, the optical transmission medium is
In the figure, it has a function of connecting a plurality of ports on the processor side and a plurality of ports on the side of the shared memory and the directory memory, which can be realized, for example, by connecting each port with an optical fiber or the like. In this case, the optical transmission medium is shown as a rectangle for the sake of convenience. However, the optical transmission medium is not limited to this shape, and any shape may be used as long as the above function is satisfied.

In this embodiment, it is possible to broadcast directory information to each processor from a port to which a directory memory is connected. In this case, because the light propagates in different directions due to the non-coherence of the light, the directory information can be notified to the processor simultaneously with the signal transmission from the processor to the shared memory.

That is, the effect of this embodiment is that the parallel operation of a plurality of processors can be realized in a pipeline. Reference of directory information required before the processor performs read or write operation,
This can be performed in advance by obtaining information sent from the directory memory. In addition, cache invalidation processing of a processor, which is performed to maintain cache coherency, can be performed during a waiting time for write processing to a shared memory of another processor. As described above, by performing the memory access processing of a plurality of processors in parallel, an efficient operation can be performed.

Next, an embodiment in which multiplex transmission is performed with a plurality of types of light in an optical transmission medium will be described with reference to FIG.
As the plurality of lights, for example, lights having different wavelengths, lights having different polarizations, lights having different intensities, and the like can be used. Here, the use of light having different intensities is considered. To select an optical signal to be used for transmission from a plurality of paths, an arbiter (arbiter) not shown is provided. The processor issuing the access request will so indicate to the arbiter and be instructed of the appropriate optical signal strength level. Then, the optical signal level controller 26 in FIG. 6 controls the level shifter 13 to adjust a signal input to the laser diode 15 so as to match the intensity level. When multiple lights overlap, their intensities are simply added. Here, it is assumed that, for example, two types of optical signals are transmitted simultaneously. Assuming that the light emitted from the processor A has an intensity of 1 when in the “High” state and the light emitted from the processor B has an intensity of 2 when in the “High” state, the total intensity in the receiving unit is 0, 1, 2 , Or 3. When the processor A is “High”, the intensity at the receiving unit is either 1 or 3, and when it is “Low”, it is either 0 or 2. Processor B is 'Hi'
When it is "gh", the intensity at the receiving unit is either 2 or 3, and when it is "Low", it is either 0 or 1. Therefore, it is possible to restore what signal each processor has output from the received intensity. Multiplex transmission becomes possible by restoring it by the comparator 25 based on the information of the arbiter on the receiving side. Generally n
In the case of intensity multiplexing, the intensity ratio of each optical signal is set to 1:
If m: m ² :...: m ⁿ⁻¹ , each can be separated in the receiving unit. When multiplex transmission is performed by changing the wavelength or polarization of light, only a desired signal can be extracted by inserting an appropriate filter 24 in front of the photodiode 19 at the incident portion.

Here, in the configuration shown in FIG. 1 or FIG. 5, the wavelength of the optical signal emitted from the directory memory may be different from that used in the communication between the processor and the memory. In this way, the directory information can always be notified to the processor. That is, even when an optical signal is sent from the memory to the processor in response to a data read request from the processor, the signal type and
By changing the signal type sent from the directory memory, the processor can selectively receive a desired signal. With such a configuration, the idle time of the processor can be further reduced, and the performance of the system can be improved.

[0026]

As described above, according to the present invention,
In order to maintain cache coherency, it is possible to refer to the directory memory in which the cache management information is recorded in parallel with the memory access of the processor, which leads to an improvement in system performance.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of a multiprocessor system of the present invention.

FIG. 2 is a diagram showing an interface unit in the embodiment of FIG.

FIG. 3 is a diagram showing details of a cache memory in the embodiment of FIG. 1;

FIG. 4 is a diagram showing details of a directory memory in the embodiment of FIG. 1;

FIG. 5 is a schematic configuration diagram of an embodiment of a multiprocessor system of the present invention.

FIG. 6 is a diagram illustrating another example of the interface unit.

FIG. 7 is a diagram showing a conventional multiprocessor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processor 2 Cache memory 3 Interface 4 Optical transmission medium 5 Shared memory 6 Directory memory 7 Cache controller 8 Memory controller 9 Memory cell 10 Directory controller 11 Memory cell 13 Level shifter 14 Laser diode driver 15 Laser diode 16 Light diffusion unit 17 Level shifter 18 Amplifier 19 Photodiode 20 Incident light 21 Outgoing light 22 Electric-optical converter 23 Optical-electric converter 24 Filter 25 Comparator 26 Optical signal level controller 26 Electric bus

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 13/38 330 G06F 13/38 330A 15/167 15/167 A 15/173 15/173 A (72) Inventor Keishi Fujimagari 430 Nakai-cho, Ashigami-gun, Kanagawa Prefecture Green Tech Naka Fuji Xerox Co., Ltd. F-term (reference)

Claims (4)

[Claims] 1. A plurality of processors, a cache memory provided corresponding to each of the plurality of processors and connected to the corresponding processor, an optical interconnection network formed by connecting the plurality of cache memories, A shared memory for communicating with the plurality of cache memories via the optical interconnection network; and a cache memory for recording an internal state of all of the plurality of cache memories. A cache memory management unit for communicating with the shared memory, wherein the plurality of cache memories transmit a memory access request for accessing the shared memory, which is issued by each cache memory, via the optical interconnection network. And also broadcasts to the cache memory management unit, Yasshumemori management unit, multiprocessor systems, characterized in that to broadcast towards said plurality of cache memories all internal state stored in the cache memory management unit to the plurality of cache memory. 2. The optical interconnection network according to claim 1, wherein a light incident portion on which an optical signal is incident is provided with a light diffusing portion for diffusing and propagating light incident from the light incident portion. Item 2. The multiprocessor system according to Item 1. 3. The multiprocessor system according to claim 1, wherein said optical interconnection network is capable of simultaneously transmitting a plurality of types of optical signals. 4. The cache memory management unit transmits the optical interconnection network transmitted from the plurality of cache memories as an optical signal transmitted from the cache memory management unit and transmitted via the optical interconnection network. 4. The multiprocessor system according to claim 3, wherein a type of optical signal different from the type of the optical signal transmitted through the intermediary is allocated.