JP2000259499A - Method for mapping distributing type cache memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve system efficiency by setting the uppermost and lowermost parts of a system memory where an operating system most frequently accesses to cache possible ranges. SOLUTION: This mapping method selects a set of bits in an address bit string and uses it to correspond to a tag mapping table. The possible combinations of the values of selected specific bits make a system memory where the corresponding tag mapping table are mapped a cache possible area or a cache impossible area according to user definition. And the uppermost and lowermost layer parts of the system memory where access is frequency performed are simultaneously defined as cache possible parts. These areas can be defined as a cache possible area or a cache impossible area in accordance with user's needs. For this reason, the cache possible areas of the memory is not continuous distributions but necessary scattered distribution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reading a memory, and more particularly to a mapping method for a cache memory.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram of a conventional cache memory device. The cache memory device 110 mainly includes a cache memory 111 and a cache control circuit 11.
2. The cache control circuit 112 controls the cache memory 111 and performs the operation of the entire cache memory device 110. Cache memory 11
1 further includes a data memory 113 and a tag memory (tag RA).
M) 114). Data memory (data RAM) 11
3 stores data corresponding to the system memory 140, and the tag memory 114 stores address data corresponding to the system memory 140. In addition, the bit is set to a dirty bit and the data memory 1
13 is updated.

FIG. 2A shows the correspondence between a cache memory and a system memory. Since only a part of the system memory data can be stored in the cache memory, the data corresponding to the system memory is actually stored in the data memory, and the bit string corresponding to a part of the address in the system memory of the data stored in the data memory In the tag memory. Therefore, the combination of the index address of the data memory and the bit string in the tag memory is
As shown in FIG. 2B, it is equal to the actual address of the system memory. As for the address of each data in the system memory, all the cache memories have a location and data address correspondence, and this kind of cache memory structure is a direct mapping. Maps to a location.

In the cache memory, data of only a part of the system memory can be stored.
During operation, it mainly reads and writes to the cache memory. Therefore, when processing a read / write data request from the CPU, the cache device must determine whether the cache memory has been hit or whether new data in the system memory should be sent to the memory. In the hit determination method, when a read request or a write request sent by the CPU is received, the address sent from the CPU is compared with the contents of the tag memory, and if they are the same, a hit is determined. The cache memory is set to be cacheable (cachable) by a tag mapping method. This is the hit mentioned above. Since the general tag bit has a limit and is generally only 8 bits or 7 bits, the memory is divided into a cacheable part and a non-cachable part due to the influence of the tag bit. .

If the size of the system memory is 256
M, for example, when the cache memory has an 8-bit tag at 512K, it is mapped (mappin
g) The maximum possible cacheable range is limited by the tag bit size. It 2 ⁸ times 512K As shown in FIG. 3, i.e., 128M. The conventional method of mapping a cache memory is to make the range of cacheable memory contiguous, as shown in the first part 200a of the 256M system memory in FIG.
Memory in the range of 8M to 256M is set by a cacheable controller to the range of non-cachable memory. As can be seen from the above description, the conventional cache memory tag mapping scheme simply divides the memory into two parts, one part of the lower cacheable memory 200.
a, another part of which is upper non-cacheable memory 20
0b. Operating system
The system (OS) generally uses the upper memory to create a stack or status keeping, for example, to start stacking downward from a 256M address or starting upward from a 0M address. . With the conventional tag mapping method of the cacheable range, only the lower part 200a of the memory, 0 to 128M, could be set to the cacheable range, so that the efficiency of the operating system was very poor. Therefore, the uppermost layer 200b and the lowermost layer 200 of the system memory
How to make a into the cacheable range is a problem of the cache memory.

[0006]

To summarize the above, the conventional cache memory tag mapping method can map only one continuous cacheable memory area, that is, the lower layer of the system memory. The system was inefficient because the top-level memory that was frequently accessed could not be made available in cache memory.

It is an object of the present invention to provide a method of mapping a distributed cache memory so that the top and bottom layers of the system memory are cacheable memories. A further object of the present invention is to provide a distributed cache memory mapping method, which eliminates the need to limit to a contiguous memory area to meet the need to distribute the cacheable range of system memory. It is a further object of the present invention to provide a method of mapping distributed cache memory to increase the system efficiency by setting a portion of the system memory most frequently accessed by the operating system to a cacheable range.

[0008]

SUMMARY OF THE INVENTION To achieve the above and other objects, the present invention provides a method for mapping a distributed cache memory, briefly described as follows. In the distributed cache memory mapping method described in this specification, a set of address bits is selected from an address bit string and used for correspondence with a tag mapping table. The possible combinations of the selected specific address bit values make the system memory mapped by the corresponding tag mapping table a cacheable area or a non-cacheable area according to the definition of the user. Because the tag mapping table makes the mapped system memory a cacheable area or a non-cacheable area, the user defines it by adding specific address bits. Can be defined in the cache part. Alternatively, in accordance with a user's request, those areas are set to a cacheable range or a non-cacheable range, and the cacheable range of the memory is not a continuous distribution but a scatter distribution according to need.

According to the mapping method proposed by the present invention, the user increases the efficiency of the system by setting the uppermost area and the lowermost area of the system memory frequently accessed by the operating system to the cacheable range. In order to make the above objects, features and advantages of the present invention more apparent, a better embodiment is described below and is described in detail with reference to the drawings.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The distributed cache memory mapping method of the present invention increases the efficiency of system access memory by making memory areas frequently accessed by the system cacheable. In a bit string indicating an address (address bit string), a set of bits at a relatively higher bit position is selected and a tag mapping table (tag ma) is selected.
pping table). The user selects and selects a possible combination of bit values to make the system memory mapped by the corresponding tag mapping table a cacheable area or a non-cacheable area. The tag mapping table maps the system memory into a cacheable area or a non-cacheable area, and the bit is defined by the user. Therefore, the uppermost layer and the lowermost layer of the system memory can be simultaneously made cacheable. Alternatively, depending on the needs of the user, those areas are set as a cacheable range or a non-cacheable range, and the cacheable range of the memory is not a continuous distribution but a scatter distribution.

FIG. 4 shows a mapping method of a distributed cache memory according to the present invention, showing a correspondence between a tag mapping table and a memory, and explaining an operation method and its function of the present invention. A set of bits in a relatively high order bit position in the address bit string is used as an address corresponding to a tag bit, and this bit is subjected to an encoding method. When the encoded bits match the tag bits, the memory becomes a cacheable part, thereby making the cacheable range of the memory a distributed type, not a conventional continuous distribution type.

According to an example, the bits A [22:20] in the address bit string are set to bits corresponding to the tag, and a tag mapping table by a combination of three bits determines a corresponding cacheable memory portion. Here, the memory capacity is assumed to be 8M. When the cache memory size is 512K and the tag is a three-digit number, the size of the cacheable memory mapped by the tag is 5
2 ³ times the 12K, that is, the size of 4M. This means that 4M in 8M memory is cacheable.

The total address bits of A [22:20] are eight different combinations, for example, in the order from (000) to (111) shown in FIG. .. Corresponds to eight memory areas such as 7M, 7M to 6M,..., 2M to 1M, and 1M to 0M. In this embodiment, the memory is divided into eight equal parts.

[0014] The operating system generally uses the upper memory to create a stack or state maintenance. Therefore, since the memory in that area is frequently accessed, the uppermost layer and the lowermost layer are set in advance as a cacheable range. 8M-7M and 1M- of FIG.
The size of the two parts of 0M is 2M. The remaining 2M range can be set to suit your needs. Finally, as shown in the figure, the cacheable range in the memory exhibits a distributed distribution, and caches the uppermost layer and the lowermost layer (for example, two portions of 8M to 7M and 1M to 0M) where system access is most frequent. Set as possible. In this way, the efficiency of the system access memory is greatly increased.

FIG. 5 shows that in the situation where A [22:20] is (011), the tag code is set to (01) via the encoding method. FIG. 4 is a correspondence diagram in which a corresponding memory range is 5M to 4M. Thus, when the cache memory has 512K and has an 8-bit tag, the size of the cacheable memory is 128M. According to the above method, with the 8M as a unit, the selected address and encoding method distributes the tag bits toward the memory cacheable range and caches the range frequently used by the range system, such as the upper and lower layers of the memory. Increase system efficiency with available memory.

[0016]

Therefore, a feature of the present invention is that a specific bit in an address bit string is set to a bit corresponding to a tag bit, and when this specific bit matches the tag bit through an encoding method, the memory is stored in a cacheable portion. By changing the range, the cacheable range of the memory is set to a distributed type, which is different from the conventional continuous distribution. Another feature of the present invention is that the uppermost and lowermost parts of the system memory are cacheable. This greatly increases the efficiency of system access memory, as this is the most frequently accessed part of the operating system. A further feature of the present invention is that it is not limited to the conventional continuous distribution type because the cacheable range of the system memory can be freely set.

Although the present invention has been disclosed by preferred embodiments, it is not intended to limit the present invention.
As will be apparent to those skilled in this technology,
Since appropriate changes and modifications can naturally be made within the scope of the technical concept of the present invention, the scope of patent protection must be determined based on the claims and equivalent areas.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional cache memory device.

FIG. 2A is a diagram illustrating a correspondence state between a cache memory and a system memory, and FIG. 2B is a diagram illustrating a method of setting an address of the cache memory.

FIG. 3 is a diagram showing a cacheable range and a non-cacheable range of a conventional system memory.

FIG. 4 is a diagram showing a correspondence between a tag mapping table and a memory according to the present invention.

FIG. 5 is a diagram of the address corresponding embodiment of FIG. 4;

[Explanation of symbols]

110 cache memory device
evice) 111 cache memory (cache memory) 112 cache control circuit (cache memory contr)
ol circuit) 113 data memory (data RAM) 114 tag memory (tag RAM) 120 central processing unit (central processing uni)
t) 140 system memory 150 bus 200a memory in cacheable range 200b memory in non-cacheable range

Claims (4)

[Claims] 1. A method of setting a cacheable range of a memory, comprising: converting a plurality of relatively high-order address bits in an address bit string into bits corresponding to tag bits; encoding the bits by an encoding method; When the encoded bit and the tag bit match, the memory is a cacheable portion, and the uppermost and lowermost layer ranges of the memory corresponding to these bits are set to the cacheable range in advance. How to map cache memory. 2. A method of setting a cacheable range of a memory, comprising: converting a plurality of relatively high-order address bits in an address bit string into bits corresponding to tag bits; encoding the bits by an encoding method; A method for mapping a distributed cache memory, wherein when the encoded bit and the tag bit match, the memory is a cacheable part. 3. The mapping method for a distributed cache memory according to claim 2, wherein the coincidence between the encoded bit and the tag bit is set by the system. 4. The method according to claim 2, wherein a range in which bits corresponding to the memory are most frequently used by the system is set in advance as a cacheable range.