JP2000252463A - Semiconductor device with horizontal mos element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a horizontal MOS element, in which an element can be made minute, along with a high breakdown strength. SOLUTION: A semiconductor device 100 with a horizontal MOS element includes a silicon substrate 10, an n-type drift region 14, a p-type second semiconductor layer 16 formed as a body region in the drift region 14 and having a channel region in the body region, n-type third semiconductor layers 18a and 18b as a source region selectively formed in the second semiconductor layer, an n-type fourth semiconductor layer 22 as a drain region formed on the drift region 14, and a buried insulating layer 30 between the second semiconductor layer 16 and the fourth semiconductor layer 22. In addition, in the second semiconductor layer, a parasitic MOS channel region is formed along a buried insulating layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique suitable for a semiconductor device including a lateral MOS element, particularly a semiconductor device including a lateral power MOSFET which can be miniaturized and has a high breakdown voltage.

[0002]

2. Description of the Related Art Since power devices are intended for high voltages and large currents, it is important to protect elements from destruction such as avalanche destruction caused by back electromotive force when driving an inductance load. It has become a challenge. For this reason, many proposals have been made to realize a high breakdown strength of the element. These proposals can be roughly classified into: first, improvement of the breakdown resistance of the element itself, and second, addition of a protection element such as a Zener diode to avoid destruction of the element.

The former proposal is disclosed in, for example,
As disclosed in Japanese Unexamined Patent Publication No. 868, a technique for increasing the impurity concentration in a region corresponding to the base of a parasitic bipolar transistor and reducing the current amplification factor h _FE of the parasitic bipolar transistor to realize a high breakdown strength. There is.
However, in this technique, since the impurity concentration in the region corresponding to the base of the parasitic bipolar transistor is increased, the threshold value of the MOS element is increased, and the on-resistance is increased.

The latter proposal is disclosed in, for example,
As disclosed in JP 177476, the power M
A technology that inserts a Zener diode between the gate and drain of an OS element and applies a high voltage higher than the withstand voltage of the Zener diode to the drain, turns on the gate, turns on the transistor, and protects the element from overvoltage. There is. However, in this technique, since the Zener diode is formed inside the element, a space for forming the Zener diode is required, so that the effective active area is reduced,
This is a factor that hinders miniaturization of the element.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device including a lateral MOS element which can be miniaturized and has a high breakdown voltage.

[0006]

According to the present invention, there is provided a semiconductor device including a lateral MOS device, a substrate made of a semiconductor or an insulator, a first semiconductor of a first conductivity type formed on the substrate and constituting a drift region. A second conductive type second semiconductor layer formed in contact with the first semiconductor layer to form a body region and having a channel region formed in the body region; and selectively formed on the second semiconductor layer. A third semiconductor layer of a first conductivity type forming a source region in contact with the channel region; and a third semiconductor layer formed between the second semiconductor layer and the first semiconductor layer to form a drain region. A fourth semiconductor layer of one conductivity type, an insulating gate formed in contact with at least the channel region, and a buried insulating layer formed between the second semiconductor layer and the fourth semiconductor layer;
The buried insulating layer is formed at a depth such that its lower end reaches at least the bottom of the second semiconductor layer, and a channel region of a parasitic MOS element is formed along the buried insulating layer in the second semiconductor layer.

According to this semiconductor device, when the MOS element is in the off state, the parasitic MOS transistor is operated, thereby avoiding breakdown of the element due to a high voltage such as a surge voltage at the time of off state, and preventing element destruction. Can be.

According to the present invention, there is provided a semiconductor device including a lateral MOS element, comprising: a substrate made of a semiconductor or an insulator; a first semiconductor layer of a first conductivity type formed on the substrate to form a base region; A second semiconductor layer of a second conductivity type, which is formed in contact with the layer, forms a base region, and a channel region is formed in the base region, and is selectively formed on the second semiconductor layer; A third semiconductor layer of a first conductivity type that is in contact with and forms an emitter region; a fourth semiconductor of a second conductivity type that is formed between the first semiconductor layer and the second semiconductor layer to form a collector region; A buried insulating layer formed between the second semiconductor layer and the fourth semiconductor layer, and a lower end of the buried insulating layer has at least a lower end. Previous Is formed with a depth to reach the bottom of the second semiconductor layer, and the channel region of the parasitic MOS devices along 該埋 included insulating layers in said second semiconductor layer is formed.

This semiconductor device is a bipolar transistor (insulated gate bipolar silane transistor: IGBT) including a MOS element. In this semiconductor device, similarly to the semiconductor device described above, when the MOS element is in the off state, the parasitic MOS transistor is operated to avoid breakdown of the element due to a high voltage such as a surge voltage at the time of off, thereby preventing element destruction. Can be prevented.

In the semiconductor device, a threshold voltage of a parasitic MOS element including at least the buried insulating layer, the second semiconductor layer, and the third semiconductor layer is higher than a power supply voltage, It is desirable to set the voltage to be smaller than the source-drain breakdown voltage of the MOS element.

By setting the threshold voltage of the parasitic MOS transistor in this way, a high voltage can be absorbed without causing a problem in the operation of the MOS element. That is,
When the potential of the drain region or the collector region (the fourth semiconductor layer) reaches the threshold voltage of the parasitic MOS transistor in the off state, the parasitic MOS transistor is turned on, and the body region or the base region (the fourth region) close to the buried insulating layer. A channel is formed in the two semiconductor layers), and a current flows. As a result, when the semiconductor device is in the off state, the element does not break down even when a high voltage such as a surge voltage is applied.

Further, the semiconductor device of the present invention has a structure in which a buried insulating layer is buried inside the element, so that it is not necessary to sacrifice the chip area as compared with the conventional method of providing a protection element. Can be achieved.

[0013] The insulated gate includes a trench formed through the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer, a gate insulating layer formed along a surface of the trench, and It is desirable to have a gate electrode formed inside the trench via a gate insulating layer. In the semiconductor device of the present invention, the insulated gate structure is not particularly limited. However, by using this as the trench gate structure having the above structure, further miniaturization of the element can be achieved.

The present invention also relates to SOI (Silicon).
The present invention can also be applied to a semiconductor device using a substrate having an On Insulator structure.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 and FIG.
A lateral power MOSFET having a trench gate structure to which the present invention is applied (hereinafter referred to as “MOSFET”)
100 is a plan view and a cross-sectional view schematically showing 100. FIG.
1 shows a cross-sectional view of a portion along the line AA in FIG. FIG. 1 omits an electrode layer and an insulating layer formed on the surface of the semiconductor layer.

The MOSFET 100 shown in FIGS. 1 and 2
Has a p-type silicon substrate 10 and a drift region (first semiconductor layer) 14 formed on the silicon substrate 10 and containing an n-type impurity.

On the upper surface of the drift region 14, p
The p-type body region (the second
A semiconductor layer 16 is formed.
6, a first source region (third semiconductor layer) 18a and a second source region (third semiconductor layer) 18b are formed by selectively diffusing high-concentration n-type impurities. These body region 16 and source region 18
a and 18b are formed by double diffusion by a self-alignment technique.

Further, on the upper surface of the drift region 14, a drain region (fourth semiconductor layer) is spaced apart from the body region 16.
22 are formed. This drain region 22 contains a high concentration of n-type impurities.

Between the body region 16 and the drain region 22, a buried insulating layer 30 made of silicon oxide, silicon nitride, or the like, extending in the thickness direction of the silicon substrate 10, is formed. The depth of the buried insulating layer 30 is set such that its lower end is formed deeper than the bottom of the body region 16 and has a predetermined distance from the silicon substrate 10.

A trench gate is formed so as to be in contact with body region 16. That is, the trench 74
Is formed so as to penetrate the first source region 18a, the body region 16 and the drift region 14 and reach the inside of the silicon substrate 10. A gate insulating layer 72 is formed on the surface of trench 74. Then, a gate electrode 70 is formed inside the gate insulating layer 72. By forming the trench 74 to the inside of the silicon substrate 10 and forming the bottom corner portion of the gate insulating layer 72 in the silicon substrate 10 in this manner, the withstand voltage can be further increased as compared with the case where the trench 74 is not provided. it can.

A source electrode 44 is formed on the surface of the first source region 18a, the exposed body region 16 and the second source region 18b, and a drain electrode 46 is formed on the surface of the drain region 22. . The source electrode 44 and the drain electrode 46 are connected to each other by the insulating layer 5.
6 are electrically separated. In MOSFET 100 according to the present embodiment, buried insulating layer 30 is a gate insulating layer, body region 16 is a channel region, and drift region 14 on the opposite side of body region 16 via buried insulating layer 30 is a gate electrode. , A parasitic MOS transistor having the second source region 18b as a source is formed. And this parasitic MOS transistor
The threshold voltage is set to be higher than the power supply voltage and lower than the source-drain breakdown voltage (device breakdown voltage).

The threshold value of the parasitic MOS transistor can be set according to the impurity concentration of body region 16 and the thickness of buried insulating layer 30. Body region 16
Considering that the impurity concentration affects characteristics such as the threshold voltage of MOSFET 100, it is desirable to control the threshold value of the parasitic MOS transistor by the thickness of buried insulating layer 30. By defining the thickness and depth of the buried insulating layer 30, the withstand voltage of the element can be controlled.

Next, the operation of the device will be described.

Referring to FIG._ONIs MOSFET1
00 shows a path of an on-current flowing when 00 is in an on state;
Symbol I_OFFIs close when the MOSFET 100 is off.
Path of current flowing by operation of raw MOS transistor
Is shown. ON current (I _ON) Is the drain region 2
2, along the drift region 14 and the gate insulating layer 72
Source region via a channel region formed by
Flow to 18a.

When a high voltage such as a surge voltage is applied when the MOSFET 100 is off, the parasitic MO
The S transistor operates. That is, the body region 16
Since the potential is fixed to the ground level via the source electrode 44, for example, when a high voltage such as a back electromotive force at the time of driving an inductance load is applied to the drain region 22, the potential of the drift region 14 It rises with it. When the potential of the drain region 14 reaches the threshold voltage of the parasitic MOS transistor, the parasitic MOS transistor is turned on, a channel is formed in the body region 16 adjacent to the buried insulating layer 30, and a current I _OFF flows. As a result, when the MOSFET 100 is in the off state, the element does not break down even if a high voltage is applied. Since the parasitic MOS transistor is set so that its threshold voltage is higher than the power supply voltage and lower than the source-drain breakdown voltage, the MOSF
Does not adversely affect ET100.

For example, in a power device used in a vehicle, it is generally required that the power supply voltage, that is, the battery voltage is about 30 V at the maximum and the element withstand voltage (source-drain withstand voltage) is at least 60 V. Therefore,
If the threshold voltage of the parasitic MOS transistor is set higher than 30V and lower than 60V, the MOSFET 1
The parasitic MOS transistor can be operated when a high voltage is applied in the off state without causing any problem in the operation of 00. As a result, the element can be protected from application of a high voltage such as a surge voltage without causing the element to break down.

Exposing an element to a breakdown state does not necessarily lead to destruction of the element directly, but causes excessive stress to the element, and the accumulation of the stress tends to cause element destruction. In the MOSFET 100 according to the present invention, as described above, by operating the parasitic MOS transistor when off,
Since high voltage can be absorbed without causing the element to be in a breakdown state, element destruction due to accumulation of stress can be reliably avoided.

In addition, the MOSFET 100 has a structure in which the buried insulating layer 30 is embedded in the element, so that it is not necessary to sacrifice the chip area as compared with the conventional method of providing a protection element, so that the element can be miniaturized. be able to.

In MOSFET 100, buried insulating layer 30 is interposed between body region 16 and drain region 22, and this buried insulating layer 30 is formed so as to be in contact with drain region 22. Therefore, the buried insulating layer 30 ensures the withstand voltage of the MOS element. Since the drift current has a portion flowing in a direction perpendicular to the main surface of the silicon substrate 10, the area of the plane region of the drift region 14 can be relatively reduced, and in this regard, the element can be miniaturized. be able to.

Further, since the channel region is formed in the vertical direction with respect to the silicon substrate 10 by having the trench gate structure, the element can be made finer as compared with the planar gate structure.

As described above, the MOSF according to the present embodiment
According to the ET100, by operating the parasitic MOS transistor, breakdown of the element due to a high voltage such as a surge voltage at the time of OFF can be avoided, and element destruction can be prevented. Further, it is possible to secure the element withstand voltage by the buried insulating layer 30 and realize the miniaturization of the element size while securing the drift region 14 for determining the element withstand voltage.

(Manufacturing Process) An example of a manufacturing process of the MOSFET 100 according to the present embodiment will be described below. 3 to 5 are cross-sectional views schematically showing steps of manufacturing the MOSFET 100.

First, as shown in FIG. 3A, a thermal oxide film 60 having a thickness of 100 to 500 nm is formed on a substrate S2 including a silicon substrate 10 and an n-type semiconductor layer (drift region) 14 formed by epitaxial growth. To form Then, an opening is formed at a portion where the impurity is to be introduced by commonly used photolithography and RIE, and a p-type impurity is doped through this opening by a commonly used ion implantation and heat treatment (thermal diffusion) technique. , A body region 16 containing a p-type impurity is formed.

Next, as shown in FIG. 3B, after removing the thermal oxide film 60, a field oxide film 50 having a thickness of 100 nm or more is formed by thermal oxidation or chemical vapor deposition (CVD). .

Next, as shown in FIG. 3C, an opening 52 for forming a trench is formed by photolithography and RIE.

Next, as shown in FIG. 3D, a trench 32 is formed by RIE to a depth of a predetermined distance from the surface of the silicon substrate 10 so as to penetrate at least the body region 16.

Next, as shown in FIG. 4A, an insulating material such as silicon oxide or silicon nitride is buried in the trench 32 by CVD.
A buried insulating layer 30 is formed. Thereby, the body region 1
6 and the drift region 14 are separated from the silicon substrate 10 in the vertical direction. In this step, the insulating layer 62 is formed on the surface of the substrate S2.

Next, as shown in FIG. 4B, an opening 58 for forming a trench is formed in the insulating layer 62 formed in the above step by photolithography and RIE.

Next, as shown in FIG. 4C, a trench 74 reaching the surface of the silicon substrate 10 is formed by RIE.

Next, as shown in FIG. 4D, after a gate insulating layer 72 having a thickness of 0.01 to 0.2 μm is formed on the inner surface of the trench 74, an n-type impurity is doped by a CVD method. The formed amorphous silicon or polycrystalline silicon is deposited in the trench 74 to form the gate electrode 70.

Next, as shown in FIG.
After removing the upper insulating layer 62, the thickness of the silicon oxide film or BPSG film of 0.2 to
A 1 μm interlayer insulating layer 56 is formed.

Next, as shown in FIG. 5B, contact holes for forming electrodes are formed in a predetermined pattern.

Next, as shown in FIG. 5C, first and second source regions 18a and 18b containing a high concentration of n-type impurities are formed by ion implantation and thermal diffusion techniques. At this time, the drain region 22 is formed at the same time.

Next, although not shown, the source regions 18a,
A source electrode 44 is formed on the surface of 18b, and a drain electrode 46 is formed on the surface of the drain region 22.

The order of forming the buried insulating layer 30 and the gate electrode 70 is not particularly limited, and may be reversed from the above-described process.

Through the above steps, the power MOSFET 100 shown in FIGS. 1 and 2 can be manufactured.

(Second Embodiment) FIG. 6 shows a lateral power MOSF having a trench gate structure to which the present invention is applied.
It is sectional drawing which shows ET200 typically. The MOSFET 200 according to the present embodiment is different from the first embodiment in having an SOI structure, but the other structures are the same. MOSFE according to the first embodiment
Portions having functions substantially similar to those of T100 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The MOSFET 200 shown in FIG. 6 has a silicon substrate 10 and an insulating substrate 12.
Drift region containing n-type impurity on 2 (first semiconductor layer)
14 are formed. That is, M of the first embodiment
The OSFET 100 uses PN junction isolation for element isolation, whereas the MOSFET 200 of this embodiment
Uses dielectric isolation. As described above, when a plurality of elements are integrated on one chip by using the dielectric isolation, there is an advantage that electrical insulation between the elements can be more completely realized. Other device structures, operations and advantages of the invention are the same as those of the first embodiment.
The description is omitted.

(Third Embodiment) FIG. 7 shows a lateral power MOSF having a planar gate structure to which the present invention is applied.
It is sectional drawing which shows ET300 typically. The MOSFET 300 according to the present embodiment is different from the first embodiment in the gate structure, but the other structures are the same. The power MOSFET according to the first embodiment
Portions having functions substantially similar to those of T100 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The MOSFET 300 has a p-type silicon substrate 10 and a drift region (first semiconductor layer) 14 formed on the silicon substrate 10 and containing an n-type impurity. Then, a p-type body region (second semiconductor layer) 16 is formed on the upper surface of the drift region 14 by diffusing a p-type impurity, and a high-concentration n-type impurity is By selectively diffusing, the first source region (third semiconductor layer) 18a and the second
Source region (third semiconductor layer) 18b is formed.

Further, on the upper surface of the drift region 14, a drain region (fourth semiconductor layer) is spaced apart from the body region 16.
22 are formed. This drain region 22 contains a high concentration of n-type impurities.

Between the body region 16 and the drain region 22, a buried insulating layer 30 made of silicon oxide, silicon nitride, or the like, extending in the thickness direction of the silicon substrate 10, is formed. The depth of the buried insulating layer 30 is set such that its lower end is formed deeper than the bottom of the body region 16 and has a predetermined distance from the silicon substrate 10.

A planar gate 80 is formed so as to be in contact with body region 16. Planar gate 80
The gate insulating layer 82 is formed on the surfaces of the first source region 18a, the body region 16 and the drift region 14, and the gate electrode 84 is formed on the gate insulating layer 82.

In MOSFET 300 according to the present embodiment, similarly to MOSFET 100 of the first embodiment, buried insulating layer 30 is used as a gate insulating layer, body region 16 is used as a channel region, and buried insulating layer 30 is interposed. A parasitic MOS transistor is formed in which the drift region 14 on the opposite side to the body region 16 is used as a gate electrode and the second source region 18b is used as a source. The threshold voltage of the parasitic MOS transistor is set to be higher than the power supply voltage and lower than the source-drain breakdown voltage (device breakdown voltage).

The threshold value of the parasitic MOS transistor can be set according to the impurity concentration of body region 16 and the thickness of buried insulating layer 30. Body region 16
Considering that the impurity concentration affects characteristics such as the threshold voltage of MOSFET 300, it is desirable to control the threshold value of the parasitic MOS transistor by the thickness of buried insulating layer 30. By defining the thickness and depth of the buried insulating layer 30, the withstand voltage of the element can be controlled.

Next, the operation of the device will be described.

In FIG. 7, the symbol I_ONIs MOSFET3
00 shows a path of an on-current flowing when 00 is in an on state;
Symbol I_OFFIs close when the MOSFET 300 is off.
Path of current flowing by operation of raw MOS transistor
Is shown. ON current (I _ON) Is the drain region 2
2, along the drift region 14 and the gate insulating layer 82
Source region via a channel region formed by
Flow to 18a.

When a high voltage such as a surge voltage is applied when the MOSFET 300 is off, the parasitic MO
The S transistor operates. That is, the body region 16
Since the potential is fixed to the ground level via the source electrode 44, for example, when a high voltage such as a back electromotive force at the time of driving an inductance load is applied to the drain region 22, the potential of the drift region 14 It rises with it. When the potential of the drain region 14 reaches the threshold voltage of the parasitic MOS transistor, the parasitic MOS transistor is turned on, a channel is formed in the body region 16 adjacent to the buried insulating layer 30, and a current I _OFF flows. As a result, when the MOSFET 300 is in the off state, the element does not break down even if a high voltage is applied. Since the parasitic MOS transistor is set so that its threshold voltage is higher than the power supply voltage and lower than the source-drain breakdown voltage, the MOSF
Does not adversely affect ET300.

In the MOSFET 300, as described above, by operating the parasitic MOS transistor when the MOSFET is off, a high voltage can be absorbed without causing the element to be in a breakdown state. Can be avoided.

Further, since the MOSFET 300 has a structure in which the buried insulating layer 30 is embedded in the element, it is not necessary to sacrifice the chip area as compared with the conventional method of providing a protection element, so that the element is miniaturized. be able to.

In MOSFET 300 according to the present embodiment, buried insulating layer 30 is interposed between body region 16 and drain region 22, and this buried insulating layer 30 is formed so as to be in contact with drain region 22. .
Therefore, the buried insulating layer 30 ensures the withstand voltage of the MOS element. The drift current is applied to the silicon substrate 1
Since it has a portion flowing in the direction perpendicular to the main surface of 0,
The area of the plane region of the drift region 14 can be relatively reduced, and in this regard, the element can be miniaturized.

As described above, the MOSF according to the present embodiment
According to ET300, by operating the parasitic MOS transistor, breakdown of the element due to a high voltage such as a surge voltage at the time of off can be avoided, and element destruction can be prevented. Further, it is possible to secure the element withstand voltage by the buried insulating layer 30 and realize the miniaturization of the element size while securing the drift region 14 for determining the element withstand voltage.

(Fourth Embodiment) FIG. 8 shows a lateral IGBT 4 having a trench gate structure to which the present invention is applied.
FIG. 4 is a cross-sectional view schematically showing 00. This IGBT400
Has a structure in which a p-type collector region 24 is provided instead of the n-type drain region 22 in the MOSFET 100 shown in FIG. That is, the IGBT 400 is a bipolar transistor having an n-type MOS gate.

The IGBT 400 is a p-type silicon substrate 10
And an n-type base region (first semiconductor layer) 14 formed on the silicon substrate 10. On the upper surface of the n-type base region 14, a p-type impurity (diffusion) is formed to form a p-type base region (second semiconductor layer) 16. n
By selectively diffusing the type impurities, a first emitter region (third semiconductor layer) 18a and a second emitter region (third semiconductor layer) 18b are formed. These p-type base region 16 and emitter regions 18a, 18b
Are formed by double diffusion using a self-alignment technique.

Further, on the upper surface of the n-type base region 14,
A collector region (fourth semiconductor layer) 24 is formed apart from p-type base region 16. This collector region 24
Contains a high concentration of p-type impurities.

P-type base region 16 and p-type collector region 2
4, extending in the thickness direction of the silicon substrate 10;
A buried insulating layer 30 made of silicon oxide, silicon nitride, or the like is formed. The buried insulating layer 30 is formed such that its lower end is deeper than the bottom of the p-type base region 16.
The depth is set so as to have a predetermined distance from the silicon substrate 10.

A trench gate is formed so as to be in contact with p-type base region 16. That is, the trench 74 includes the first emitter region 18 a and the p-type base region 1.
6 and the n-type base region 14 and the silicon substrate 1
0 is formed. A gate insulating layer 72 is formed on the surface of trench 74. And
A gate electrode 70 is formed inside the gate insulating layer 72. Thus, the trench 74 is formed in the silicon substrate 10.
By forming the gate insulating layer 72 to the inside and forming the bottom corner of the gate insulating layer 72 in the silicon substrate 10, the withstand voltage can be further increased as compared with the case where it is not.

The first emitter region 18a, the exposed p-type base region 16 and the second emitter region 18b
, An emitter electrode 44 is formed on the surface of the collector region 24, and a collector electrode 48 is formed on the surface of the collector region 24.
The emitter electrode 44 and the collector electrode 48 are electrically separated from each other by the insulating layer 56.

In the IGBT 400 according to the present embodiment, the buried insulating layer 30 is a gate insulating layer, the p-type base region 16 is a channel region, and the buried insulating layer 30 is on the side opposite to the p-type base region 16 via the buried insulating layer 30. A parasitic MOS transistor having the n-type base region 14 as a gate electrode and the second emitter region 18b as a source is formed. The parasitic MOS transistor is set so that its threshold voltage is higher than the power supply voltage and lower than the emitter-collector breakdown voltage (element breakdown voltage).

The threshold value of the parasitic MOS transistor is p
Concentration of the base region 16 and the buried insulating layer 30
Can be set according to the thickness of the film. Considering that the impurity concentration of the p-type base region 16 affects characteristics such as the threshold voltage of the MOS gate, it is desirable to control the threshold value of the parasitic MOS transistor by the thickness of the buried insulating layer 30. By defining the thickness and depth of the buried insulating layer 30, the withstand voltage of the element can be controlled.

Next, the operation of the device will be described.

In FIG. 8, the symbol I _ON represents an IGBT 400
Indicates a path of a hole current flowing when the IGBT 400 is in an on state, and a symbol I _OFF indicates a parasitic MOS
4 shows a path of an electron current flowing by the operation of the transistor.

When a high voltage such as a surge voltage is applied when IGBT 400 is off, the parasitic MOS transistor operates. That is, the p-type base region 16
Since the potential is fixed to the ground level via the emitter electrode 44, for example, when a high voltage such as a back electromotive force at the time of driving an inductance load is applied to the collector region 24, the potential of the n-type base region 14 is also changed to the same. It rises with it. When the potential of the collector region 14 reaches the threshold voltage of the parasitic MOS transistor, the parasitic MOS transistor is turned on, a channel is formed in the p-type base region 16 close to the buried insulating layer 30, and a current I _OFF flows. As a result, when the IGBT 400 is off, the device does not break down even if a high voltage is applied. Since the threshold voltage of the parasitic MOS transistor is set to be higher than the power supply voltage and lower than the emitter-collector breakdown voltage, the parasitic MOS transistor does not adversely affect the element.

In the IGBT 400, as described above, by operating the parasitic MOS transistor when the IGBT 400 is off, a high voltage can be absorbed without causing the element to be in a breakdown state. Can be avoided.

The IGBT 400 has a structure in which the buried insulating layer 30 is buried inside the device, so that it is not necessary to sacrifice the chip area as compared with the conventional method of providing a protection device, so that the device is miniaturized. be able to.

In IGBT 400 according to the present embodiment, buried insulating layer 30 is interposed between p-type base region 16 and collector region 24, and buried insulating layer 30 is formed in a state of being in contact with collector region 24. ing.
Therefore, the buried insulating layer 30 ensures the withstand voltage of the MOS element and can prevent the latch-up of the parasitic thyristor. Since the drift current has a portion flowing in the direction perpendicular to the main surface of the silicon substrate 10, the area of the planar region of the n-type base region 14 can be relatively reduced. Can be achieved.

Further, since the channel region is formed in the vertical direction with respect to the silicon substrate 10 by having the trench gate structure, the element can be miniaturized as compared with the planar gate structure.

As described above, the IGBT according to the present embodiment
According to 400, by operating the parasitic MOS transistor, breakdown of the element due to a high voltage such as a surge voltage at the time of off can be avoided, and element destruction can be prevented. Further, it is possible to secure the element breakdown voltage by the buried insulating layer 30 and realize the miniaturization of the element size while securing the n-type base region 14 that can determine the element breakdown voltage.

In the IGBT, the SOI substrate of the second embodiment and the planar gate structure of the third embodiment can be employed.

The present invention can be applied to a semiconductor device including a p-type MOS element.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a lateral power MOSFET having a trench gate gate structure according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view schematically showing the MOSFET shown in FIG. 1 along line AA.

FIGS. 3A to 3D show MOs shown in FIGS. 1 and 2;
It is sectional drawing which shows the manufacturing method of SFET typically in a process order.

4 (a) to 4 (d) are cross-sectional views schematically showing a MOSFET manufacturing method performed after the step shown in FIG. 3 in the order of steps.

FIGS. 5A to 5C are cross-sectional views schematically showing a method for manufacturing a MOSFET, which is performed subsequent to the step shown in FIG.

FIG. 6 is a cross-sectional view schematically showing a lateral power MOSFET having a trench gate structure according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view schematically showing a lateral power MOSFET having a planar gate structure according to a third embodiment of the present invention.

FIG. 8 is a cross-sectional view schematically showing a lateral IGBT having a trench gate structure according to a fourth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 12 insulating substrate 14 drift region, base region 16 body region, base region 18 source region, emitter region 18a first source region, first emitter region 18b second source region, second emitter region 22 drain Region, 24 collector region 30 buried insulating layer 44 source electrode, emitter electrode 46 drain electrode 48 collector electrode 70 gate electrode 72 gate insulating layer 74 trench 80 planar gate 82 gate insulating layer 84 gate electrode

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masato Kijin 41-1, Oku-cho, Yokomichi, Nagakute-cho, Aichi-gun, Aichi F-term in Toyota Central R & D Laboratories, Inc. (reference) 5F040 DA00 DA21 DA24 DC01 EB14 EC07 EC20 EE04 EF18 EK01 EM02 EM03 FC21 5F110 AA13 AA22 CC10 DD01 DD05 EE08 EE09 GG02 NN74

Claims (4)

[Claims] 1. A substrate made of a semiconductor or an insulator, a first semiconductor layer of a first conductivity type formed on the substrate and constituting a drift region, and formed in contact with the first semiconductor layer to form a body region. Forming a channel region in the body region.
A second semiconductor layer of a conductivity type, a third semiconductor layer of a first conductivity type selectively formed on the second semiconductor layer and forming a source region in contact with the channel region; A first conductive type fourth layer formed with the first semiconductor layer interposed and constituting a drain region.
A semiconductor layer, at least an insulated gate formed in contact with the channel region, and a buried insulating layer formed between the second semiconductor layer and the fourth semiconductor layer; Is formed at a depth reaching at least the bottom of the second semiconductor layer, and a channel region of a parasitic MOS element is formed in the second semiconductor layer along the buried insulating layer. A substrate made of a semiconductor or an insulator; a first semiconductor layer of a first conductivity type formed on the substrate and constituting a base region; and a first semiconductor layer formed in contact with the first semiconductor layer. A second conductive type second semiconductor layer having a channel region formed in the base region; a first conductive layer selectively formed in the second semiconductor layer and forming an emitter region in contact with the channel region; A third semiconductor layer of a type, a fourth semiconductor layer of a second conductivity type formed between the second semiconductor layer and the first semiconductor layer and constituting a collector region, formed at least in contact with the channel region A buried insulating layer formed between the second semiconductor layer and the fourth semiconductor layer, wherein the buried insulating layer has a lower end reaching at least a bottom of the second semiconductor layer. Formed by Is, and the channel region of the parasitic MOS devices along 該埋 included insulating layers in said second semiconductor layer is formed, a semiconductor device including a lateral MOS device. 3. The threshold voltage of a parasitic MOS device including at least the buried insulating layer, the second semiconductor layer, and the third semiconductor layer according to claim 1, wherein the threshold voltage is higher than a power supply voltage. Lateral MOS set smaller than the source-drain breakdown voltage of the MOS element
A semiconductor device including an element. 4. The trench according to claim 1, wherein the insulated gate is a trench formed through the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer, and a surface of the trench. A semiconductor device including a lateral MOS element, having a gate insulating layer formed along the gate line, and a gate electrode formed inside the trench via the gate insulating layer.