JP2000252352A - Substrate holder and charged particle beam aligner employing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To replace a wafer at high speed by forming grooves of specified width and depth, at a specified interval, in a chucking face of insulator longitudinally and latitudinally thereby ensuring sufficient heat transfer. SOLUTION: Anti-slip grooves 7 are formed, at a fine pitch, in the attraction face 3 of an electrostatic chuck 1 in X, Y directions. The groove pitch is set at 250 μm or less so that at least one anti-slip grooves 7 is present in one transfer area of 250 μm square on the wafer. The anti-slip groove does not require a large width and the width is preferably set at 10 μm or less in order to increase the chucking face of the chuck touching the wafer. The depth is also set at 10 μm or less in order to facilitate the machining. According to the arrangement, sufficient heat transfer is ensured and the wafer can be replaced at high speed. Furthermore, slip between the wafer and the chuck can be prevented when the wafer is heated through EB irradiation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a substrate holding apparatus for holding a substrate such as a wafer provided in an exposure apparatus for forming a pattern of a semiconductor device under vacuum. In particular, the present invention relates to a substrate holding device which takes measures against problems such as thermal expansion of a substrate or dust between a substrate and a substrate suction surface. Further, the present invention relates to an exposure apparatus having such a substrate holding device.

[0002]

2. Description of the Related Art In a substrate holding apparatus of this type (hereinafter also referred to as a chuck), a wide groove (for example, 0.09 mm wide) is formed on a suction surface of a substrate in order to prevent dust from adhering to the substrate and floating the wafer as much as possible. ) (For example, pitch 0.1m)
m, groove area ratio 81%). The groove is filled with He gas to compensate for the reduced heat transfer due to the reduced contact area between the chuck suction surface and the wafer due to the presence of the groove. In addition, the above-mentioned groove is usually formed by machining.

[0003]

When such a chuck using He gas is used in a charged particle beam (electron beam, ion beam, etc.) exposure apparatus for exposing under vacuum, the following problems occur. That is, after the exposure is completed, if the He gas is completely exhausted and then the wafer is to be removed, H
The e-gas is in a groove with a very small conductance, and the piping connecting the pump and the chuck has a small conductance, so that it takes a long time to exhaust. However, if the wafer is removed with a little He gas remaining in the groove, it is difficult to exhaust H into the wafer chamber.
The e-gas diffuses and adversely affects the device.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a substrate holding apparatus which has sufficient heat transfer and can exchange wafers at a high speed. Also, by preventing a slip from occurring between the wafer and the chuck when the wafer is heated by the EB irradiation, it is possible to prevent the wafer from slightly changing its position due to thermal expansion so as not to affect the exposure accuracy. is there. It is a further object of the present invention to prevent adverse effects on exposure when dust is present between the substrate and the chuck.

[0005]

Means for Solving the Problems and Embodiments of the Invention In order to solve the above problems, a substrate holding apparatus of the present invention is an apparatus having a substrate suction surface made of an insulator and holding a substrate in a vacuum. A width of 10 μm or less and a depth of 10 μm
Grooves of less than μm are formed vertically and horizontally with an interval of less than 250 μm. Here, it is preferable that the area ratio occupied by the groove on the suction surface is 1 to 10%. Note that the lower limit of the groove width and the depth is 1 width in consideration of processing reliability and the like.
It is considered to be about μm and about 1 μm deep.

In the case of a vacuum chuck, even if the ratio between the groove and a portion (referred to as a protrusion) in contact with the substrate other than the groove is changed,
There is no change in the total of the chucking force. Therefore, the chuck pressure increases in inverse proportion to the total area of the projection. For this reason, it is advantageous to make the groove wider and the protrusion smaller, without taking measures against dust. However, in the case of an electrostatic chuck, the chucking force is greatly reduced when a vacuum layer enters between the substrate and the insulator, depending on the depth of the groove. Therefore, in the present invention, the dimensions and the like of the groove are limited so that most of the chuck surface is in contact with the wafer.

[0007] A substrate holding device according to another aspect of the present invention has a substrate suction surface made of a thick base, an electrode, and an insulator.
The thick plate base or the adsorption surface is made of an insulator having a thermal conductivity higher than that of Si. A charged particle beam exposure apparatus according to the present invention includes: an optical system that forms an image of a charged particle beam on a sensitive substrate; a substrate holding device that holds the sensitive substrate; and a charged particle beam path of the optical system and a periphery of the sensitive substrate. A charged particle beam exposure apparatus comprising: means for maintaining; means for measuring an optical axis direction position of each part of the surface to be exposed of the sensitive substrate fixed on the substrate holding device; and a control unit for controlling each part. The substrate holding device has a substrate suction surface made of an insulating material,
It is an insulator whose thermal conductivity is larger than that of Si. Furthermore, the position in the optical axis direction of a small area of the exposed area on the sensitive substrate is measured, and the position of the sensitive substrate in the optical axis direction is determined based on the result. Alternatively, it is characterized in that the specifications of the optical system are controlled.

Even when there is no slip between the wafer and the chuck, individual positions on the exposed surface of the wafer drift little by little due to thermal expansion of the wafer and the chuck.
In order to correct this drift, a mark or the like on the wafer is detected and measured for each exposure area in a certain small unit, and the exposure position is adjusted based on the result. Thereby, high-precision exposure can be performed.

In the charged particle beam exposure apparatus of the present invention,
Furthermore, a detector is provided for measuring the position (height) of each part of the surface to be exposed of the sensitive substrate in the optical axis direction, and the control unit receives information from the detector and performs the above-mentioned operation in accordance with the height of the exposure position. It is preferable to control the specifications of the optical system.

When the area ratio of the groove on the chuck suction surface is low, the problem of dust between the chuck and the wafer becomes serious,
There is no problem if the position (height) of the entire surface of the wafer in the optical axis direction is measured and the focus is corrected for each small exposure area.

A description will be given below with reference to the drawings. First,
An overall configuration of an electron beam exposure apparatus according to one embodiment of the present invention will be described. FIG. 3 is a diagram schematically showing an outline of a division transfer type electron beam projection exposure apparatus according to one embodiment of the present invention.
The electron gun 21 arranged at the uppermost stream of the optical system emits an electron beam downward. A condenser lens system 22 is provided below the electron gun 1.

An illumination beam shaping aperture 23 is provided below the condenser lens system 22. This molding opening 23
Passes only an illumination beam that illuminates one subfield (unit exposure pattern area) of the mask (reticle) 26. Specifically, the opening 23 forms the illumination beam into a square having a dimension of slightly more than 1 mm square in mask size conversion.
The image of the opening 23 is formed by the illumination lens 25 on the mask 2.
6 is formed.

Below the beam shaping aperture 23, there is a blanking deflector, a blanking aperture, and an illumination beam deflector 24.
Etc. are arranged. The blanking deflector deflects the illumination beam to strike the non-opening of the blanking aperture so that the beam does not strike the mask 26. The illumination beam deflector sequentially scans the illumination beam mainly in the X direction in FIG. 3 to illuminate each subfield of the mask 26 within the field of view of the illumination optical system.

An illumination lens 25 is provided below the molding opening 23.
Is arranged. The illumination lens 25 converts the electron beam into a parallel beam and impinges it on the mask 26, and forms an image of the beam forming aperture 23 on the mask 26.

The mask 26 is located in a plane perpendicular to the optical axis (XY plane).
And has a number of subfields (described below with reference to FIG. 4). On the mask 26, a pattern (chip pattern) forming one semiconductor device chip as a whole is formed.

The mask 26 is mounted on a mask stage 27 that can move in the X and Y directions. To illuminate each subfield beyond the field of view of the illumination optical system, the mask 26 is moved mechanically. Since each subfield is illuminated within the field of view of the illumination optical system, the electron beam can be deflected by the deflector 24 as described above.

Below the mask 26, projection lenses 28 and 33, a deflector 29 and the like are provided. Then, an illumination beam is applied to a certain subfield of the mask 26, and the electron beam passing through the pattern portion of the mask 26 is reduced by the projection lenses 28 and 33, and deflected by the lenses and the deflector 29 to be deflected by the wafer 45. An image is formed at a predetermined position above. An appropriate resist is applied on the wafer 45, the resist is given an electron beam dose, and the pattern on the mask 27 is reduced and transferred onto the wafer 45.

The second projection lens 28 and the second projection lens 33
A dynamic focus coil 31 is also disposed between them. The dynamic focus coil adjusts the focus position of the pattern image on the mask 27 at high speed.

Z sensors (optical axis direction position detectors) 37, 3 are located on the side of the second projection lens 33 on the wafer 45.
9 are provided. These Z sensors 37 and 39 are so-called oblique incidence type optical position detectors (JP-A-56-4220).
No. 5, JP-A-58-113706, etc.). The detection light 41 emitted obliquely downward from the sensor light source 37 on the left side of the drawing strikes the surface to be exposed of the wafer 45, is reflected obliquely upward, and enters the Z sensor detector 39. This detector 39
The height of the wafer exposure surface can be detected from the characteristics of the reflected light from the wafer exposure surface incident on the wafer.

The deflector 29, the dynamic focus coil 31, and the Z sensors 37 and 39 are controlled by a pattern imaging position control unit 35 (a part of a computer for controlling the exposure apparatus). Details of the operation will be described later.

Immediately above the wafer 45, the secondary electron detector 4
3 are arranged. The secondary electron detector 43 detects secondary electrons emitted from the wafer 45. Detected 2
The position of the mark on the wafer 45 can be known from the next electron signal, and basic information on the alignment between the wafer and the optical system or the mask can be obtained. Further, the position fluctuation of each part of the wafer during the exposure can be known.

The wafer 45 is fixed on the electrostatic chuck 1 by suction. The electrostatic chuck 1 is mounted on a wafer stage 53 that can move in the X and Y directions. By synchronously scanning the mask stage 27 and the wafer stage 53 in directions opposite to each other, it is possible to sequentially expose a number of subfields arranged in a chip pattern. In addition, both stages 27 and 53 are equipped with an accurate position measuring system using a laser interferometer, and the position of the stage is accurately controlled. By controlling the accurate stage position and the optical system, the reduced images of the subfields on the mask 26 are accurately joined on the wafer 45, and the entire chip pattern on the mask is transferred onto the wafer. The chuck surface and the main body (thick plate base) of the chuck 1 are made of high heat conductive SiC.

The above optical system, stage, etc.
And housed in a wafer chamber 51. Lens barrel 1
A vacuum pump 17 is connected to the upper part of the apparatus 3 via a duct 15. By operating this pump 17,
The inside of the lens barrel 13 and the chamber 51 becomes a vacuum atmosphere.

FIG. 4 is a plan view schematically showing a divided state of a pattern to be transferred by the electron beam transfer exposure apparatus according to one embodiment of the present invention. (A) shows the arrangement of the entire pattern, and (B) shows a portion B of (A) in an enlarged manner.
This drawing conceptually shows both the pattern on the mask and the pattern on the wafer.
The entire pattern area 71 shown in FIG. 4A is divided into six stripes 72 arranged in the X direction. Each stripe 72 includes a number of subfields (reference numeral 90 in (B)).
Are further divided into deflection bands 73, 75, 83, 85, etc., which are columns in the X direction.

According to a system which is currently considered to be influential,
During the transfer exposure, the rows (deflection bands) of the X-direction subfields in one stripe 72 are sequentially exposed by electron beam deflection. On the other hand, the rows in the Y direction in the stripe 72 are sequentially exposed by continuous stage scanning. Next stripe 7
When going to 2, send the stage intermittently.

The reduction rate of transfer is considered to be 1/4 or 1/5, and the size of one chip on a wafer is as follows.
Since 27mm x 44mm is assumed for 4G DRAM,
The overall size of the mask including the non-pattern portion of the chip pattern is about 120 to 230 mm × 150 to 350 mm.

In this example, deflection strips 73, 75 in which beam position evaluation marks (see reference numerals 91, 93 in FIG. 4B) are arranged at both ends in the Y direction of each stripe 72 in the entire pattern area 71. 85, 87, etc. are arranged. The deflection bands 83 other than the deflection bands at both ends are portions where a general pattern (device pattern) is formed.

As shown in FIG. 4B, the beam position evaluation marks 91 and 93 are formed by arranging some linear marks. X-directional beam position evaluation mark 91
In the figure, linear marks extending in the Y direction are arranged in the X direction. In the mark 93 for evaluating the beam position in the Y direction, linear marks extending in the X direction are arranged in the Y direction. These marks 91 and 93 are portions (holes or low-scattering membrane portions) where the electron beam is hardly scattered on the mask, and are metal layers or edge portions that easily reflect the electron beam on the wafer.

In this example, the exposure of the pattern is performed along the transfer direction 79 indicated by the arrow. That is, starting from the exposure of the mark arrangement deflection band 85 at the lower left of the drawing, the first stripe 72a is moved upward, and the first stripe 72a is exposed.
Make a U-turn on the second stripe 72b and proceed downward. After that, make a U-turn under the second stripe 72b and proceed to the next stripe.

Next, the alignment in the transfer exposure of the pattern of FIG. 4 will be described. At the stage where the wafer is placed on the wafer stage, the position of the optical mark separately formed on the wafer is measured by an optical microscope attached to the electron beam exposure apparatus, and the entire wafer is globally aligned.

The transfer is performed in the order of the arrow 79 as described above, and the exposure is first started from the mark arrangement deflection band 85 at the lower left of FIG. The mark arrangement deflection band 85 is provided with beam position evaluation marks 91 and 93 shown in FIG. 4B, and the mark detection is performed. When the optical axis starts to enter the inside of the deflection band 85, mark detection starts. At this time, since the transfer has not been performed yet, no thermal distortion has occurred, and if only the relative position between the beam and the mark can be detected, a correction value at the time of transfer (translation component, difference between the relative position between the beam and the wafer mark) Can be calculated. The position of the optical axis in the X direction is aligned with the center 95 of the deflection band 85 where the marks 91 and 93 are provided.

Using the correction data, the first stripe 72a is transferred and exposed to the upper end of the drawing. Next, the stage is moved in the X direction to place the second stripe 72b below the optical axis, and the exposure is advanced in the downward direction of the second stripe 72b. At this time, mark detection is performed when the optical axis enters the uppermost deflection band 75 of the second stripe 72b. Then, a change in the rotation of the wafer (due to thermal expansion or the like) is first calculated from the data detected in the deflection band 85 at the lower end of the first stripe 72a and the data detected in the current deflection band 75.
Regarding the relative position between the beam and the wafer, the transfer position of the stripe 72b is corrected by correcting the transfer position based on the mark detection result in the mark arrangement deflection band 75 of the second stripe 72b.

Incidentally, marks may be provided at both ends of the deflection band having a length of 5 mm, and the rotation may be calculated by detecting the marks.
Since the relative position between the beam and the wafer is corrected using the value measured immediately before the transfer, the thermal distortion can be effectively corrected.

Next, details of the electrostatic chuck will be described. FIG. 1 is a schematic diagram for explaining a configuration of a wafer holding chuck of an exposure apparatus according to one embodiment of the present invention. (A) is an overall plan view, (B) is B in (A).
Part (C) is a side sectional view of the part B, (D).
FIG. 2 is a partial cross-sectional side view schematically illustrating the entire configuration. The chuck 1 includes an insulator disk 1a made of ceramics or the like. The wafer is suction-held on the upper surface (suction surface) 3 of the insulator 1a.

Electrodes 2a and 2b are buried immediately below the suction surface 3 of the electrostatic chuck 1. Each of the electrodes 2a and 2b extends in a fan-shaped region which is approximately 1/6 of the suction surface 3. A power supply 5a, 5b is connected to each of the electrodes 2a, 2b. The two power supplies 5a and 5b have opposite polarities. The polarities of the voltages applied to the electrodes 2a and 2b are also opposite to each other. The portion of the chuck body below the electrode is called a thick plate base.

As shown in FIGS. 1B and 1C, slip preventing grooves 7 are formed on the surface 3 of the chuck at fine pitches in the X and Y directions. In this example, the groove pitch was set to 200 μm so that at least one slip stopper groove 7 was always included in a 250 μm square, which was a single transfer area on the wafer. Since the purpose of the groove is to prevent slippage, the width does not need to be large. The narrower groove is preferable because the area where the chucking surface 3 contacts the wafer is larger, and the groove width is set to 10 μm or less. Since the shallower the depth, the easier it is to process, the depth is set to 10 μm or less.

Next, a method of forming the groove of the chuck will be described with reference to FIG. FIG. 2 is a schematic side view illustrating an example of a process of processing a groove of the chuck. Forming a 10 μm wide groove is not easy when the substrate is an insulator (ceramic). As shown in FIG. 2, first, (a) polyimide 20 μm is formed on chuck surface 3 as heat-resistant resist 9.
m thickness. Next, as shown in (b), a pattern was formed by photolithography, and a part 10 of the resist 9 was removed. Next, as shown in (c), a groove 7 having a width of 10 μm was dug in the suction surface 3 of the chuck base 1a by sandblasting. Finally, as shown in (d), the resist 9 was removed, and the processing of the groove 7 was completed.

In the chuck according to the present embodiment, no gas flows through the groove, so that heat transfer from the wafer to the chuck depends only on conduction. Therefore, the insulating layer and the thick substrate of the chuck are made of a material having a higher thermal conductivity than Si so that the temperature of the wafer does not rise due to the electron beam irradiation during the exposure. Si
Materials having better thermal conductivity than (thermal conductivity 125 W / m ° K) include high thermal conductive SiC (270 W / m ° K) and Si
C single crystal (60-490 W / m ° K), diamond (900-2000 W / m ° K), BeO (260 W / mK)
mK) and AlN (60-170 W / mK).
Single-crystal SiC and diamond are expensive, and even if they have an extremely high thermal conductivity than Si, they are not so effective and are therefore difficult to target. BeO is toxic and not preferred. AlN and high thermal conductivity SiC are good in terms of thermal conductivity. Particularly, it is known that a material having a high thermal conductivity SiC, referred to as Hitaceram SC-101, to which a small amount of beryllium (BeO) is added as an auxiliary has particularly high electric resistance and excellent heat conductivity. (NIKKEI ELECTR
ONICS1984.9.24, p267) In addition, high thermal conductivity SiC has a temperature conductivity of 1.4 cm ² /
sec, Cu (1.2 cm ² / sec), Al (1.
It is a large value compared to 0cm ² /sec),AlN(0.7cm ² / sec).

As a measure against dust, as described with reference to FIG.
The positions of the exposed surface of the wafer 45 in the optical axis direction are measured by the Z sensors 37 and 39, and are fed back to the dynamic focus coil 31 to perform the focusing again. As a result, X
If a position change in the Y direction occurs, the position is corrected by feeding back to the deflector 29.

[0040]

As is apparent from the above description, according to the present invention, it is possible to provide a substrate holding apparatus which has sufficient heat transfer and can exchange wafers at a high speed. Also, it is necessary to prevent a slip from occurring between the wafer and the chuck when the wafer is heated by EB irradiation, and to prevent the exposure accuracy from being affected even if the wafer slightly changes its position due to thermal expansion. it can. Further, it is possible to prevent adverse effects on exposure when dust is present between the substrate and the chuck.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining a configuration of a wafer holding chuck of an exposure apparatus according to one embodiment of the present invention.
(A) is an overall plan view, (B) is an enlarged plan view of a B portion in (A), (C) is a side cross-sectional view of the B portion, and (D) is a partial cross-section schematically showing the entire configuration. It is a side view.

FIG. 2 is a schematic side view showing an example of a machining process of a groove of a chuck.

FIG. 3 is a view schematically showing an outline of a division transfer type electron beam transfer exposure apparatus according to one embodiment of the present invention.

FIG. 4 is a plan view schematically showing a divided state of a pattern to be transferred by an electron beam transfer exposure apparatus according to one embodiment of the present invention. (A) shows the arrangement of the entire pattern, and (B) shows a portion B of (A) in an enlarged manner.

DESCRIPTION OF SYMBOLS 1 Electrostatic chuck 2 Electrode 3 Suction surface 5 Power supply 7 Groove 9 Resist 11 Electron beam exposure device 13 Optical column 15 Duct 17 Vacuum pump 21 Electron gun 22 Condenser lens system 23 Illumination beam shaping aperture 24 Deflector 25
Illumination lens 26 Mask 27 Mask stage 28 First projection lens 29 Deflector 31 Dynamic focus coil 33 Second projection lens 35 Pattern imaging position controller 37 Z sensor light source 39 Z sensor detector 43 Secondary electron detector 45 Wafer 51 Wafer Chamber 53 Wafer stage 71 Overall pattern area 72 Stripe 72a First stripe 72b Second stripe 73 Preliminary mark arrangement deflection band 75 Mark arrangement deflection band 79 Transfer direction 83 General pattern deflection band 85 Mark arrangement deflection band 90 Subfield 91 X direction beam Position evaluation mark 93 Y-direction beam position evaluation mark

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H097 BA02 BA04 CA16 GA22 GA41 KA28 LA10 5F031 HA02 HA08 HA16 MA27 NA05 PA26 PA30 5F046 AA05 AA22 CC05 CC09 DA27 DB04 DC04 EC03 5F056 AA15 AA23 CB25 EA17

Claims (8)

[Claims] 1. An apparatus for holding a substrate in a vacuum having a substrate suction surface made of an insulating material;
A substrate holding apparatus characterized in that grooves having a depth of 0 μm or less and a depth of 10 μm or less are formed vertically and horizontally at an interval of 250 μm or less. 2. The substrate holding device according to claim 1, wherein an area ratio of the groove on the suction surface is 1 to 10%. 3. The substrate holding device according to claim 1, wherein said groove is formed by sandblasting. 4. The method according to claim 1, wherein the substrate holding device is an electrostatic chuck, and when an insulating material is formed on a surface to be attracted of the substrate, a voltage applied to the electrostatic attraction electrode is increased. Item 3. The substrate holding device according to item 1 or 2. 5. A substrate holding apparatus having a substrate suction surface composed of a thick substrate, an electrode and an insulator; wherein the thick substrate or the adsorption surface is made of an insulator having a thermal conductivity larger than that of Si. A substrate holding device characterized by the above-mentioned. 6. The substrate holding device according to claim 5, wherein said insulator is high thermal conductive SiC. 7. An optical system for forming an image of a charged particle beam on a sensitive substrate, a substrate holding device for holding the sensitive substrate, a means for maintaining a charged particle beam passage of the optical system and a periphery of the sensitive substrate in a vacuum, A charged particle beam exposure apparatus comprising: means for measuring the position in the optical axis direction of each part of the surface to be exposed of the sensitive substrate fixed on the substrate holding device; and a control unit for controlling each part; The holding device has a substrate adsorption surface made of an insulator, and the adsorption surface has a thermal conductivity of Si.
It is an insulator that is larger than that of the sensitive substrate.Furthermore, the position in the optical axis direction of a part of the exposure area on the sensitive substrate is measured, and based on the result, the position of the sensitive substrate in the optical axis direction or A charged particle beam exposure apparatus characterized by controlling the specifications. 8. The charged particle beam exposure apparatus according to claim 7, wherein said insulator is high thermal conductive SiC.