JP2000250957A - Logic simulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute logic simulation such as a large scale multi-processor system under a condition approximated to actual operation without loading a processor logic file. SOLUTION: A logic simulator 120 to simulate memory control logic at a gate level is linked with an architecture simulator 100 to simulate execution of an instruction at a data transfer level by using a program to be operated on an actual machine. And a function to transfer control to the side of the logic simulator by cyclically executing plural instructions by pseudo advance control and queuing memory requests for an instruction in a memory access system is provided in the architecture simulator 100.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation of a large-scale multiprocessor system and the like. The present invention relates to a logic simulation device suitable for realizing a system simulation in a state where no logic simulation is performed.

[0002]

2. Description of the Related Art In a conventional logic simulation method of a multiprocessor system, it is assumed that processor logic (processor logic file) is mounted on a logic simulator or emulator. But,
In a set development of a system using a mass-produced processor chip such as a commercially available one, a logic file of a processor may not exist in a logic simulation stage. Also, when a large-scale multiprocessor system is simulated, the number of target logic gates exceeds the upper limit of the number of logic gates that can be implemented in a logic simulator or emulator. If simulation cannot be realized, or
There is a problem that the simulation performance decreases as the number of mounted logic gates increases.

Conventionally, as a method of solving such a problem, not mounting processor logic to reduce the total number of mounted gates and improve simulation performance,
There has been proposed a method of expanding the scale of a system to be simulated by increasing the scale of implementation of memory control and inter-processor network logic. In this method, an architecture simulator that simulates program execution at the instruction level is connected to the logic simulator instead of the processor logic, and the architecture simulator and the logic simulator are operated alternately and cyclically.
This realizes a system simulation of a large-scale parallel processor or the like. Note that such a logic simulation method is described in, for example, JP-A-8-96021.
No., published in Japanese Unexamined Patent Publication No.

[0004]

In the above conventional method,
A memory request signal or a bus transaction generated by a memory access instruction executed by the architecture simulator is added to the memory control logic or bus, and the logic simulator or emulator is started. When the logic simulator or emulator completes execution of an arbitrary simulation cycle, the architecture simulator executes the next instruction. The system simulation was realized by repeating this sequence.

[0005] The architecture simulator is generally a high-speed simulator that sequentially executes instructions at the data transfer level in the order of program order, unlike a pipeline simulator or the like. The problem with simulating a multiprocessor system with the conventional method described above is that if the program on the architecture simulator issues a memory reference instruction, activates the logic simulator, and then sends a reply from the memory via the memory control logic. If a state of waiting for data occurs, the architecture simulator cannot execute the next instruction until the reply data returns. This means that the architecture simulator completes processing of one instruction in one simulation cycle without performing pipeline processing, and load use (the case where the target register data of the preceding load instruction is used in the subsequent instruction) occurs. If they do, they will malfunction.

As described above, in the conventional method, since the memory reference system request can be issued only in one shot, a continuous request sequence or a request contention state which gives a high load to the multiprocessor control and the cache memory control system logic. There was a problem that could not be generated. or,
There is a problem that only a simulation at a timing different from the actual system operation can be performed. Although there is a method of replacing the architecture simulator with a pipeline simulator and connecting it, a great deal of man-hour and development period must be spent on the development of the pipeline simulator itself. Further, the connection interface with the logic simulator becomes complicated, and the processing performance of the pipeline simulator itself is much lower than that of the architecture simulator, so that the logic simulation performance is abnormally reduced.

SUMMARY OF THE INVENTION An object of the present invention is to solve these conventional problems and to execute a logic simulation of a large-scale multiprocessor system or the like at high speed by applying a high load close to the actual operation without mounting a processor logical file. To implement.

[0008]

According to the present invention, a logic simulator for simulating a memory control logic at a gate level or a logic function level is linked with an architecture simulator for simulating an instruction execution at a data transfer level.
In a logic simulation that performs a logic simulation of a multiprocessor system or the like using a program that runs on a real machine, a plurality of instructions are cyclically executed by an architectural simulator under pseudo-precedence control, and a memory request is issued for a memory access instruction. A function to queue and transfer control to the logic simulator side is provided.

In order to perform exclusive control at the time of load use, the architecture simulator includes a pseudo register file with a tag indicating whether the register is valid or invalid. Causes the process to wait until the pseudo register becomes valid.

When the calculation of the memory access address of the memory access instruction is completed, the architecture simulator queues the memory request, invalidates the tag of the target pseudo register, and executes the memory access instruction. Upon completion, the reply data of the memory access instruction is received from the logic simulator side, and when the data is registered in the target pseudo register, the tag of the pseudo register is validated.

Further, the architecture simulator includes:
The memory requests registered in the memory request queue are randomly extracted in some cases in addition to the queuing order, and control is passed to the logic simulator side.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram illustrating a schematic configuration of an example of a system to be subjected to a logic simulation. This is an example of a so-called bus-type SMP configuration system, and the node (# 0) 200 stores the local memory (L
S # 0) 201, memory control logic unit (SC # 0) 20
2, the processor bus 203, and the processor bus 2
, A plurality of processors (IP # 0 to IP # i) (204) each having a cache connected thereto, and the node 200 has the same configuration via the memory control logic unit 202 as the node (# 1). 2 shows an example of a multiprocessor system connected to the multiprocessor system 210.

FIG. 3 is a diagram showing an example of an operation when a memory access operation occurs in the system of FIG. Now
When a memory read occurs in the processor (IP # 0) on the node (# 0) 200, and when the corresponding address is hit in the own cache, the corresponding data is read from the cache. The processor (IP) on the node (# 1)
If a data store occurs in #n) and the corresponding address does not hit in its own cache, a transaction of a memory store is issued to the bus 213, and the stored data is transferred to the local memory 211 via the memory control logic unit 212. Is written to. At the same time, node 210,
If another processor in 200 has the same cache address line (block), its own node 210
The request for canceling the corresponding cache line is sent to the other processor via the processor bus 213, and to the processor inside the other node 200 via the memory control logic units 212 and 202.
j, IP # i, etc.), and the corresponding cache line of the cache is invalidated by the corresponding processor.

According to the present invention, the operation in such a multiprocessor system is described by a logic simulation.
In the state where the processor logical file is not mounted, an operation state as close as possible to the actual machine is generated and verified.

FIG. 1 is a block diagram showing an embodiment of a logic simulation apparatus according to the present invention. The architecture simulator 100 includes a pseudo cache 101,
Pseudo address translation buffer (pseudo TLB) 102, valid / invalid pseudo register file 103 with tag, memory request queue 104, instruction processing unit 1 for executing instructions
05, and an instruction execution control unit 106 for controlling activation of the instruction processing unit 105 and the like. There are as many architecture simulators 100 as the number of nodes as shown in FIG. Also, one architecture simulator 1
In 00, the pseudo cache 101, pseudo TLB 102, tagged pseudo register file 103, and memory request queue 104 exist as many as the number of processors in the node. Note that the memory request queue 104 is actually built in the instruction execution control unit 106, but is externally shown in FIG. 1 for easy understanding.

The architecture simulator 100 is connected to a logic simulator 120 via a transaction control unit 110. Transaction control unit 110
Is responsible for bus transaction control such as data transmission / reception operations between the architecture simulator 100 and the logic simulator 120. Logic simulator 120
Is a cycle-based or event-driven circuit simulator that simulates logic at the gate level, or
This is a simulator that simulates the logic at the logical function level (here, these are collectively called a logic simulator), and the memory control logic 12 corresponding to the CS of each node.
1. A memory pseudo procedure 122 for accessing the pseudo memory 130 is mounted. Pseudo memory 130
Is divided into a plurality of areas corresponding to the LS of each node,
Instruction sequences and data that operate on the actual machine are stored.

Here, it goes without saying that the architecture simulator 100, the transaction control unit 110, the logic simulator 120 and the pseudo memory 130 shown in FIG. 1 are actually constructed on a computer.

FIG. 4 shows a pseudo register file 1 with a tag.
FIG. 3 is a diagram showing a configuration of the third embodiment. The register file 103
Is composed of a pseudo register 401 corresponding to each register included in the corresponding processor (IP), and a tag bit 402 indicating validity / invalidity of the pseudo register.

FIG. 5 is a diagram showing an example of the data structure of one entry of the memory request queue 104, which includes a virtual address, a real address, a data size, an addressing mode, a register type (general purpose register, floating point register, etc.), a register number, It includes a transaction type (read operation, write operation, etc.), a valid bit (valid / invalid of the entry), a next queue entry pointer, and the like.

As will be described later, the instruction processing unit 105
When the instruction is executed, the tag of the pseudo register used by the corresponding instruction in the pseudo register file 103 with the tag corresponding to the IP is checked. If the instruction is invalid, the process enters a waiting process until the target pseudo register becomes valid. At the time of caching, when the memory access address calculation of the memory access instruction is completed, a new entry is registered in the memory request queue 104 corresponding to the request IP, and the target pseudo register of the pseudo register file 103 with the tag corresponding to the IP is registered. The tag is invalidated, the execution of the memory access related instruction is completed at that point, and the process proceeds to the next instruction processing. On the other hand, the instruction execution control unit 106 activates the instruction processing unit 105, checks the memory request queue 104, extracts each IP request one entry at a time, and passes it to the transaction control unit 110. When the load reply data is received from the transaction control unit 110, the target line is registered in the pseudo cache 101 of the corresponding IP, and the data is written in the pseudo register registered in the target entry of the memory request queue 104 of the corresponding IP. , The tag is made valid, and the target entry of the memory request queue 104 is invalidated.

First, the overall operation of the present logic simulation apparatus will be described with reference to FIG. First, after performing a pseudo power-on reset of the system, the logic simulator 120 passes control to the transaction control unit 110 (), and the transaction control unit 110 passes control to the architecture simulator 100 corresponding to the node as it is, The instruction execution control unit 106 in the control unit 100 receives the control (), and the resources (the pseudo cache 101, the pseudo TLB 102, the pseudo register file with tag 103, the memory request queue 104)
Etc.). This is the initial sequence.

After the resources are initialized, the instruction execution control unit 10
6 activates the instruction processing unit 105 (). Start control is
It is executed multiple times during one simulation cycle. When the instruction processing unit 105 is activated by the instruction execution control unit 106, the instruction processing unit 105 processes the instruction.
The memory access request is registered in the memory request queue 104, and the process proceeds to the next instruction. Here, the command processing unit 105 executes each start control to execute each IP in the node.
Process one instruction each. This is repeated a plurality of times during one simulation cycle. This enables pseudo-precedence control.

On the other hand, when the activation of the instruction processing unit 105 is completed (), the instruction execution control unit 106 activates the transaction control unit 110 (). At this time, the instruction execution control unit 106 checks the memory request queue 104 and issues a memory request to the transaction control unit 110 when an entry is registered in the queue.
The transaction control unit 110 generates bus transaction data and activates the logic simulator 100 (). The logic simulator 100 accesses the pseudo memory 130 and returns control to the transaction control unit 110 (). The transaction control unit 110 activates the instruction execution control unit 106 () and passes the memory reply data. The instruction execution control unit 106 invalidates the corresponding entry in the memory request queue 104,
Then, the instruction processing unit 105 is started again after the writing to the pseudo-register file 103 with tag or the like is performed ().
Hereinafter, the processes (1) to (4) are repeated for each simulation cycle.

Next, the processing of the instruction processing unit 105, the instruction execution control unit 106, and the transaction control unit 110 will be described in detail. The processing of the logic simulator 120 is basically the same as the conventional one, and a description thereof will be omitted.

FIG. 7 is a flowchart showing the operation of one embodiment of the instruction processing unit 105, and corresponds to processing of one instruction. When acquiring the instruction execution address (step 700), the instruction processing unit 105 checks the tag of the pseudo cache 101 in the architecture simulator 100 and determines that the target instruction address line is
1 (step 70).
1). If not registered in the pseudo cache 101,
In order to issue an instruction line transfer request from the pseudo memory 130, a memory request queue entry is created (step 718), and the entry is registered in the memory request queue 104 (step 719). Pseudo cache 10
If the corresponding instruction line has already been registered in No. 1, the instruction at the target address is read from the pseudo cache 101 (step 702), and the operation code is analyzed (step 703). Next, it is determined whether or not the instruction is a memory access instruction (step 704). If the instruction is not a memory access instruction, each instruction simulating process is executed (step 70).
6). At this time, when the tag-added pseudo register file 103 is used, if the tag of the register is invalid, the process is suspended until the tag becomes valid.

In the case of a memory access instruction, the memory access address is calculated (step 705), the tag of the pseudo cache 101 is checked, and it is determined whether or not the data address line of the target operand is registered in the pseudo cache 101. (Step 707). If the data line has already been registered in the pseudo cache 101, the data at the target address is read from the pseudo cache 101 (step 708), and a flag indicating a cache hit (temporary flag) is set (step 70).
9). The corresponding data line is a pseudo cache 2101
If not, it is determined whether the target instruction is a store instruction (step 710). If the instruction is a store instruction, the storage target data is acquired from the tagged pseudo register file 103 (step 711). Also in this case, if the corresponding pseudo register tag is invalid, the processing is suspended until it becomes valid. If the store data has been acquired, it is determined whether or not the store target address has hit in the pseudo cache 101 (step 712). If hit, the store target data is written in the pseudo cache 101, and if necessary, the cache tag information Is updated (step 713), and the cache hit flag is reset (step 72).
0). If there is no cache hit in step 712, a memory request queue entry is created to issue a data line transfer request from the pseudo memory 130 (step 718), and the entry is registered in the queue 104 (step 719).

If a load instruction is determined in step 710, the number of a register to be a load target is obtained (step 714). Then, it is determined whether or not the target data is hit in the cache (step 715). If hit, the load target data is written in the tagged pseudo register file 103, and the target register tag is made valid (step 716). The hit flag is reset (step 720). Also in step 716, if the corresponding pseudo register tag is invalid, writing is suspended until it becomes valid. If there is no cache hit, the tag of the target register in the pseudo register file 103 is invalidated in order to issue a data line transfer request from the pseudo memory 130 (step 71).
7) The use of this pseudo register is suspended until the register data is determined. Further, a memory request queue entry is created (step 718), and the entry is registered in the queue 104 (step 719).

The instruction processing unit 105 repeats the above operation until the execution of the program is completed. In the case of a system with a multiprocessor configuration, the pseudo cache 101 and the pseudo TLB1
02, the pseudo register files 103 and the memory request queues 104 are prepared by the number of processors, and the instruction processing unit 105 cyclically executes the instruction processing of each processor in units of one instruction while switching these resources.

FIG. 8 is a flowchart showing the operation of the exclusive control in the instruction processing unit 105 according to an embodiment. When the instruction processing unit 105 decodes the instruction and obtains the register number used for the operation (step 800), the instruction processing unit 105 refers to the tagged pseudo register file 103 (step 801),
The corresponding register tag is checked (802). If the valid bit is set, the corresponding pseudo register data is obtained (step 802), and the operation is started (step 803). If the valid bit is not set, it waits for the register data until the valid bit is set. In the case of a load instruction, the writing of data is waited.

FIG. 9 is a flowchart showing the operation of the instruction execution control unit 106 when the instruction processing unit 105 is activated, according to one embodiment. The instruction execution control unit 106 receives control from the transaction control unit 110 and activates the instruction processing unit 105 (in FIG. 6). Usually, since there is a frequency difference between the processor bus and the processor, for example, one bus cycle is four times.
In the case of a processor cycle, the instruction processing unit 105 can be repeatedly activated four times. The instruction execution control unit 106 activates the instruction processing unit 105 (step 901), and repeats this for a predetermined number of times (step 902). Instruction processing unit 10
5 is completed, the transaction control unit 110
If the bus right acquisition IP number has been received at the time of booting from the server, it is acquired (step 903), and the memory request queue 104 of the processor corresponding to the IP number is acquired.
Is obtained (step 904). Then, it is checked whether or not an entry exists in the memory request queue 104 (step 905). If an entry exists in the memory request queue 104, it is checked whether or not the request is output in the programming order (step 906). If the request is in the programming order, the first entry stored in the queue is selected (step 907). In this case, an arbitrary entry is randomly extracted from the registered entries (step 908), and the local ID is used as an identifier when a reply to the transaction (memory request) is returned from the transaction control unit 110, and The corresponding entry is registered in the memory request queue 104 of the processor (step 909). When the queue is empty or when the registration of the local ID in the memory request is completed, the transaction control unit 110 is started (step 910).

FIG. 10 is a flowchart showing an embodiment of the operation when the instruction execution control unit 106 receives the control from the transaction control unit 110. When the instruction execution control unit 106 is started (FIG. 6), the corresponding processor number, local ID, reply address, data pointer, and the like are passed from the transaction control unit 110 (step 1000). The instruction execution control unit 106
If the local ID is 0, it is defined as a cache snoop request accompanying another processor request. Check this local ID (step 100
1) If the local ID is 0, a cache tag is searched from the reply address, and it is checked whether or not the corresponding address line exists in the cache 101 (step 10003). Invalidating the valid bit of the cache tag (step 100)
4).

If the local ID is other than 0, the target memory request queue 104 is selected from the processor number (step 1002), and the corresponding entry is searched using the local ID (step 1005). And
The cache tag pointer is read from the relevant entry, the valid bit of the relevant cache tag is set (step 1006), and the data is written to the relevant cache line (step 1007). Further, the corresponding register is determined from the register type and the register number, data is written to the corresponding pseudo register of the tagged pseudo register file 103 (step 1008), and an effective bit is set in the tag (step 1009). After all the processes are completed, the valid bit of the corresponding memory request queue entry is dropped and the entry is invalidated (step 1010).

FIG. 11 shows the transaction control unit 110.
6 is a flowchart showing an example of the data transmission / reception operation of the embodiment. When the control is returned from the instruction execution control unit 106 (FIG. 6), the transaction control unit 110 acquires a pointer of a corresponding memory request queue for generating a transaction (step 1100), and is registered in the queue entry. The bus transaction data is generated using the data (step 1101). Usually, since the transfer of a plurality of bytes is completed in a plurality of cycles, the bus transaction data is divided by the number of execution cycles (step 1102). Is added to the logic signal (step 1103), and the logic simulator 120 is started (step 1104). After executing one cycle of logic, the logic simulator 120 returns control to the transaction control unit 110. The transaction control unit 110 repeats the same operation until transmission of all transaction data is completed (step 110).
5).

The transaction control section 110 acquires transaction data from the bus (step 1).
106), the received data is converted into a programmable format (step 1107), and the same processing is repeated until all the same transaction data is obtained (step 1108). Then, after packing one transaction worth of data received in a plurality of cycles (step 1109), the instruction execution control unit 106 is activated with the data pointer as an argument (1110).

FIG. 12 is a block diagram showing another embodiment of the logic simulation apparatus according to the present invention. The architecture simulator 100 includes a pseudo cache 101, a pseudo TLB 102, a tagged pseudo register file 103, a memory request queue 104, an instruction processing unit 105, an instruction execution control unit 106, a transaction control unit 110, and a pseudo memory 130. This is suitable for logic simulation of a single-node multiprocessor system. The operation of this embodiment is basically the same as that of FIG.

[0036]

According to the present invention, a system simulation of a multiprocessor or parallel processor configuration far exceeding the logic implementation restrictions of a logic simulator can be performed at high speed in a state close to actual operation by pseudo-preceding control. It becomes possible. Further, since a system simulation can be performed without a processor logical file, it is particularly effective for advanced development of a system using a mass-produced processor chip.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a logic simulation apparatus according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a system to be simulated;

FIG. 3 is a diagram showing an example of a memory access system operation of the system of FIG. 2;

FIG. 4 is a diagram showing a configuration example of a pseudo register file with a tag.

FIG. 5 is a diagram illustrating an example of a data structure of a memory request queue.

FIG. 6 is a sequence diagram for explaining the overall operation of FIG. 1;

FIG. 7 is an operation flowchart of an embodiment of an instruction processing unit.

FIG. 8 is an operation flowchart of an embodiment of exclusive control of an instruction processing unit.

FIG. 9 is an operation flowchart of an embodiment according to activation of the instruction processing unit of the instruction execution control unit.

FIG. 10 is an operation flowchart of an embodiment according to activation of the instruction execution control unit from the transaction control unit.

FIG. 11 is a flowchart showing one embodiment of a data transmission / reception operation of the transaction control unit.

FIG. 12 is a block diagram showing another embodiment of the logic simulation apparatus according to the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 architecture simulator 101 pseudo cache 102 pseudo TLB 103 pseudo register file with tag 104 memory request queue 105 instruction processing unit 106 instruction execution control unit 110 transaction control unit 130 pseudo memory 120 logic simulator 121 memory control logic 122 memory pseudo processor

Claims (4)

[Claims] An apparatus for performing a logic simulation of a processor system using a program operating on a real machine by linking a logic simulator for simulating memory control logic and an architecture simulator for simulating instruction execution at a data transfer level. The architecture simulator has a function of cyclically executing a plurality of instructions by pseudo-preceding control, queuing a memory request for a memory access instruction, and passing control to the logic simulator side. Logic simulation device. 2. The logic simulator according to claim 1, wherein the architecture simulator includes a tagged pseudo-register file indicating whether the register is valid or invalid, and checks a pseudo-register tag used by the target instruction, and determines whether the register is invalid. Is a logic simulation apparatus which starts waiting until the pseudo register becomes valid. 3. The logic simulator according to claim 2, wherein the architecture simulator queues the memory request when the calculation of the memory access address of the memory access instruction is completed, and invalidates the tag of the target pseudo register. When the execution of the memory access instruction is completed, the reply data of the memory access instruction is received from the logic simulator, and the data is registered in the target pseudo register, the tag of the pseudo register becomes valid. Logic simulation device. 4. The logic simulator according to claim 1, wherein the architecture simulator comprises:
A logic simulation device characterized by randomly extracting a memory request registered in a memory request queue and transferring control to a logic simulator side.