JP2000250665A - Semiconductor integrated circuit and memory card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent unnecessary power consumption resulting from a halfway operating power source and malfunction when an external power source is inadequate to the operation guarantee voltage of the semiconductor integrated circuit. SOLUTION: An interface control circuit 2 inputs information (supply voltage range information) showing the range of a source voltage (Vcc) supplied to itself from outside and decides whether or not the voltage range specified by the information meets the operation guarantee voltage and when not, signal input to and output from the outside are cut off. Consequently, the semiconductor integrated circuit does not respond to an external signal, internal nodes of the circuit are placed almost in an electrically fixed state, and even if the external power source is inadequate to the operation guarantee voltage of the semiconductor integrated circuit, malfunction of the semiconductor integrated circuit due to the operating power source of halfway level is prevented to reduce unnecessary power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
In addition, the present invention relates to a memory card such as a file memory, and to a technology effective when applied to a memory card having a file memory function mounted on one chip, for example.

[0002]

2. Description of the Related Art Since a semiconductor integrated circuit is unstable in operation from the time when operating power is turned on until a specified operation assurance voltage is reached, the semiconductor integrated circuit is reset in response to the turning on of the operating power, and after a certain period of time. Operation is enabled only after the reset state is released. In the reset state, the semiconductor integrated circuit is initialized, and a predetermined input / output operation is prohibited. The instruction of the reset state and its release can be performed by a reset signal supplied from the outside, or can be independently performed by detecting the power supply voltage level by itself.

Further, a semiconductor integrated circuit applied to a device detachable from a host system, such as an IC card or a PC card, can be supplied with operating power from the host system via an interface or a connector. it can.

The reset of the semiconductor integrated circuit is described in, for example, "8086 Microcomputer (Microcomputer Series 15, Maruzen Co., Ltd., December 1986)
On page 34 of the PCMCIA-ATA flash memory card, which is one of the PC cards.
(Published April 11, 4)) on pages 78 and 79.

[0005]

First, the present inventors have studied the operating voltage and power-on reset of a semiconductor integrated circuit. According to this, when the number of types of circuits increases in a semiconductor integrated circuit formed on one semiconductor substrate, it may not be necessary to make the operation guarantee voltages of all the circuits the same. For example, the operating voltage of an electrically rewritable nonvolatile memory often requires a relatively high operating voltage due to its memory cell structure. In a logic circuit in which data is transmitted via a static latch circuit that is completely synchronized with a clock signal, low-voltage operation is easy because of its static operation. Among the logic circuits, in a circuit that requires a dynamic operation of a data transmission system or the like, there is a limit to the low-voltage operation in order to secure a certain operation speed. As described above, in some cases, the minimum operation guarantee voltage of some circuits may be low depending on the functions or types of circuits mounted on one chip. In this case, after the power-on reset, after waiting for a lapse of time for the power supply voltage to reach the operation guarantee minimum voltage of a relatively high level, if the reset state of the entire semiconductor integrated circuit is released, a malfunction due to the power supply voltage shortage may occur. There is no danger. However, it has been clarified by the present inventor that in some cases inconvenience may occur unless the reset state of the part is released while the state in which the operation voltage of some circuits can be satisfied is achieved. That is, when the operation assurance voltage of a circuit that receives an external instruction and returns a response in an initialization operation after the release of a power-on reset is relatively low, power is supplied at least to such an extent that the circuit can operate. Then, the reset state of only the circuit can be partially released, and a response to the outside can be returned. It is desirable to do so in order to stabilize the operation of the system. This is because the host device must determine whether or not there is no response to the no-response, and the semiconductor integrated circuit that maintains the reset state without any response also wastes power.
For example, when operating power is supplied from the host device to the semiconductor integrated circuit of the terminal device, the semiconductor integrated circuit of the terminal device returns determination information as to whether or not the supplied power matches the operation assurance voltage to the host device. A simple system can be assumed.

Second, the inventor has studied how to deal with a case where the external power supply is incompatible with the operation guarantee voltage of the semiconductor integrated circuit. According to this, even if the functions of the semiconductor integrated circuits are the same, the operating voltage may be different depending on the manufacturer and the type of the product. It is not realistic to cover the entire operating voltage range in a data processing system that is supposed to arbitrarily use such semiconductor integrated circuits having different operating voltages. For example, it is configured by a host device and a terminal device or a peripheral device using a semiconductor integrated circuit that is detachable from the host device and is supplied with operating power from the host device via an interface portion or a connector portion. Data processing system. In such a data processing system, when the operating voltage range of the semiconductor integrated circuit does not match the operating voltage range covered by the host device,
The inventor has clarified the necessity of preventing a malfunction of a semiconductor integrated circuit or a peripheral device due to a supply of an operation power supply at an incomplete level and suppressing unnecessary power consumption.

[0007] From the viewpoints of malfunction prevention and low power consumption, which are the second issues to be considered, when a host device uses attribute information held by a semiconductor integrated circuit or a peripheral device for control, there is an abnormality in the attribute information. The present inventors have clarified that the same applies to the case where control by the host device becomes impossible.

An object of the present invention is to provide a semiconductor integrated circuit capable of operating a circuit portion operable with a low power supply even when a power supply lower than a required operation guarantee voltage is applied as a whole. Is to do.

Another object of the present invention is to provide a semiconductor integrated circuit which can respond to an external instruction even when only a power supply lower than a required operation guarantee voltage is supplied as a whole.

[0010] Still another object of the present invention is to provide a semiconductor integrated circuit in which a circuit that responds to an external instruction in an initialization operation or the like can be made operable after power-on, as compared with other circuits. Is to provide.

Still another object of the present invention is to provide a semiconductor integrated circuit capable of preventing a malfunction due to a half-level operation power supply when an external power supply is incompatible with an operation guarantee voltage of the semiconductor integrated circuit. To provide.

Still another object of the present invention is to provide a semiconductor device capable of reducing wasteful power consumption due to a half-level operation power supply when an external power supply is incompatible with an operation guarantee voltage of a semiconductor integrated circuit. It is to provide an integrated circuit.

Still another object of the present invention is to provide a memory card using a semiconductor integrated circuit which is detachable from a host device and which is supplied with operating power from the host device via an interface portion or a connector portion. Provided is a memory card capable of detecting whether an operation guarantee voltage range is compatible with an operation voltage range covered by a host device, preventing a malfunction due to an incomplete level of operation power supply, and reducing unnecessary power consumption. Will be.

Another object of the present invention is to provide a semiconductor integrated circuit which does not consume useless power even when the host device cannot be controlled due to an abnormality in attribute information used for controlling the host device. It is in.

Still another object of the present invention is to control a host device in a memory card using a semiconductor integrated circuit which is detachable from a host device and is controlled by the host device via an interface portion or a connector portion. An object of the present invention is to provide a memory card capable of detecting an abnormality in attribute information provided to the user, and realizing reduction of useless power consumption and prevention of malfunction even if the abnormality causes control from the host device to become impossible. .

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

<< Two-Step Reset Operation >> A semiconductor integrated circuit (1) is connected to a first circuit (2) having an external interface function and is connected to the first circuit and has a lower operation guarantee voltage than the first circuit. Circuit and a third circuit (5) for instructing the first and second circuits to reset in response to turning on of an external power supply (Vcc) on a single chip. Including. The third circuit instructs the first circuit to release a reset state when the external power supply voltage exceeds a first voltage (VR1), and the external power supply voltage has a higher level than the first voltage. When the voltage exceeds the second voltage (VR2), the second circuit is instructed to release the reset state. By the two-step reset operation, the timing at which the circuit portion (2) having a lower operation guarantee lower limit voltage, which can originally operate quickly after the operation power supply is turned on, can be operated earlier than other circuits. Even if the power supply voltage required for the entire semiconductor integrated circuit does not reach the required power supply voltage, only the circuit portion having such a low operation guarantee lower voltage can be made operable.

The reset state is a state in which a predetermined operation of the circuit is prohibited from the viewpoint of preventing a malfunction until the reset is released. Is initialized, and either or one of the states can be adopted as necessary. Preferably, both states are realized.

The first circuit (2) may employ a configuration capable of performing an output operation in response to an instruction (voltage range confirmation command) input from outside before the reset state of the second circuit is released. it can. Thereby, even when only a power supply lower than the required operation guarantee voltage is supplied as a whole, it is possible to respond to an external instruction, and it is possible to minimize the state of no response to the external instruction.

Information (supply voltage range information) indicating the range of the external power supply voltage is externally input to the first circuit, and the voltage range specified by the information satisfies the operation guarantee voltage of the semiconductor integrated circuit. A configuration for determining whether or not the determination may be adopted. In addition, the first circuit receives information (operation assurance voltage range information) indicating an operation assurance voltage range of the semiconductor integrated circuit in response to externally inputting information indicating an external power supply voltage range. A configuration for outputting to the outside may be adopted. The semiconductor integrated circuit (1) adopting this configuration is mounted on a memory card that is detachable from the host device (100) and that is supplied with operating power (Vcc) from the host device via an interface or a connector. Can be applied. Then, when the power is supplied from the host device, the semiconductor integrated circuit can detect whether or not the operating voltage range is compatible with the operating voltage range covered by the host device. Can be returned to the host device. At this time, if only the operation assurance voltage of the first circuit that returns the range of the operation assurance voltage required by the semiconductor integrated circuit to the host device is satisfied, only the first circuit is released from the reset state, and the external circuit operates. A response in the guaranteed voltage range can be returned. Therefore, it is possible to eliminate the non-response to the host device as much as possible and to stabilize the operation of the system. Rejection of a non-response state to the host device will be described in more detail. For example, assume a system in which a plurality of the semiconductor integrated circuits applied to a memory card are mounted on a host device via a common signal line and used. In the power-on reset of this system, each semiconductor integrated circuit outputs information of a unique operation assurance voltage range to a common signal line (signal lines for data 2C and command 2B) in parallel, and the information is logically output on the common signal line. The product is taken and input to the host device. Therefore, if all the semiconductor integrated circuits operate, the host device can first recognize the common voltage range that satisfies the operation guarantee voltage of each semiconductor integrated circuit. Therefore, the host device can first determine the range of the power supply voltage required to normally operate at least one of the plurality of semiconductor integrated circuits connected this time, or, among the plurality of semiconductor integrated circuits, First, it can be determined whether or not a power supply voltage required to operate at least one normally can be supplied. For that purpose, it is necessary that all the semiconductor integrated circuits can return the information of the operation guarantee voltage range to the host device. Therefore, in consideration of the power supply capability of the host device, it is necessary to consider the information of the operation guarantee voltage range so that a response can be returned even if the necessary operation power is not finally obtained.
From this point of view, stabilization of the system operation is realized by releasing the reset of the circuit operable with the relatively low operation power supply and returning the information on the operation guarantee voltage range to the host device. Further, in the system, if a predetermined voltage equal to or higher than the minimum voltage of the power supply standard of the host device is set as the reset release voltage of the first circuit, a circuit whose operation guarantee lower limit voltage is slightly higher than that is regarded as a second circuit. Even if it is adopted, it is possible to prevent a problem in the system.

The first circuit can shut off signal input / output with the outside when the judgment result does not satisfy the operation guarantee voltage. Thereby, the semiconductor integrated circuit is
Malfunction due to the supply of an incomplete level of operation power can be prevented, and wasteful power consumption can be reduced.

[0023] The semiconductor integrated circuit may further include a fourth circuit (4) connected to the first circuit and having a lower operation guarantee voltage than the first circuit. At this time,
As a first aspect of the reset operation for the fourth circuit (FIG. 14), the third circuit instructs the fourth circuit to be in a reset state in response to turning on an external power supply, and the external power supply voltage is When the voltage exceeds the second voltage, the fourth circuit can be instructed to release the reset state. Thus, the reset state of the fourth circuit can be automatically released together with the second circuit path.

As a second aspect of the reset operation for the fourth circuit (FIG. 13), the second circuit instructs the fourth circuit to reset in response to its own reset state, The reset state of the fourth circuit can be released in response to the release of its own reset state. According to this, since the reset state of the fourth circuit is performed by the second circuit whose reset state has been released and which has become operable, the possibility that the reset state of the fourth circuit is released by mistake is reduced. it can. If the fourth circuit is exclusively a memory for storing information, the possibility of undesired destruction of stored information can be reduced.

As a third mode of the reset operation for the fourth circuit (FIG. 12), the first circuit further instructs the fourth circuit to a reset state in response to its own reset state. The second circuit can further instruct the first circuit to release the reset state of the fourth circuit in response to the release of the reset state of itself. In this operation mode, similarly to the second mode, the reset state of the fourth circuit is released by the second circuit released from the reset state and made operable. The possibility that the reset state is released can be reduced.

In particular, in the third aspect, the first circuit further includes a reset state release for the fourth circuit while the third circuit indicates the reset state to the second circuit. Can be suppressed. Thereby, the second
A situation in which the reset state of the fourth circuit is erroneously released before the reset state of the circuit is released can be more strictly prevented.

Assuming that the above-mentioned semiconductor integrated circuit is applied to a memory card which is detachable from a host device and supplied with operating power from the host device via an interface portion or a connector portion, for example,
For example, the first circuit is an interface control circuit (2), the second circuit is a microcomputer (3), the third circuit is a reset circuit (5), and the fourth circuit is electrically rewritable. Nonvolatile memory (4)
It can be. At this time, the microcomputer has an instruction execution function and can manage the arrangement of file data in the nonvolatile memory, and the interface control circuit has an interface function with the outside and receives a command from the outside and The microcomputer controls instruction execution by the microcomputer and controls access to the nonvolatile memory. More specifically, the interface control circuit accepts a command from the outside, instructs the operation of the microcomputer and the nonvolatile memory, and performs access control of file data to the nonvolatile memory. The microcomputer controls generation and update of a management table for managing an array of file data in a management unit area of the nonvolatile memory, and uses the management table to access the interface control circuit using the management table when accessing file data. Is specified.

<< Voltage Range Abnormality Detection >> The semiconductor integrated circuit (1) from the viewpoint of voltage range abnormality detection indicates the range of the power supply voltage supplied to itself (supply voltage range information).
Is externally input, and it is determined whether or not the voltage range specified by the information satisfies the operation guarantee voltage. If the operation guarantee voltage is not satisfied, signal input / output with the outside is shut off.

More specifically, the semiconductor integrated circuit has an interface control circuit (2) and an internal circuit. The interface control circuit inputs information indicating the range of the power supply voltage from the outside, and is specified by the information. It is determined whether or not the voltage range satisfying the operation guarantee voltage of the semiconductor integrated circuit. If the operation guarantee voltage is not satisfied, signal input / output with the outside is shut off. From another viewpoint, the interface control circuit inputs information indicating the range of the power supply voltage from the outside, and a voltage common to the voltage range specified by the information and the range of the operation assurance voltage of the semiconductor integrated circuit. It is determined whether or not the signal exists, and when the result of the determination is that there is no common voltage, signal input / output with the outside is shut off.

The interruption of the signal input / output with the outside can be performed, for example, by using an input buffer (Bi
n) can be realized by increasing the input impedance and increasing the output impedance of the output buffer (Bout) interfaced to the outside.

Due to the interruption of the signal input / output to / from the outside, the semiconductor integrated circuit does not respond to the signal from the outside, and the internal nodes of the circuit are substantially in an electrically fixed state, and the operation assurance voltage of the semiconductor integrated circuit is maintained. However, even if the external power supply is incompatible, it is possible to prevent the semiconductor integrated circuit from malfunctioning due to the half-level operation power supply. Further, wasteful power consumption due to the operation of the semiconductor integrated circuit in response to a half-level operation power supply can be reduced.

The internal circuit includes a microcomputer (3), and the interface control circuit can instruct the microcomputer to enter a standby state when the input / output is cut off. As a result, the operation of the microcomputer can be completely suppressed, and reduction of wasteful power consumption can be promoted.

When the internal circuit has an electrically rewritable nonvolatile memory (4), the operation of the nonvolatile memory is prohibited when the input / output is cut off, thereby protecting the stored information and preventing the operation of the nonvolatile memory. This can contribute to both reduction in power consumption.

In the interface control circuit, a non-volatile storage means (261) for generating information indicating a range of operation-guaranteed voltage of the semiconductor integrated circuit, and a register means for holding information indicating a range of an externally supplied power supply voltage (260)
And comparison means (AND, OR) for comparing the value generated from the nonvolatile storage means with the value of the register means, and the comparison means can detect an abnormality in the operating voltage. Thus, the abnormality of the operating voltage can be detected only by operating the interface control circuit.

In response to the information indicating the range of the external power supply voltage being input from outside, the interface control circuit stores information indicating the range of the operation guarantee voltage of the semiconductor integrated circuit (operation guarantee voltage range information). It can be output to the outside. As described in the two-stage reset operation, in a system in which a plurality of the semiconductor integrated circuits applied to a memory card or the like are commonly connected to a host device, at the time of a power-on reset,
The range of the power supply voltage required to operate at least one of the plurality of semiconductor integrated circuits normally is determined in advance, or necessary to operate at least one of the plurality of semiconductor integrated circuits normally. It is useful to determine in advance whether a suitable power supply voltage can be supplied.

Assume that the semiconductor integrated circuit is applied to, for example, a memory card that can be attached to and detached from a host device and supplied with operating power from the host device via an interface portion or a connector portion.
As described above, the semiconductor integrated circuit includes an interface control circuit (2), a microcomputer (3), and an electrically rewritable nonvolatile memory (4). At this time, when the power is supplied from the host device, the semiconductor integrated circuit detects whether or not the operating voltage range is compatible with the operating voltage range covered by the host device. Block input. Therefore, the memory card can realize both the malfunction prevention by the half-level operation power supply and the reduction of useless power consumption.

<< Attribute Information Abnormality Detection >> The semiconductor integrated circuit (1) from the viewpoint of attribute information abnormality detection includes a storage unit (4).
And data processing means (2, 3). The data processing means sets an inactive mode when detecting an abnormality in the attribute information held in the storage means, and releases the mode in the inactive mode. To disable external command input except for specific command input. At this time, the specific command is, for example, a command for setting the attribute information in a writable state or a command for writing the attribute information. Such a write command can be used for an initial operation of writing attribute information to a semiconductor integrated circuit, and the like.

Another semiconductor integrated circuit from the viewpoint of attribute information abnormality detection has a storage means and a data processing means, and the data processing means detects an abnormality in the attribute information held in the storage means. , And cuts off signal input / output with the outside except for a specific input. At this time, the specific input is, for example, a predetermined signal input state to a predetermined external terminal. The specific input is used to release an input cutoff state to enable an initial operation of writing attribute information to the semiconductor integrated circuit.

The attribute information is ID information of the semiconductor integrated circuit or characteristic information of the semiconductor integrated circuit. The ID information is, for example, code information specific to the semiconductor integrated circuit, and the characteristic information is, for example, information such as a storage capacity of the storage unit and an access speed. The abnormality in the attribute information can be information absence or data destruction. The data destruction can be performed, for example, by using ECC (Erro) added to the attribute information.
r Correcting Code) cannot be corrected.

As described above, it is possible to reduce unnecessary power consumption of the semiconductor integrated circuit which enters an uncontrollable state due to an abnormality in attribute information used for control or the like by the host device. At this time, the initial write operation of the attribute information is guaranteed by the write command and the specific input.

As the data processing means, an interface control circuit (2) for interfacing with the outside and a microcomputer (3) connected to the interface control circuit can be adopted. At this time, the interface control circuit performs the inactive mode setting or the signal input / output cutoff control.

In order to further reduce the power consumption in the inactive mode, the interface control circuit instructs the microcomputer to enter a standby state in response to the inactive mode and responds to the input of the specific command. A configuration in which the standby state of the microcomputer is released can be employed. Further, the interface control circuit stops the clock supply to the microcomputer in response to the inactive mode, restarts the clock supply to the microcomputer in response to the input of the specific command, and causes the microcomputer to A configuration for requesting an interrupt to start processing for executing a specific command can be adopted.

Similarly, in order to reduce the power consumption even in the signal input / output cutoff state with the outside, the interface control circuit instructs the microcomputer to enter a standby state in response to the input cutoff, A configuration in which the standby state of the microcomputer is released in response can be employed. Further, the interface control circuit stops the clock supply to the microcomputer in response to the input cutoff, restarts the clock supply to the microcomputer in response to the specific input, and causes the microcomputer to supply the specific input to the microcomputer. A configuration that requests an interrupt to execute a response process can be employed.

If the above semiconductor integrated circuit is applied to a memory card which is detachable from a host device and is controlled or accessed from the host device via an interface portion or a connector portion, the memory card becomes In addition, it is possible to detect an abnormality in attribute information used for control by the host device, and to reduce unnecessary power consumption and prevent malfunction in a state in which control is not possible due to the abnormality.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS << Outline of Memory Card LSI >> FIG. 1 shows a semiconductor integrated circuit for a memory card according to an example of the present invention. The semiconductor integrated circuit shown in FIG. 1 is not particularly limited, but is a system-on-chip LSI (semiconductor integrated circuit) constituting a minimum unit of a file memory.
And is formed on one semiconductor substrate (chip) such as single crystal silicon.

A semiconductor integrated circuit (also simply referred to as a memory card LSI) 1 shown in FIG. 1 is an example of an interface control circuit 2, a microcomputer 3 as an example of a data processing device, and an electrically rewritable nonvolatile memory. A flash memory 4, a reset circuit 5, a clock oscillation circuit 6 using a vibrator, a buffer RAM 7, and a work RAM 8 are provided.

The memory card LSI1 externally receives a power supply voltage Vcc and a ground voltage Vss as operating power supplies. The input power supply voltage Vcc and ground voltage Vss are supplied to the above circuits.

The interface control circuit 2 includes a host interface circuit (host I / F) 11 and a microcomputer interface (microcomputer I / F)
/ F) 12, File control logic (FCL)
13 and a data transfer logic (DTL) 14.

The host interface circuit 11 receives a clock signal (Clock) 2A and a card select signal (Card Select) 2D from the outside, and outputs a command (Command) 2B and data (Data) 2C.
Input and output. Although not particularly limited, the command 2B,
The data 2C is input / output in a bit serial manner. The host interface circuit 11 receives a command 2B supplied from the outside, decodes the command 2B, instructs the operation of the microcomputer 3 and the flash memory 4, and performs access control of file data to the flash memory 4.

The operation of the microcomputer 3 is instructed by giving an interrupt signal NMI and an interrupt factor to the microcomputer 3 from the host interface circuit 11 via the microcomputer interface 12. The microcomputer interface 12 exchanges various data such as the interrupt signal NMI, the control signal Ctl, and data information and control information with the microcomputer 3.

The file control logic 13 controls file data access to the flash memory 4 in accordance with the control of the microcomputer 3 or in accordance with the result of command decoding by the host interface circuit 11. The buffer RAM 7 is a file data buffer memory for temporarily storing file data externally supplied to the host interface circuit 11 or temporarily storing file data read from the flash memory 4. Access control to the buffer RAM 7 is performed by the data transfer logic 14. The data transfer logic 14 has an ECC circuit 14A, and performs EE generation for file data, and error checking and correction by ECC when accessing the buffer RAM 7. In the write operation of the file data, the file data is read from the buffer RAM 7 to the bus 10 by the data transfer logic 14, and the read file data is written to the flash memory 4 under the control of the file control logic 13. In the read operation of the file data, the file data is read from the flash memory 4 to the bus 10 under the control of the file control logic 13, and the read file data is written to the buffer RAM 7 under the control of the file transfer logic.

Although not particularly limited, the file memory LS
I1 has a file data access method compatible with the hard disk device. For example, one cluster as an access management unit area includes four sectors, and a management area is allocated to each class. The management area holds pointer information for determining the arrangement of the clusters constituting the file, information on the number of rewrites, information on whether the sector is good or bad, and the like. Further, the flash memory 4 has a directory area for specifying a file name of a storage file and a leading cluster thereof.

The microcomputer 3 generates a management table in the built-in SRAM 35 based on the information of the management area and the directory area in order to manage the arrangement of the file data for the cluster of the flash memory 4. The microcomputer 3 controls generation and updating of the management table, and generates information indicating a management unit area to be accessed using the management table when accessing file data. The access control information of the file data is given to the file control logic 13 via the microcomputer interface 12.

The microcomputer 3 includes a central processing unit (CPU) 30 connected to an internal bus 38,
Built-in ROM storing operation program of PU30
(Read only memory) 34, built-in SRAM (static random access memory) 35 used as a work area or a temporary data storage area of the CPU 30, and an external bus when the CPU 30 accesses an external address space. It has a bus controller (BSC) 33 for controlling 37 bus cycles and a user break controller (UBC) 31 for supporting debugging such as breakpoint control. Interrupt control circuit (I
The NTC 32 inputs an interrupt signal NMI and an interrupt cause, performs priority control on the interrupt, and requests the CPU 30 to issue an interrupt. Although not particularly limited, the interrupt processing program is stored in the built-in ROM 34.

The external bus 37 of the microcomputer 3 is connected to a watch dog timer (WDT) 36 for monitoring the runaway of the CPU 30 in addition to the bus controller 33. Connected by The microcomputer 3 has one I / O port 39A as another interface circuit. This I / O port 39A is dedicated to input of an interrupt signal NMI and output of a control signal represented by Ctl. Although not particularly limited, a general-purpose I / O port is not provided.

The microcomputer 3 has a sleep mode and a standby mode as low power consumption modes, although not particularly limited. The CPU 30 shifts to the sleep mode by executing the sleep command when the standby control bit provided in the control register (not shown) has the first logical value. When transitioning to the sleep mode, the CPU 30 stops the operation while maintaining the state of the register and the like. Peripheral circuits continue to operate. The sleep mode is released by an interrupt or a reset. On the other hand, when the standby control bit provided in the control register has the second logical value, the CPU 30 executes the sleep command to shift to the standby mode. When the CPU 30 transitions to the standby mode, the CPU 30 stops the operation while maintaining the state of the register and the like, and also stops the operation of the peripheral circuits. The standby mode is released by an interrupt or a reset.

The clock pulse generator 39 B of the microcomputer 3 supplies the clock signal C
LK2 is supplied. For example, when the microcomputer 3 is set in the standby mode, the oscillation circuit 6 stops outputting the clock signal CLK2 by a signal output from the microcomputer 3 in response to the standby mode.
In this state, the port 39 is connected to the microcomputer interface 12.
When the interrupt signal NMI is asserted at A, the clock control circuit 15 detects the state. Thereby, the clock control circuit 15 sends the clock signal CL to the oscillation circuit 6.
The supply of K2 is restarted. Therefore, when the CPU 30 responds to the interrupt, the clock signal CLK2
Supply has been resumed, the microcomputer 3
Can get out of standby mode.

The reset circuit 5 outputs a reset signal RE
S1 resets the interface control circuit 2,
The microcomputer 3 is reset by the reset signal RES2.
Reset. The reset operation of the flash memory 4 is performed by a reset enable bit R provided in a control register in the file control logic (FCL) 13.
This is performed by a reset signal RES3 controlled according to the value of SB.

FIGS. 2 and 3 show the memory card LSI1.
An example of a data processing system using is shown. Although not shown, the memory card LSI1 is packaged by a technique such as resin molding with the connector exposed.
100 is a host system, and 101 is a slot for installing a memory card. 2 and 3 illustrate a configuration in which a plurality of memory cards LSI1 can be mounted at one time.
In both cases, the signal lines for the clock 2A, command 2B, and data 2C are common to each memory card LSI1. In the example of FIG. 2, the card selection signal 2D unique to each memory card LSI 1 is used for card selection for a plurality of mounted memory cards LSI1, and in the example of FIG. It uses a card address. In the example of FIG. 3, the memory card LSI 1 recognizes that the memory card LSI 1 has been selected by inputting the card address allocated thereto in the initialization operation.

<< Operation Mode of Memory Card LSI >> The memory card LSI 1 is supplied with an operating power supply Vcc and a ground voltage Vss from a host device 100 as shown in FIGS. 2 and 3, and the host device 100 is Data 2C and command 2B via the interface circuit 11
Is interfaced, but only after a predetermined sequence has the memory card L
Recognized as SI1. The predetermined sequence is a voltage range abnormality detection operation and an attribute information abnormality detection operation. The voltage range abnormality detection operation is performed at power-on reset. Before describing these in detail, first, the operation mode of the memory card LSI 1 and the host interface circuit 11 that controls the operation mode will be described.

FIG. 4 shows the host interface circuit 1
1 is shown. According to FIG. 4, the host interface circuit 11 includes a command input register 20 for inputting a command 2B, a response control circuit 21 for returning a response to the command input, a data input register 22 for inputting data 2C, and a data for outputting data 2C. It has an output register 23. The input command is decoded by the command decoder 24, and the control logic circuit 26 performs interrupt control for the microcomputer 3, data input / output control, response control to the host device, the voltage abnormality detection operation, and the like according to the result of the decoding. Reference numeral 27 denotes a temporary storage memory used by the control logic 26.

The host interface circuit 11 has a state machine (state transition control logic circuit) for a command in the control logic circuit 26. FIG. 5 shows an example of a command that can be received by the memory card LSI1. In the command shown in FIG. 5, a command class is defined for each command code. The state machine controls transition of a command class of a command that can be accepted according to a state. As shown in the state transition control diagram of FIG. 6, the states to be transitioned are roughly divided into an initialization state ST1, an inactive state ST2, a debug state ST3, and an access state ST4 starting from a power-on reset. The command classes belonging to each state are as described in FIG. For example, in the debug state, only commands of the debug class can be accepted by the control logic circuit 26.

In the example shown in FIG. 5, the command code is 8 bits. For example, the initialization class includes commands for soft reset, voltage range confirmation, card ID confirmation, and card address setting. Necessary control data follows the command code. For example, the voltage confirmation command is accompanied by supply voltage range information indicating a range of a power supply voltage that can be supplied by the host device. A card address to be set in the memory card accompanies the card address setting command. The card address setting command is a command for setting a card address in each memory card LSI1 in the system of FIG.

The card ID confirmation command is transmitted from the memory LSI
Is a command for causing the host interface circuit 11 to output a card ID, which is one of the attribute information held by the host interface circuit 11.

The card information class includes a card ID read command and a characteristic information read command. The card ID read command is a command for internally transferring a card ID, which is one of the attribute information held by the memory LSI, from the flash memory 4 to the interface control circuit 11. This card ID read command is a significant command in the system of FIG. The characteristic information read command is a command for internally transferring characteristic information, which is another attribute information held by the memory LSI, from the flash memory 4 to the interface control circuit 11. The characteristic information is, for example, information such as the storage capacity of the flash memory and the access speed. The card ID and the characteristic information read from the flash memory 4 are stored in the temporary storage memory 27. By configuring the temporary storage memory 27 by a nonvolatile memory such as a flash memory, the card ID and the characteristic information can be stored in the memory 27 in advance.
Can be stored.

The read sector class includes a one-sector read command and a burst read command. The write access class includes one sector write, burst write,
Each command of erasure is included. The debug class includes a debug permission command, a vendor command, and the like. The vendor command includes a command for writing the attribute information of the flash memory 3 (attribute information write command).

As is clear from the transition control diagram of FIG. 6, after the power-on reset, unless the card address setting command is executed in the initialize state, the state does not transition to the access state. In the access state, the state can be changed to the debug state by executing the debug permission command. The inactive state is a state in which command reception is rejected except for the debug permission command. The inactive state is a state that is changed from the initialization state when an abnormal state due to a voltage range abnormality detecting operation and an abnormal state due to an attribute information abnormality detecting operation are detected. As for the relationship between the command and the interrupt to the microcomputer 3, as shown in FIG. Will be. The debug class command can output an interrupt to the microcomputer 3 even in the inactive state.

The state transition control diagram shown in FIG. 6 is applied to the system shown in FIG. In the state transition control in the memory card LSI 1 used in the system configuration of FIG. 2, the transition condition from the initialization state to the access state in FIG. 6 is the completion of the execution of the voltage range confirmation command. Further, the memory card LSI 1 used in the system configuration of FIG. 2 does not need to support the commands of card ID confirmation, card address setting, and ID reading.

<< Voltage Range Abnormality Detection >> The voltage range abnormality detecting operation will be described in detail. When the host interface circuit 11 receives the voltage check command in the initialization class, the host interface circuit 11 indicates information indicating an operation guarantee voltage range of the memory card LSI 1 (operation guarantee voltage range information).
Is sent from the response control circuit 21 to the signal line of the command 2B in association with the command code 01H. Along with this response operation, the host interface circuit 11 determines whether the voltage range specified by the supply voltage range information sent along with the voltage confirmation command satisfies the operation guarantee voltage of the memory card LSI1. The configuration for that is
Although not particularly limited, the control logic circuit 26 has hardware. A specific example of the configuration is shown in FIG.

In FIG. 8, the register 260 stores supply voltage range information extracted by the command decoder 24. For example, the supply voltage range information defines a corresponding voltage for each bit as illustrated in FIG.
The logical value “1” of the corresponding bit indicates correspondence, and the logical value “0” indicates non-correspondence. For example, B0 to B5 are logical values "1".
Then, the host device sets Vcc to 2.5 V to 3.0 V.
Means that the supply of the power supply voltage is guaranteed. The control logic circuit 26 is a non-volatile storage unit 261 as a random logic circuit that generates information (operation guarantee voltage range information) indicating the operation guarantee voltage range of the memory card LSI1.
Having. The format of the operation guarantee voltage range information is the same as the data format of the supply voltage range information of FIG. For example, if the operation guarantee voltage of the microcomputer 3 and the flash memory 4 is 2.7 V to 3.6 V and the operation guarantee voltage of other circuits such as the interface control circuit 2 is 2.0 V to 3.6 V, the memory card LSI
1 The operation assurance voltage range information of 2.7 V to 3.6
The information indicates the voltage range of V. Memory card LSI1
Is the operating voltage range required for the memory card LSI1 to operate normally as a whole. The register 262 is loaded with the operation guarantee voltage range information from the nonvolatile storage means 261. Register 262
The operation assurance voltage range information loaded in the
1 to the host device. The supply voltage range information of the register 260 and the operation assurance voltage range information of the register 262 are compared for each corresponding bit by an AND gate AND. Is output. The voltage range abnormality detection signal 263 indicates a voltage range abnormality by a low level. That is, when there is no common voltage between the supply voltage range and the operation guarantee voltage range, the outputs of the AND gate AND are all set to low level (logical value “0”), whereby the voltage range abnormality detection signal 263 becomes low. Be leveled. The abnormal voltage range state indicates that the power supply voltage Vcc supplied from the host device is
Is not in a state of satisfying the operation guarantee voltage.

When detecting the abnormal state of the voltage range, the memory card LSI1 shuts off signal input / output with the outside.
For example, as illustrated in FIG.
Reference numeral 6 controls each input buffer Bin for inputting the command 2B, inputting the data 2C, and inputting the clock 2A to a high input impedance state by the low level of the voltage range abnormality detection signal 263. Although not shown, the input of the card select signal 2D is similarly cut off.

The output control signals 255B and 256B for controlling the output enabled state and the high output impedance state for the respective output buffers Bout for outputting the data 2C and the command 2B are the voltage range abnormality detection signal 2
63 is supplied to an output buffer Bout via AND gates 265A and 266A. When the voltage range abnormality detection signal 263 is set to a low level, the output control signal 25
All output buffers Bout are controlled to a high output impedance state regardless of the logical values of 5B and 256B.

In this example, when an abnormal voltage range is detected, signal input / output to / from the memory card LSI 1 is shut off. Due to the signal input / output cutoff, the memory card LSI1 does not respond to an external signal, and the nodes of the internal circuit of the memory card LSI1 are substantially in an electrically fixed state. Thus, even if the external power supply Vcc from the host device 100 is incompatible, it is possible to prevent the memory card LSI 1 from malfunctioning due to an incomplete level of operation power supply. Further, wasteful power consumption due to the operation of the memory card LSI1 by receiving an incomplete level of operation power can be reduced.

Further, in the above example, the memory card LSI 1 is set to the inactive state by detecting an abnormality in the voltage range, and the possibility that a command is erroneously accepted can be prevented.

The interface control circuit 2 instructs the microcomputer 3 to interrupt upon detection of the voltage range abnormality, whereby the microcomputer 3 can be shifted to the sleep mode or the standby mode. As a result, the operation of the microcomputer 3 can be completely suppressed, and reduction of wasteful power consumption can be promoted. To exit from the sleep mode or the standby mode, it is sufficient to shift to the debug state by a debug permission command.

Further, since the microcomputer 3 cannot invert the reset enable bit RSB in the sleep mode or the standby mode, the reset state of the flash memory 4 is maintained. In this way, the operation of the flash memory 3 is also prohibited in response to the input cutoff of the memory card LSI1, and it is possible to contribute to both protection of stored information and reduction of power consumption.

<< Two-Step Reset >> Next, the memory card L
The reset operation of SI1 will be described. Memory card LSI
1, the operation assurance voltage of the microcomputer 3 and the flash memory is higher than that of other circuits typified by the interface control circuit 2. For example, as exemplified in FIG. 10, the interface control circuit 2 can operate between the operation guarantee lower limit voltage VT1 and the operation guarantee upper limit voltage VU. The microcomputer 3 can operate between the operation guarantee lower limit voltage VT2 and the operation guarantee upper limit voltage VU. The flash memory is operable between the voltage VD and the operation guarantee upper limit voltage VU with the voltage VD between the voltages VT1 and VT2 as the lower limit voltage of operation guarantee. The operation guarantee voltage range of the memory card LSI1 described in the voltage range abnormality detection is a range from the operation guarantee lower limit voltage VD of the flash memory 4 to the upper limit voltage VU in FIG. The voltage VD is also the operation guarantee lower limit voltage of the memory card LSI1.

When the memory card LSI 1 has such voltage characteristics, the reset circuit 5 sets the level of the power supply voltage Vcc defining the reset release timing of the interface control circuit 2 to VR1 (VR1> VT1), The level of the power supply voltage Vcc that defines the reset release timing of
2).

For example, as shown in FIG. 11, a reset circuit 5 generates a reference voltage generating circuit 50 that generates the voltages VR1 and VR2 as reference voltages independent of the power supply voltage level by using a band gap of silicon or the like. Having. Comparator 51 using operational amplifier
Compares the power supply voltage Vcc with the voltage VR1 and finds that Vcc> V
The reset signal RES1 is maintained at a high level until the state becomes R1. Comparator 52 using operational amplifier
Compares the power supply voltage Vcc with the voltage VR2, and Vcc> V
The reset signal RES2 is maintained at a high level until the state becomes R2. The reset signals ES1 and RES2 indicate a reset state by a high level, and instruct a release of the reset state by a low level.

When the reset state is instructed, the interface control circuit 2 forces the state inside the circuit to the initial state, forces a predetermined signal node inside the circuit to a prescribed logical value, and in parallel with this, Logic operation for control is prohibited. While the logical operation is prohibited, the input / output operation with the outside is suppressed. When the reset operation is released, operation is enabled from the initial state, and operation is enabled by receiving a command from the outside by the state transition control.

When the microcomputer 3 is instructed to be in the reset state, a predetermined signal node in the circuit is forcibly set to a prescribed logical value, and in parallel with this, instruction execution operations and input / output operations are completely prohibited. ing. When the release of the reset state is instructed, the instruction is fetched from the address 0 of the program counter, and the initialization processing by the instruction execution is started.

The interface control circuit 2 includes, as illustrated in FIG.
Has a ready / busy flag 269. The ready / busy flag 269 is set to a busy state in response to an instruction of the reset state to the interface control circuit 2. The process of inverting the ready / busy flag 269 to the ready state is performed by the microcomputer 3 in the initialization process after the reset state is released. Therefore, the ready / busy flag is not set to the ready state unless the microcomputer 3 is released from the reset state. The host device 100 is
The busy flag 269 can be read through the signal line of the command 2B, whereby it can be detected whether or not the reset of the microcomputer 3 has been released. The reading of the ready / busy flag 269 by the host device 100 is performed by causing the interface control circuit 2 to execute a specific command.

FIG. 12 shows the memory card LSI1 of FIG. 1 redrawn from the viewpoint of reset control. When the power supply voltage Vcc is applied, the reset signals RES1, R
ES2 goes high and the interface control circuit 2
Then, the reset state is instructed to the microcomputer 3. As a result, the interface control circuit 2 and the microcomputer 3 are in an operation prohibited state, and the internal circuit nodes are initialized to prescribed values. In this initialization operation, the reset enable bit RSB disposed inside the interface control circuit 2 is initialized to a high level,
The reset state of the flash memory 4 is indicated by a reset signal RES3 having the logical value of the bit RSB, and the nodes of the internal circuit are initialized to a prescribed logical value in a state where the memory operation is prohibited.

Here, when the microcomputer 3 is in the reset state, its logical operation is prohibited, so that the microcomputer 3 does not actively rewrite the reset enable bit RSB. However, when the power supply is not stable, noise may cause the reset enable bit RSB to be undesirably rewritten. In particular, due to the nature of being used as a file memory, rewriting or destruction of undesired data must be avoided as much as possible. Therefore, the reset signal RES2 is supplied to the interface control circuit 2, and the reset enable bit RSB is set to the reset enable bit RSB instruction level together with the rewrite instruction of the reset enable bit RSB from the microcomputer 3.
Rewrite condition. For example, as illustrated in FIG. 12, a rewrite signal 300 for the reset enable bit REB from the microcomputer 3 and a reset signal RE
S2 and S2 are supplied to an OR gate (not shown), and the OR signal is rewritten as a reset enable bit RSB. Reset enable bit RSB
Since the two signals 300 and RES2 must be set to a predetermined low level in order to set the reset release instruction level, the occurrence of an undesired reset release to the flash memory 4 can be reduced stochastically. Thereby, protection of the information stored in the flash memory 4 can be strengthened.

When the power supply voltage Vcc exceeds at least the voltage VR1, the interface control circuit 2 is released from the reset state and is made operable. Finally the power supply voltage Vcc
Does not exceed VR2, the interface control circuit 2 remains enabled. If at least the interface control circuit 2 is enabled, the interface control circuit 2 processes the voltage range confirmation command supplied from the host device 100, and
The first operation guarantee voltage range information can be sent back to the host device 100 to respond to the command. Even if the power supply voltage Vcc does not eventually exceed VR2, the host device 1
No response to 00 can be avoided. Further, the interface control circuit 2 detects the voltage range abnormality using the supply voltage range information accompanying the voltage range confirmation command. If there is the voltage range abnormality, the memory card LS is determined by the low level of the voltage range abnormality detection signal 263.
I1 has its signal input / output with the outside cut off.

Here, the initialization processing of the host device 100 during the power-on reset operation of the memory card LSI 1 will be described. FIG. 15 shows an example of the initialization processing by the host device. The initialization process is started by the host device 100 detecting that the memory card LSI1 is mounted in the mounting slot 101, as shown in FIGS. First, the host device 100
Initializes an interface circuit (not shown) for controlling the memory card LSI1, and initializes all the memory cards LSDI1 connected to the host device 100, including the newly inserted memory card LSI1. (S1). Subsequently, the host device 100 applies a common power supply voltage Vcc to each memory card LSI1. At the same time, the voltage range confirmation command is issued to each memory card LSDI1. Each memory card LSI
The host device 1 transmits its own operation guarantee voltage range information to the host device 1.
Output to 00. The host device 100 waits for input of the operation guarantee voltage range information (S2). The host device 100 recognizes the operation guarantee voltage range of each memory card LSI1 based on the input operation guarantee voltage range information (S3). Then, in the case of the system as shown in FIG. 3, the card ID confirmation command and the card address setting command are issued to set the card address for each memory card LSI 1 (S4). In the system of FIG. 2, the card address setting process is not performed because the card select signal is used.

The operation voltage confirmation processing (S3) by the host system will be described in further detail. For example, as illustrated in FIGS. 2 and 3, the plurality of memory cards LSI1 are connected to the host device 100 via a common signal line for transmitting data 2C, commands 2B, and the like. In the power-on reset of this system, each memory card L
In response to the voltage range confirmation command, the SI1 outputs the information of the operation guarantee voltage range specific to each to the common signal line in parallel. When each memory card LSI1 performs a data output operation in parallel, the output buffer of each memory card LSI1 is operated with an open drain. The information output in parallel is ANDed on the common signal line and input to the host device 100. That is, as is clear from the description of FIGS. 7 and 8, each bit of the operation guarantee voltage range information has a logical value of "1", which means that the voltage indicated by the bit is one of the voltages in the operation compensation range. ing. Therefore, if the predetermined bit of the operation assurance voltage range information obtained via the common signal line is a logical value “1”, any of the logic values of the corresponding bits of the operation assurance voltage range information output from each memory card LSI 1 It means that the logical value is “1”. This state is equivalent to the result of the logical product for the corresponding bit. Therefore, if all the memory cards LSI1
Is operating, the host device 100 can recognize a common voltage range that satisfies the operation guarantee voltage of each memory card LSI1. Therefore, the host device 100 can first determine the range of the power supply voltage required to normally operate at least one of the plurality of memory cards LSI1 connected this time, or, among the plurality of memory cards LSI1, Can be first determined whether a power supply voltage required to operate at least one of the above can be supplied normally.

For that purpose, it is necessary that all the mounted memory cards LSI1 can return the information of the operation guarantee voltage range to the host device 100. Memory card LS
Considering this point, I1 is an interface control circuit 2 that can operate with a relatively low operation power supply even if a necessary operation power supply is not finally obtained in relation to the power supply capability of the host device 100. Prior to the microcomputer 3 or the like, the reset state is released, and information on the operation guarantee voltage range can be returned to the host device 100.

Even if there is a memory card LSI1 that cannot finally obtain the required operation power in terms of the power supply capability of the host device 100, the LSI1 shuts off the signal input / output to the outside and stops operating. Host device 10
0 has no effect as long as the operating voltage range recognized first can be satisfied. In a conventional configuration in which the reset state of the entire LSI is released on the condition that the operating voltage of the entire LSI becomes a necessary operating voltage, a necessary operating power cannot be finally obtained in terms of power supply capability. , The LSI
Must maintain the reset state, cannot return information on the operation guarantee voltage range, etc. to the host device, and maintain a non-response state. A circuit that maintains the reset state without any response tends to be unstable, and wastes power.

As is clear from the above description, the memory card LSI 1 capable of two-stage reset can contribute to stabilization of the system operation by minimizing the non-response to the host device. Further, if a predetermined voltage equal to or higher than the minimum voltage of the power supply of the host device 100 is set as the reset release voltage VR1 of the interface control circuit 2 in the system, the microcomputer 3 or the flash memory whose operation guarantee lower limit voltage is slightly higher than that Even if 4 is adopted, on the system,
It can be done without any trouble.

FIG. 13 shows an example of another memory card LSI 1A having a different reset control method for the flash memory 4. That is, the microcomputer 3
Reset signal RES in response to its own reset state
At 2, the flash memory 4 is instructed to be in a reset state,
Reset signal R in response to release of reset state
ES3 is inverted to a low level and the flash memory 4
Release the reset state of. According to this, the reset state of the flash memory 4 is performed by the microcomputer 3 whose reset state has been released and which has become operable. Therefore, the possibility that the reset state of the flash memory 4 is released by mistake is relatively low. The interface control circuit 2 receives the reset signal RES2 and
If the microcomputer 3 has an extra port for outputting the reset signal RES3, reset control of the flash memory can be performed with a simple configuration. However, since the reset release of the flash memory 4 is performed without the intervention of the interface control circuit 2, the function of suppressing the undesired reset release of the flash memory is slightly inferior to that of FIG.

FIG. 14 shows still another example of the memory card LSI 1B of the reset control method for the flash memory 4. That is, the reset control of the flash memory 4 is also performed using the reset signal RES2. According to this, the flash memory 4 can be automatically released from the reset state together with the microcomputer 3,
Although the reset control logic is the simplest, the probability that the flash memory 4 is reset by mistake is the same as the probability that the microcomputer is reset by mistake. The resistance to undesired destruction must be lower than in FIGS.

<< Attribute Information Error Detection >> Memory Card LSI
1 stores attribute information as a file memory in the flash memory 4. The attribute information is ID information which is a code unique to the memory card LSI1, or information such as the storage capacity and access speed of the flash memory which is characteristic information of the semiconductor integrated circuit. The ID information is used by the host device 100 for processing such as the card address setting. The characteristic information is stored in the host device 100
Is used to determine the control mode of the memory card access according to. As is clear from this, the memory card L
If the ID information or characteristic information of SI1 is destroyed or does not exist, it becomes difficult for the memory card LSI1 to receive regular control by the host device.

Therefore, the microcomputer 3 of the memory card LSI 1 detects abnormality of the ID information and the characteristic information in the initialization processing after the reset state is released. The initialization processing program is stored in the ROM 34 starting from address 0, although there is no particular limitation.

FIG. 16 shows an example of the initialization processing procedure by the microcomputer 3. When the initialization processing routine is started, first, the microcomputer 3 and the registers of the interface control circuit 2 are initialized (S10). Next, the built-in SRA
A memory test of the M35, the work RAM 8, the buffer RAM 7, etc. is performed (S11), and the reset state of the flash memory 4 is released (S12). Next, a read access to the flash memory 4 is instructed, and a management table for the file memory is developed in the built-in SRAM 35 (S13). The management table includes a reference table for bad sectors, and the like. Further, the ID information and the characteristic information are searched from the flash memory (S14). In the case where the ID information and the characteristic information cannot be obtained by the search (the absence of the data), the case where the searched ID information and the characteristic information have an ECC error, in any case, It is determined that there is an abnormality in the attribute information such as ID information and characteristic information. If there is an abnormality, an attribute information abnormality flag is set (S16). If there is no abnormality, the card ID information and the card characteristic information are stored in the temporary storage memory 27 of the interface control circuit 2. Thereafter, the attribute information abnormality flag is checked, and if the flag is set (S1)
8) The memory card LSI 1 determines that the mode is the inactive mode, and executes a process of shifting to the sleep mode (S19). If the attribute information abnormality flag is in the reset state, the microcomputer 3 cancels the busy state (S20), and can accept an interrupt or the like from the interface control circuit 2 so as to be able to respond to a card access request. The release of the busy state is to set the ready / busy flag 269 to the ready state.

The attribute information abnormality flag set in step S16 is indicated by 301 in FIG. 4 and is given to the control logic circuit 26 of the interface control circuit 2. The control logic circuit 26 determines that the attribute information is abnormal by detecting the set state of the attribute information abnormality flag 301, and changes the internal state to the inactive state. Thereby, the interface control circuit 2 is set to the inactive mode in which only the command of the debug class can be received.
In the inactive mode, the interface control circuit 2 invalidates an external command input except for a command input of a debug class. Therefore, even if a command other than the debug class is supplied to the memory card LSI 1 in the inactive mode connected together with another memory card LSI, the interface control circuit 2 does not instruct the microcomputer 3 to interrupt, and the Operation is suppressed. Therefore, it is possible to reduce wasteful power consumption of the memory card LSI1 which is put into an uncontrollable state due to an abnormality in attribute information used for control or the like by the host device 100.

In the inactive mode, as shown in FIG. 6, the state can be changed to the debug state by inputting the debug permission command, and the vendor unique command can be received here. The vendor unique command includes a write command for the attribute information and the like. Therefore, the initial writing operation of the attribute information is guaranteed.

In order to further reduce the power consumption in the inactive mode, the interface control circuit 2 instructs the microcomputer 3 to enter a standby state in response to the inactive mode. And
The microcomputer 3 is released from the standby state in response to the input of the debug permission command. When stopping the supply of the clock signal CLK2 from the clock oscillation circuit 6 in the standby state,
The supply of the clock signal CLK2 may be restarted in response to the occurrence of an interrupt for releasing the standby state.

In the case of the attribute information abnormality, the processing is LSI1
To the inactive mode. For example, when the control logic circuit 26 detects an abnormality in the attribute information, signal input / output with the outside may be cut off except for a specific input, for example, an input to a card select signal. The input / output cutoff method can be dealt with by the high impedance control for the buffer circuit described with reference to FIG. This configuration can be used in the case of the system of FIG. 3 in which the card select signal 2D is not used for selecting the memory card LSI1. At this time, the input of the card select signal 2D is used as a setting signal of a write operation mode for enabling the attribute information to be written to the flash memory 4 initially. Also in this example, it is useful to reduce unnecessary power consumption of the memory card LSI which enters an uncontrollable state due to an abnormality in attribute information, and can guarantee an initial operation of writing attribute information. Furthermore, the microcomputer is set to a standby state in a signal input / output cutoff state with the outside,
Further, the means for stopping the supply of the clock signal CLK2 and further reducing the power consumption can be applied in the same manner as described above.

<< Memory >> Here, an example of the flash memory 4 will be described for reference. First, the principle of storing information in a flash memory will be described with reference to FIG.

The memory cell exemplarily shown in FIG. 17A is constituted by an insulated gate field effect transistor having a two-layer gate structure. In the figure, 431 is a P-type silicon substrate, 432 is a P-type semiconductor region formed on the silicon substrate 431, and 433 and 434 are N-type semiconductor regions. 435 is a floating gate formed on the P-type silicon substrate 431 via a thin oxide film 436 (for example, 10 nm thick) as a tunnel insulating film, and 437 is formed on the floating gate 435 via an oxide film 438. Control gate. The source is composed of 434 and the drain is 43
3,432. The information stored in the memory cell is held in the transistor as a change in the threshold voltage. Hereinafter, a case where a transistor for storing information (hereinafter, also referred to as a memory cell transistor) in a memory cell is an N-channel type, unless otherwise specified.

The operation of writing information into the memory cell is realized by, for example, applying a high voltage to the control gate 437 and the drain and injecting electrons from the drain to the floating gate 435 by avalanche injection. By this write operation, the storage transistor is turned on as shown in FIG.
As shown in (B) of FIG.
37, the threshold voltage becomes higher than that of the storage transistor in the erased state in which the writing operation is not performed.

On the other hand, in the erase operation, for example, a high voltage is applied to the source and the floating gate 4
This is realized by extracting electrons from 35 to the source side. As shown in FIG. 17B, the threshold voltage of the storage transistor viewed from its control gate 437 is lowered by the erase operation. In FIG. 17B,
The threshold value of the memory cell transistor is set to a positive voltage level in both the write and erase states. That is, the threshold voltage in the writing state is increased and the threshold voltage in the erasing state is decreased with respect to the word line selection level applied to the control gate 437 from the word line.
With such a relationship between the two threshold voltages and the word line selection level, a memory cell can be constituted by one transistor without employing a selection transistor. When the stored information is electrically erased, the stored information is erased by pulling out the electrons accumulated in the floating gate 435 to the source electrode. In operation, more electrons are drawn than the amount of electrons injected into the floating gate 435.
Therefore, if over-erasing is performed such that electrical erasing is continued for a relatively long time, the threshold voltage of the memory cell transistor becomes, for example, a negative level, which causes an inconvenience that the threshold voltage is selected even at a non-selected level of the word line. Is generated. Note that writing can be performed by using a tunnel current as in erasing.

In the read operation, the voltages applied to the drain and the control gate 7 are compared so that weak writing to the memory cell, that is, undesired carrier injection to the floating gate 435 is not performed. Limited to extremely low values. For example, a low voltage of about 1 V is applied to the drain, and a low voltage of about 5 V is applied to the control gate 437. By detecting the magnitude of the channel current flowing through the memory cell transistor based on these applied voltages, the logical values “0” and “1” of the information stored in the memory cell can be determined.

FIG. 18 shows the configuration principle of a memory cell array using the memory cell transistors. FIG. 1 representatively shows four memory cell transistors Q1 to Q4. In the memory cells arranged in a matrix in the X and Y directions, memory cell transistors Q arranged in the same row
1, Q2 (Q3, Q4) control gates (memory cell selection gates)
1 (WL2) and the drain regions (input / output nodes of the memory cells) of the storage transistors Q1, Q3 (Q2, Q4) arranged in the same column are connected to the corresponding data lines DL1 (DL2), respectively. I have. Source regions of the storage transistors Q1, Q3 (Q2, Q4) are coupled to a source line SL1 (SL2).

FIGS. 19A, 19B and 19C show an example of voltage conditions for an erase operation and a write operation for a memory cell. In the figure, a memory element means a memory cell transistor, and a gate means a control gate as a selection gate of the memory cell transistor. In the figure, in the erasing by the negative voltage method, a high electric field required for erasing is formed by applying a negative voltage such as -10 V to the control gate. As is clear from the voltage conditions illustrated in FIG. 10, in the erasing by the positive voltage method, at least the memory cells whose sources are commonly connected can be erased in a lump. Therefore, FIG.
In the configuration described above, if the source lines SL1 and SL2 are connected, the four memory cells Q1 to Q4 can be collectively erased. In the source line division method, in addition to the case of using data lines as a representative as shown in FIG. 18 (extending the common source line in the data line direction), the case of using word lines as the unit (common source line) Extending in the word line direction). On the other hand, in the erasing by the negative voltage method, batch erasing can be performed on the memory cells to which the control gate is commonly connected.

FIG. 20 shows an example of the flash memory 4. In FIG. 20, reference numeral 403 denotes a memory array, which includes a memory mat and a sense latch circuit. The memory mat has a large number of electrically erasable and writable nonvolatile memory cell transistors. As described with reference to FIG. 17, for example, a memory cell transistor includes a source and a drain formed in a semiconductor substrate or a memory well, a floating gate formed in a channel region via a tunnel oxide film, and an interlayer insulating film formed in a floating gate. It is configured to have a control gate superposed through a film. The control gate is connected to the word line 406, the drain is connected to the bit line 405,
The source is connected to a source line not shown.

The external input / output terminals I / O0 to I / O7 are also used as address input terminals, data input terminals, data output terminals, and command input terminals. External input / output terminal I / O0
The X address signal input from ＩI / O 7 is supplied to X address buffer 408 via multiplexer 407. X address decoder 409 decodes an internal complementary address signal output from X address buffer 408 to drive a word line.

Although not particularly shown, the memory array 4
The memory mats included in 03 are arranged on the left and right of the sense latch circuit array. That is, a precharge circuit, a bit line, and the like are arranged at both input / output nodes of the sense latch circuit, respectively. The bit line 405 is selected by the Y gate array circuit 413 based on a selection signal output from the Y address decoder 411. External input / output terminal I
The Y address signals input from / O0 to I / O7 are preset in a Y address counter 412, and the address signals sequentially incremented from the preset value are supplied to the Y address decoder 411.

The bit line selected by Y gate array circuit 413 is conducted to the input terminal of output buffer 415 during data output operation, and is conducted to the output terminal of input buffer 417 via data control circuit 416 during data input operation. You. The connection between the output buffer 415 and the input buffer 417 and the input / output terminals I / O0 to I / O7 is controlled by the multiplexer 407. I / O terminals I / O0
The command supplied from the I / O 7 is a multiplexer 40
7 and the mode control circuit 41 via the input buffer 417.
8 given. The data control circuit 416 includes, in addition to the data supplied from the input / output terminals I / O0 to I / O7,
The logic value data according to the control of the mode control circuit 418 can be supplied to the memory array 403.

The control signal buffer circuit 419 has a chip enable signal CEb, an output enable signal OEb, a write enable signal WEb,
A serial clock signal SC, a reset signal RESb, and a command enable signal CDEb are supplied.

The mode control circuit 418 controls the signal interface function with the outside according to the state of these signals, and controls the internal operation according to the command code. In the case of a command or data input to the input / output terminals I / O0 to I / O7, the signal CDEb is asserted. In the case of a command, the signal WEb is further asserted. In the case of data, the signal WEb is negated. If it is an address input, the signal CDEb is negated and the signal WEb is asserted. Thereby, the mode control circuit 418
Can distinguish commands, data and addresses multiplexed from the external input / output terminals I / O0 to I / O7. The mode control circuit 418 can assert the ready / busy signal R / Bb during an erase or write operation to notify the state to the outside.

The internal power supply circuit 420 generates various operation power supplies 421 for writing, erasure verification, reading, and the like, and supplies them to the X address decoder 409, the memory cell array 403, and the like.

The mode control circuit 418 controls the entire flash memory 4 according to a command. The operation of the flash memory 4 is basically determined by a command.

Commands assigned to the flash memory are, for example, commands such as read, erase, and write. The read command is constituted by a first command, and the other commands are constituted by first and second commands.

The flash memory 4 has a status register 423 for indicating its internal state.
When the signal OEb is asserted, the input / output terminal I
/ O0 to I / O7.

When a write operation is instructed by the write command, the sense latch circuit can latch write data supplied via the Y gate array circuit 413. According to this example, the flash memory 4
Has 8-bit input / output terminals I / O0 to I / O7, so that write data can be set in eight sense latch circuits by one write data input. In this description, since the unit of writing is a word line unit, the write voltage is set in the sense latch circuits for the bit lines of all the memory cells whose selection terminals are coupled to one word line. Is applied to perform the write operation. For example, in a write operation,
All the bit lines are precharged to a predetermined level in advance, the bit lines of the memory cells selected for writing are discharged to the ground potential, the bit lines of the memory cells selected for writing are maintained at the precharge level, When a write high voltage is applied to the write-selected word line, a high voltage is applied between the control gate and the drain of the write-selected memory cell, whereby
The threshold voltage of the memory cell selected for writing is increased,
The writing state is set. Before the write operation, the memory cell is in an erased state in which the threshold voltage has been lowered. Note that the threshold voltage states for writing and erasing may be defined in the opposite manner.

Incidentally, the reset signal RESb in FIG.
Is a signal corresponding to the reset signal RES3. FIG.
The input / output signals of the multiplexer 407 and the control signal buffer circuit 419 are exchanged with the FCL 13 of FIG.

Next, the built-in SRAM 35, work RA
A description will be given with reference to an example of a static memory cell constituting the buffer RAM 7 and M8. FIG. 21 typically shows one static memory cell 70. The static memory cell 70 has a pair of CMOS inverters composed of an n-channel MOS transistor 71 and a p-channel MOS transistor 72, and one of the CMOS inverters is connected to the other.
The input terminal of the MOS inverter is cross-coupled to the output terminal of the other CMOS inverter to form a static latch. A pair of storage nodes of the static latch are coupled to complementary bit lines 78t and 78b via n-channel type select MOS transistors 75 and 76. The gates of the select MOS transistors 75 and 76 are connected to a word line 77.
Is joined to.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto, and various modifications can be made without departing from the gist of the invention. No.

For example, the commands and data are not limited to serial signals, but may be parallel signals.

The cluster size is not limited to four sectors. It can be determined as appropriate depending on the memory mat configuration of the flash memory, the storage capacity of the built-in SRAM for expanding the management table, and the like.

The external instruction to which the interface control circuit responds when the power is turned on is not limited to the instruction for confirming the voltage range. It may be an instruction to respond to other states or circuit characteristics of the internal circuit.

The microcomputer means a logic circuit unit having a function of fetching and executing an instruction.
The present invention is not limited to the configuration in which the verified design data of the SI is used. A newly custom-designed circuit may be used.

The polarity of the reset signal may be opposite to the above. A low level indicates a reset state, and a high level indicates release of the reset state.

The voltage range abnormality detection operation may be detected by a microcomputer performing a comparison operation in bit units.
However, in this case, the operation is enabled only after the reset state of the microcomputer is released.

The semiconductor integrated circuit is not limited to application to a memory card. Communication interface cards such as MODEM (modem) and TA (terminal adapter), LAN
The present invention can be widely applied to network cards such as (local area network), interface cards for video capture, voice recognition, and the like.

Further, the memory card LSI has been described as one chip. By using one chip, higher operation speed and lower power consumption can be expected as compared with a multi-chip configuration.

[0129]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

A third circuit having a first circuit having an external interface function and a second circuit having an operation guarantee lower-limit voltage higher than the first circuit, and controlling reset of the first and second circuits. The first circuit instructs the first and second circuits to be in a reset state in response to turning on an external power supply, and first releases the reset state of the first circuit when the power supply voltage is low. By this two-stage reset, the first circuit can perform processing in response to an external instruction regardless of whether or not the reset of the second circuit is canceled. Even if a proper operation assurance voltage cannot be obtained, a non-response state to the outside can be avoided.

Information (supply voltage range information) indicating the range of the power supply voltage supplied to itself is input from outside, and it is determined whether or not the voltage range specified by the information satisfies the operation guarantee voltage. When the operation guarantee voltage is not satisfied, signal input / output with the outside is shut off. Due to this voltage range abnormality detection, the semiconductor integrated circuit does not respond to external signals, the internal nodes of the circuit are almost electrically fixed, and the external power supply does not match the operation guarantee voltage of the semiconductor integrated circuit. Even in this case, it is possible to prevent a malfunction of the semiconductor integrated circuit due to a half-level operation power supply, and it is possible to reduce unnecessary power consumption.

A configuration for two-stage reset and voltage range abnormality detection uses a semiconductor integrated circuit that is detachable from the host device and can be supplied with operating power from the host device via an interface portion or a connector portion. In the conventional memory card, it is possible to detect whether or not the operation guarantee voltage range is compatible with the operation voltage range covered by the host device, and it is possible to prevent malfunction due to an incomplete level of operation power supply and reduce wasteful power consumption. .

In response to the abnormality of the attribute information, an inactive mode in which commands other than the specific command cannot be accepted is set, and input / output of external signals other than the specific input is cut off. With the configuration of the attribute information abnormality detection, it is possible to prevent the semiconductor integrated circuit from consuming unnecessary power even when the host device cannot be controlled due to the abnormality of the attribute information used for controlling the host device or the like. Can be.

With a configuration for detecting attribute information abnormality, in a memory card using a semiconductor integrated circuit that is detachable from the host device and controlled by the host device via an interface portion or a connector portion, the control of the host device is performed. An abnormality in the attribute information provided for such purposes can be detected, and even if control from the host device becomes impossible due to the abnormality, reduction of unnecessary power consumption and prevention of malfunction can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory card LSI as an example of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a data processing system using the card select signal unique to each memory card LSI.

FIG. 3 is a block diagram illustrating an example of a data processing system that uses a card address sent along with a command.

FIG. 4 is a block diagram illustrating an example of a host interface circuit.

FIG. 5 is an explanatory diagram showing an example of a command that can be accepted by a memory card LSI.

FIG. 6 is an explanatory diagram illustrating an example of state transition control by a state machine.

FIG. 7 is an explanatory diagram showing the significance of supply voltage range information.

FIG. 8 shows that the voltage range specified by the supply voltage range information sent along with the voltage confirmation command is the memory card LS.
FIG. 3 is a block diagram showing an example of a circuit configuration for determining whether or not an operation guarantee voltage of I is satisfied.

FIG. 9 is a logic circuit diagram illustrating an example of a buffer circuit that shuts off input / output with the outside in response to a voltage range abnormal state.

FIG. 10 is an explanatory diagram illustrating an example of a relationship between a guaranteed operation voltage and a reset release voltage of the microcomputer and the flash memory.

FIG. 11 is a logic circuit diagram illustrating an example of a reset circuit.

FIG. 12 is a block diagram mainly showing a viewpoint of reset control of the memory card LSI of FIG. 1;

FIG. 13 is a block diagram showing an example of another memory card LSI in which a reset control method for a flash memory is different from that of FIG. 12;

FIG. 14 is a block diagram showing another example of a memory card LSI in which a reset control method for a flash memory is different from that of FIG. 12;

FIG. 15 is a flowchart illustrating an example of initialization processing of the host device during a power-on reset operation of the memory card LSI.

FIG. 16 is a flowchart illustrating an example of an initialization process by the microcomputer.

FIG. 17 is an explanatory diagram showing the information storage principle of a flash memory.

FIG. 18 is a circuit diagram showing a configuration principle of a memory cell array using flash memory cell transistors.

FIG. 19 is an explanatory diagram showing an example of voltage conditions for an erase operation and a write operation for a flash memory cell.

FIG. 20 is a block diagram illustrating an example of a flash memory.

FIG. 21 is a circuit diagram illustrating an example of a static memory cell.

[Explanation of symbols]

 1 Memory card LSI Vcc Power supply voltage Vss Ground voltage 2 Interface control circuit 2A Clock signal 2B Command 2C Data 2D Card select signal 3 Microcomputer 4 Flash memory 5 Reset circuit VT1 Operation guarantee lower limit voltage of interface control circuit VR1 Reset release of interface control circuit Voltage VT2 Minimum operation guarantee voltage of macro computer VR2 Reset release voltage of macro computer VD Minimum operation guarantee voltage of memory card LSI VU Maximum operation guarantee voltage of memory card LSI 6 Clock oscillation circuit 7 Buffer RAM 11 Host interface circuit Bout Output buffer Bin input Buffer 20 Command input register 21 Response control circuit 22 Data input register 23 Data output register 24 Command decoder 26 Control logic circuit 30 CPU 32 Interrupt controller NMI Interrupt signal CLK1, CLK2 Clock signal RES1, RES2, RES3 Reset signal RSB Reset enable bit 50 Reference voltage utterance circuit 100 Host device 260 Register for storing supply voltage range information 261 Non-volatile Storage means 262 Register for storing operation guarantee voltage range information 263 Voltage range abnormality detection signal 301 Attribute information abnormality flag

Continuing on the front page (72) Inventor Atsushi Shikata 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Kenki Kanamori 5--20, Josuihoncho, Kodaira-shi, Tokyo No. 1 Hitachi Semiconductor Co., Ltd. Semiconductor Business Headquarters (72) Inventor Kazunori Furuzawa 5-20-1, Josuihoncho, Kodaira-shi, Tokyo F-term F-term (Hitachi) Semiconductor Business Headquarters Co., Ltd. 5B011 DB21 EA06 EB01 EB03 GG04 JA03 JA07 MB16 5B035 AA05 AA11 BB09 CA12 CA13 CA35

Claims (21)

[Claims] 1. An information indicating a range of a power supply voltage is inputted from outside, and it is determined whether or not a voltage range specified by the information satisfies an operation guarantee voltage. A semiconductor integrated circuit for interrupting signal input / output. 2. A semiconductor integrated circuit having an interface control circuit and an internal circuit, wherein the interface control circuit inputs information indicating a range of a power supply voltage from outside, and a voltage range specified by the information is a semiconductor range. A semiconductor integrated circuit for determining whether or not an operation guarantee voltage of an integrated circuit is satisfied, and shutting off signal input / output with the outside when the operation guarantee voltage is not satisfied. 3. A semiconductor integrated circuit having an interface control circuit and an internal circuit, wherein the interface control circuit inputs information indicating a range of a power supply voltage from outside, and a voltage range and a semiconductor specified by the information. A semiconductor integrated circuit for determining whether or not a common voltage exists in a range of an operation guarantee voltage of the integrated circuit; and when the determination result indicates that there is no common voltage, interrupting signal input / output with the outside. circuit. 4. The interruption of signal input / output to / from the outside is achieved by a high input impedance state of an externally interfaced input buffer and a high output impedance state of an externally interfaced output buffer. 4. The semiconductor integrated circuit according to claim 2, wherein: 5. The internal circuit includes a microcomputer, and the interface control circuit instructs the microcomputer to enter a standby state when interrupting signal input / output with the outside. 5. The semiconductor integrated circuit according to any one of items 2 to 4. 6. The non-volatile memory means for generating information indicating a range of an operation guarantee voltage of a semiconductor integrated circuit, and a register means for holding information indicating a range of an externally supplied power supply voltage. 6. The semiconductor integrated circuit according to claim 5, further comprising comparison means for comparing a value generated from said nonvolatile storage means with a value of said register means. 7. The internal circuit further includes an electrically rewritable nonvolatile memory, and prohibits the operation of the nonvolatile memory when interrupting signal input / output with the outside. 7. The semiconductor integrated circuit according to claim 5, wherein: 8. The interface control circuit outputs information indicating an operation guarantee voltage of a semiconductor integrated circuit to an external device in response to input of information indicating an external power supply voltage range from the outside. 8. The method according to claim 2, wherein:
The semiconductor integrated circuit according to any one of the above items. 9. An image processing apparatus comprising: a storage unit; and a data processing unit, wherein the data processing unit sets an inactive mode when detecting an abnormality in the attribute information held by the storage unit, and sets the inactive mode in the inactive mode. A semiconductor integrated circuit for invalidating an external command input except for a specific command input for canceling. 10. The semiconductor integrated circuit according to claim 9, wherein said specific command is a command for setting said attribute information in a writable state or a command for writing attribute information. 11. A storage unit and a data processing unit, wherein the data processing unit shuts off signal input / output to / from outside except for a specific input when detecting an abnormality in attribute information stored in the storage unit. A semiconductor integrated circuit characterized in that: 12. The semiconductor integrated circuit according to claim 11, wherein said specific input is a predetermined signal input state to a predetermined external terminal. 13. The attribute information is an ID of a semiconductor integrated circuit.
13. The semiconductor integrated circuit according to claim 9, wherein the semiconductor integrated circuit is information, and the abnormality is information absence or data destruction. 14. The semiconductor integrated circuit according to claim 9, wherein the attribute information is characteristic information of the semiconductor integrated circuit, and the abnormality is information absence or data destruction. 15. The data processing means has an interface control circuit for interfacing with the outside, and a microcomputer connected to the interface control circuit, wherein the interface control circuit responds to the inactive mode. 11. The semiconductor integrated circuit according to claim 9, wherein a standby state is instructed to the microcomputer, and the standby state of the microcomputer is released in response to the input of the specific command. 16. The data processing means has an interface control circuit for interfacing with the outside, and a microcomputer connected to the interface control circuit, wherein the interface control circuit responds to the inactive mode. A clock supply to the microcomputer is stopped, a clock supply to the microcomputer is restarted in response to the input of the specific command, and an interrupt is requested to the microcomputer to start a process for executing the specific command. 11. The semiconductor integrated circuit according to claim 9, wherein: 17. The data processing means includes an interface control circuit for interfacing with an external device, and a microcomputer connected to the interface control circuit, wherein the interface control circuit performs signal input / output with the external device. 13. The semiconductor integrated circuit according to claim 11, wherein a standby state is instructed to the microcomputer in response to the cutoff, and the microcomputer is released from the standby state in response to the specific input. 18. The data processing means includes an interface control circuit for interfacing with an external device, and a microcomputer connected to the interface control circuit, wherein the interface control circuit performs signal input / output with the external device. In response to the interruption, the clock supply to the microcomputer is stopped, the clock supply to the microcomputer is restarted in response to the specific input, and an interrupt requesting the microcomputer to execute a process in response to the specific input is requested. 13. The semiconductor integrated circuit according to claim 11, wherein 19. An interface control circuit having an external interface function, a microcomputer connected to the interface control circuit, and a nonvolatile memory electrically rewritable and access-controlled by the interface control circuit. Wherein the interface control circuit receives an external command to instruct operations of the microcomputer and the nonvolatile memory, and controls access to file data to the nonvolatile memory. Controlling the generation and update of a management table for managing the array of file data in the management unit area of the nonvolatile memory, and accessing the interface control circuit using the management table when accessing the file data. The interface control circuit inputs information indicating the range of the power supply voltage from the outside, and determines whether the voltage range specified by the information satisfies the operation guarantee voltage of the memory card. A memory card for shutting off signal input / output with the outside when the operation guarantee voltage is not satisfied. 20. An interface control circuit having an external interface function, a microcomputer connected to the interface control circuit, and a nonvolatile memory electrically rewritable and access-controlled by the interface control circuit. Wherein the interface control circuit receives an external command to instruct operations of the microcomputer and the nonvolatile memory, and controls access to file data to the nonvolatile memory. Controlling the generation and update of a management table for managing the array of file data in the management unit area of the nonvolatile memory, and accessing the interface control circuit using the management table when accessing the file data. The interface control circuit sets an inactive mode when detecting an abnormality in the attribute information held in the nonvolatile memory, and releases the mode in the inactive mode. A memory card for invalidating an external command input except for a specific command input for the purpose. 21. An interface control circuit having an external interface function, a microcomputer connected to the interface control circuit, and a nonvolatile memory electrically rewritable and access-controlled by the interface control circuit. Wherein the interface control circuit receives an external command to instruct operations of the microcomputer and the nonvolatile memory, and controls access to file data to the nonvolatile memory. Controlling the generation and update of a management table for managing the array of file data in the management unit area of the nonvolatile memory, and accessing the interface control circuit using the management table when accessing the file data. The interface control circuit interrupts signal input / output with the outside except for a specific input when detecting an abnormality of attribute information held in the nonvolatile memory. A memory card, comprising: