JP2000244323A - Σδa/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a quantization noise by serially connecting an input terminal and an adder and an integrator, and comparing the output of the integrator with a predetermined value, and outputting the result as a digital value, and connecting the output signal of a flip flop with an output terminal, and controlling the generation timing of a trigger signal to be applied to the flip flop. SOLUTION: A trigger control circuit 100 limits the frequency of the generation of a trigger signal to be outputted to a flip flop 13. The trigger control circuit 100 is provided with a signal processing circuit A for generating a trigger component signal by detecting the up-edge of the output of a comparator 12 and a signal processing circuit B for generating a trigger component signal by detecting the down-edge of the output of the comparator 12. The trigger component signals generated by those signal processing circuits are inputted to an OR circuit 101, and the output is outputted to a clock input terminal Cin of a flip flop 13 as a trigger signal TRG.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a .SIGMA..DELTA. A / D converter for outputting a pulse density signal corresponding to an input signal, and particularly to a reduction in quantization noise without increasing the signal processing speed of an analog circuit portion such as an integrator or a comparator for handling an analog signal. And a ΣΔ AD converter.

[0002]

2. Description of the Related Art The configuration of a conventional ΣΔ AD converter will be described with reference to FIG. In the figure, an input signal X (z) is input to an integrator 11 via an adder 15, and an output thereof is input to a comparator 12.

The output of the comparator 12 is input to a flip-flop 13, and the output is output to an output terminal 62. The flip-flop 13 has a ΣΔAD
Internal clock signal CL serving as a sampling signal for the converter
K is connected, and its output is input to the − terminal of the adder 15 via the D / A converter 14.

In the ΣΔ AD converter having such a configuration, the input signal X (z) is integrated by an integrator 11, and the integrated signal A 11 is compared with a predetermined value of a comparator 12. This comparison output D12 is the flip-flop 1
3 and is repeatedly turned on and off at the timing of the clock signal CLK to output an output signal D13.

The output signal D1 of the flip-flop 13
3 is converted into an analog signal A14 by the D / A converter 14, and then the input signal X is converted by the adder 15.
(Z).

[0006] By repeating such an operation,
The ΣΔ AD converter 4 can output a pulse density signal Y (z) corresponding to the input signal X (z).

Further, like the circuit shown in FIG.
By adding the adder 45 and the integrator 41 to the circuit of the above, it is possible to further reduce the quantization noise and increase the resolution as compared with the circuit of FIG. The circuit in FIG. 9 is called a primary ΣΔ AD converter because there is one integrator, and the circuit in FIG. 10 is called a secondary ΣΔ AD converter because there are two integrators.

Here, assuming that the sampling frequency in the ΣΔ AD converter described above is fs, the signal band is fc, and the output level of the converter is ± Δ, the quantization noise power N1 of the ΣΔ AD converter is N1 ² = 8/9 × π ² × Δ ² × (fc / fs) ³ (1)

The quantization noise power N2 of the ^second -order ΣΔ AD converter shown in FIG. 10 can be expressed by the following equation: N2 ² = 32/15 × π ⁴ × Δ ² × (fc / fs) ⁵ (2) .

On the other hand, the maximum amplitude of the output signal is ± Δ,
Power when the primary secondary case both for the delta ^2/2, the signal-to-noise ratio SN1 primary ΣΔAD converter, SN1 = 9 / (16 × π 2) × (fc / fs) - ³ (3), and the signal noise ratio SN2 of the second-order 、 ２Δ AD converter is as follows: SN2 = 15 / (64 × π ⁴ ) × (fc / fs) ^-5 (4)

As a feature of the ΣΔ AD converter described above, the output is one bit (there is a multi-bit output type).
, A small-scale hardware, easy power saving, and high resolution without adjustment by increasing the sampling rate.

[0012]

However, in the conventional ΣΔ AD converter described with reference to FIGS. 9 and 10, the signal-to-noise ratio is improved as is apparent from the above equations (3) and (4). Therefore, it is necessary to increase the sampling frequency fs. In order to increase the sampling frequency fs, it is necessary to improve the performance because other components follow the operation speed. For example, the operation speed of the operational amplifier constituting the integrator is improved, the delay time of the comparator is reduced, and the delay time of the D / A converter is reduced.

In general, the operating current of an operational amplifier and a comparator increases as the operating speed increases, and the price increases. Conversely, as the operation speed decreases, the current consumption decreases, and the price decreases.

When such a ΣΔ AD converter is used in, for example, a two-wire eddy flow meter, these 流量 Δ AD converters transmit a flow signal shared with an operating power source to an external device as a 4-20 mA current signal for a measurement range. Therefore, it is necessary to operate the AD converter at a total current consumption of 4 mA or less.

Therefore, in the conventional ΣΔ AD converter,
If an attempt is made to improve the signal-to-noise ratio by increasing the sampling frequency fs, it is necessary to improve the performance of the components constituting the analog circuit, resulting in an increase in cost.

When the conventional ΣΔ AD converter is used for a two-wire transmitter such as a vortex flow meter, the current consumption of the analog circuit is limited, so that it can operate at 4 mA or less. However, there is a problem that the sampling frequency fs can be increased only by the above.

An object of the present invention is to provide a ΣΔ AD converter capable of reducing quantization noise by increasing the operation speed of a digital circuit without increasing the operation speed of an analog circuit. With the goal.

[0018]

According to the first aspect of the present invention, an input terminal, an adder, and an integrator are connected in series, and the output of the integrator is determined in advance. The output signal of the flip-flop is output to an output terminal using a comparator that compares the predetermined value and outputs the result of the comparison as a 1-bit digital value, and a flip-flop that holds the output of the comparator in synchronization with a trigger signal. The ΣΔ AD converter, which connects the output signal to the adder via a D / A converter and outputs a pulse density signal corresponding to the input signal, generates a trigger signal to be applied to the flip-flop. And a trigger control circuit for controlling the trigger control circuit.

Thus, the trigger control circuit can control the frequency at which the output signal of the flip-flop changes.

According to a second aspect of the present invention, in the first aspect of the present invention, the trigger control circuit restricts a trigger signal of the flip-flop for a preset period to change the pulse density signal. It is possible to reduce the frequency of performing. This is equivalent to lowering the frequency of the digital signal input to the D / A converter 14.

According to the third to sixth aspects of the present invention, in the first aspect of the present invention, the trigger control circuit can be manufactured with a simple circuit configuration using general-purpose components.

According to a seventh aspect of the present invention, in the first aspect of the present invention, the trigger control circuit comprises
It is possible to cope with the next ΣΔ AD converter.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram of a ΣΔ AD converter according to the present invention. In the same figure, those performing the same operations as in FIG. 9 described in the conventional example are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 1 differs from FIG. 9 in that the output of the comparator 12 is
And the output of the trigger control circuit 100 is connected to the clock input terminal Cin of the flip-flop 13.

The trigger control circuit 100 is a circuit for limiting the frequency of occurrence of a trigger signal to be output to the flip-flop 13, and is a signal processing for detecting the rising edge of the output of the comparator 12 and generating a trigger component signal a. A circuit A and a signal processing circuit B for detecting a down edge of the output of the comparator 12 and generating a trigger component signal b are provided. These are driven in accordance with the timing of a clock signal CLK which is a sampling signal of the ΣΔ AD converter. The trigger component signal a and the trigger component signal b generated here are input to an OR circuit 101 and the output thereof is used as a trigger signal TRG as a flip-flop. 13
Is output to the clock input terminal Cin.

The signal processing circuit A and the signal processing circuit B have the same configuration, and the up-edge is detected by directly inputting the output of the comparator 12 inside the trigger control circuit 100 to the signal processing circuit A. Then, a trigger component signal a is generated, and a signal obtained by inverting the output of the comparator 12 is input to the signal processing circuit B by an inverter 102 provided in the trigger control circuit 100, thereby detecting a down edge and causing the trigger component Generate signal b.

FIG. 2 shows operation waveforms of the trigger control circuit 100 described above. FIGS. 6A and 6B show the relationship between the clock signal CLK, the output S1 of the comparator 12, and the trigger signal TRG output from the trigger control circuit 100. FIG.

The trigger control circuit 100 is a circuit for limiting the frequency of occurrence of a trigger signal as described above. This is for limiting the interval between the previously generated trigger signal TRG and the next generated trigger signal TRG. Thus, the frequency of occurrence of the trigger signal TRG is limited.

That is, the trigger control circuit 100
If the output S1 of the comparator 12 changes from low to high within a predetermined delay time of n clocks from the previously generated trigger signal TRG, the trigger is generated after a delay time of n clocks from the previous trigger signal generation. Signal T
Generate RG. In FIG. 2A, the conventional ΣΔAD
In the converter, the output of the comparator 12 is latched by the flip-flop 13 at the following timing. However, in the case of the ΣΔ AD converter of the present invention, the delay time for a predetermined n clocks from the previous timing when the trigger signal TRG is generated. Is output, the output of the comparator 12 is latched.

Further, as shown in FIG. 2B, the trigger control circuit 100 controls the trigger signal TR generated last time.
When the output S1 of the comparator 12 changes from low to high after a predetermined delay time of n clocks from G has elapsed, at the edge-up timing of the clock signal CLK immediately after the output S1 changes from low to high. A trigger signal TRG is generated. The operation in this case is the same as the operation of the conventional ΣΔ AD converter.

Such a trigger control circuit 100
The operation of the .SIGMA..DELTA. AD converter of the present invention provided with the above will be described with reference to the waveform diagram of FIG. FIG. 3A shows the ΣΔ of the present invention.
When a signal having a size of 入 力 of the input range is input to the AD converter, the input S2 of the comparator 12, the output S1 of the comparator 12, the trigger component signal a, the trigger component signal b, and the output S3 of the flip-flop 13 FIG. 2B shows the relationship between the clock signal CLK and the clock signal CLK. FIG. 4B shows the same components as described above when a signal having a magnitude close to the full scale of the input range is input to the ΣΔ AD converter of the present invention. FIG.

In FIG. 3A, even when the output S1 of the comparator 12 changes, the trigger signal TRG, which is the OR signal of the trigger component signal a and the trigger component signal b, is limited, so that the output S3 of the flip-flop 13 is limited. Does not change immediately. That is, the trigger signal T of the flip-flop 13 is
Due to the limitation of the RG, the frequency of change of the pulse density signal input to the D / A converter 14 is reduced, and as a result, the output of the D / A converter 14 is held for a certain period of time. The operation speed of the analog circuit portion after 15 is reduced.

The output of the flip-flop of the conventional .SIGMA..DELTA. AD converter changes most frequently when a signal having a size of 1/2 of the input range is input, and its frequency (hereinafter, referred to as the maximum output frequency). Is 1 / frequency of the clock signal
Double. However, in the case of the ΣΔ AD converter of the present invention, the frequency is 1 / n times the frequency of the clock signal. However, n in this case is effective when n ≧ 3. n = 1,2
In this case, the operation is similar to that of the conventional ΣΔ AD converter.

FIG. 3B is a waveform diagram of each part when a signal having a magnitude close to the full scale of the input range is input to the ΣΔ AD converter of the present invention.
Output S3 changes little. In this case, when the output S1 of the comparator 12 has changed, the trigger signal TRG by the trigger control circuit 100 has already passed since the delay time for the preset n clocks has elapsed.
There is no restriction on outbreaks. Therefore, in this case, when the output S1 of the comparator 12 changes, the trigger control circuit 100 generates the trigger signal TRG at the timing of the rising edge of the clock signal CLK immediately after that. The operation in this case is the same as the operation of the conventional ΣΔ AD converter.

That is, the trigger control circuit 100
The case where the input signal X (z) of about １ ／ of the input range where the pulse density signal Y (z) is output most frequently is input by appropriately setting the delay time for the n clocks. Only when the trigger signal TRG is limited, and the input signal X (z) having a magnitude close to full scale or zero or a frequency at which the pulse density signal Y (z) does not change is input, the trigger signal TRG is reduced. Do not limit.

The error at the input of the comparator 12 of the ΣΔ AD converter having such a configuration is n / 2 times that of the conventional ΣΔ AD converter. Quantization noise power is also n ^2/4
And the signal noise ratio SN is 4 / n ² times.

Therefore, assuming that the signal-to-noise ratio SN when the 変 換 Δ AD converter of the present invention has a primary configuration is SN11, SN11 = 4 / n ² × 9 / (16 × π ² ) × (fc / fs) ^{- 3} (5) On the other hand, the frequency at which the output of the ΣΔ AD converter changes is reduced to 2 / n times. Therefore, paying attention to the operation speed of the analog circuit portion such as the comparator 12, if the processing speed equivalent to the conventional method is maintained, the clock frequency (sampling frequency) can be increased to n / 2 times. FIG. 4 shows a comparison between the signal noise ratio SN of the conventional system and the signal noise ratio of the present invention normalized by fS / 2, which is the highest frequency of the output of the conventional ΣΔ AD converter.
It becomes like the table of. That is, according to the method of the present invention, the signal-to-noise ratio SN can be made n / 2 times more advantageous without increasing the operation speed of the analog circuit portion as compared with the conventional method.

The ΣΔ AD converter of the present invention described above can be applied to a 構成 Δ AD converter having a secondary structure. In this case, however, it is necessary to multiply the output of the first-stage integrator 41 by a coefficient k in order to stabilize the operation, as shown in FIG. In this case, it can be stabilized by multiplying by a coefficient of k ≦ 2 / n (6).
If the signal noise ratio SN in this case is SN12, then SN12 = k ² × (4 / n ² ) × 15 / (64 × π ⁴ ) × (fc / fs) ^-5 (7) Here, similarly to FIG. 4, the signal noise ratio SN of the conventional system and the system of the present invention is normalized by the maximum output frequency and compared, as shown in the table of FIG. That is, according to the method of the present invention, the signal-to-noise ratio SN is k
² × (n / 2) ³ times advantage can be obtained.

Next, an example of the aforementioned signal processing circuit A is shown in FIG.
This will be described with reference to the configuration diagram shown in FIG. In the figure, an output S1 of the comparator is connected to one end of an AND circuit 203, and an output of the AND circuit 201 is connected to an input of a trigger generation circuit 202. Trigger generation circuit 202
Is supplied with a clock signal φ0.
The output of 02 is connected as a trigger component signal a to one end of an OR circuit 101 provided inside the trigger control circuit 101 and to the reset terminal RST of the timer circuit 201. The timer circuit 201 receives a clock signal φ1 having a phase opposite to that of the clock signal φ0, and the count-up signal S5 of the timer circuit 201 is connected to the other end of the AND circuit 203. Here, the clock signal φ0 and the lock signal φ1 are signals generated by subjecting the clock signal CLK input to the signal processing circuit A to signal processing and separating the clock signal CLK into two signals.

FIG. 8 shows a signal waveform of each part of the signal processing circuit A thus configured. FIG. 2A shows FIG.
Within a delay time of a predetermined n clocks from the previously generated trigger signal TRG described in
8B shows the operation waveform of the signal processing circuit A when the output changes from low to high, and FIG. 8B shows a predetermined n clocks from the previously generated trigger signal TRG described with reference to FIG. Comparator 1 after a delay time of
2 is an operation waveform of the signal processing circuit A when the output of the signal No. 2 changes from low to high.

In FIG. 8 (a), the signal processing circuit A
When the trigger circuit 202 outputs the trigger component signal a, the timer circuit 201 is reset by this signal, and the counting of the delay time for a preset n clocks is started. This is the timing in FIG.

Thereafter, if the output S1 of the comparator 12 changes from low to high before the timer circuit 201 counts up, the AND circuit 203 outputs the trigger signal because the count-up signal S5 of the timer circuit 201 is still low. The input of circuit 202 is also low. This is the timing in FIG.

Thereafter, when the timer circuit 201 counts up and the count-up signal S5 becomes high,
If the output S1 of the comparator 12 is in a high state, the output of the AND circuit 203 becomes high, and the trigger circuit 202
Becomes high, and the trigger component signal a is output.
This is the timing in FIG.

Next, the operation of FIG. 8B will be described.
In the figure, when a trigger processing circuit 202 outputs a trigger component signal a by a trigger circuit 202, the signal processing circuit A resets the timer circuit 201 by this signal, and sets a preset n
Start counting the delay time for the clock. This is the timing in FIG.

Thereafter, when the timer circuit 201 counts up and the count-up signal S5 becomes high,
If the output S1 of the comparator 12 is not high,
This state is maintained, and when the output S1 of the comparator 12 becomes high next time, the trigger component signal a is output. This is the timing in FIG.

The signal processing circuit A detects the rising edge of the output S1 of the comparator 12 and generates a trigger component signal a by such an operation. Further, the signal processing circuit B is connected to an input of a circuit having the same configuration as that of the signal processing circuit A described here via an inverter, and outputs the output S1 of the comparator 12 via an inverter.
, The falling edge of the output S1 of the comparator 12 is detected and the trigger component signal b is generated.

[0047]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. According to the first and second aspects of the present invention, the operation speed of the digital circuit can be increased without increasing the operation speed of the analog circuit constituting the ΣΔ AD converter by adding the trigger control circuit to the conventional ΣΔ AD converter. It becomes possible.
Accordingly, by increasing the speed of the digital circuit portion which can be easily increased without increasing the speed of the analog circuit which causes an increase in power consumption and cost, ΣΔ
It is possible to improve the signal noise ratio SN of the AD converter. This is because when compared with the conventional ΣΔ AD converter, it is possible to secure the same signal noise ratio SN as the conventional one by using a general-purpose analog circuit having a low operation speed, so that high accuracy and low current consumption are achieved. It can be easily mounted on a required two-wire transmitter such as a vortex flowmeter.

According to the third to sixth aspects of the present invention, since the trigger control circuit can be manufactured with a simple circuit configuration using general-purpose parts, the ΣΔ AD converter can be manufactured at low cost. Is possible.

According to a seventh aspect of the present invention, in the first aspect of the present invention, the trigger control circuit comprises
It is possible to cope with the next ΣΔ AD converter.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a ΣΔ AD converter according to the present invention.

FIG. 2 is a time chart showing signal waveforms of a trigger control circuit.

FIG. 3 is a time chart showing each signal waveform of the ΣΔ AD converter according to the present invention.

FIG. 4 shows a conventional ΣΔAD converter and a ΣΔAD according to the present invention.
It is a comparison table of a converter.

FIG. 5 is a configuration diagram showing one embodiment of a ΣΔ AD converter according to the present invention.

FIG. 6 shows a conventional ΣΔAD converter and a ΣΔAD according to the present invention.
It is a comparison table of a converter.

FIG. 7 is a configuration diagram showing one embodiment of a trigger control circuit according to the present invention.

FIG. 8 is a time chart showing signal waveforms of the trigger control circuit.

FIG. 9 is a configuration diagram illustrating an example of a conventional secondary ΣΔ AD converter.

FIG. 10 is a configuration diagram illustrating an example of a conventional secondary ΣΔ AD converter.

[Explanation of symbols]

 11, 41 Integrator 12 Comparator 13 Flip-flop 14 D / A converter 15, 45 Adder 61 Input terminal 62 Output terminal

Claims (7)

[Claims] A comparator for connecting an input terminal, an adder, and an integrator in series, comparing an output of the integrator with a predetermined value, and outputting a result of the comparison as a 1-bit digital value; Using a flip-flop that holds the output of the comparator in synchronization with a trigger signal, connecting the output signal of the flip-flop to an output terminal,
The output signal is fed back to the adder via a D / A converter to output a pulse density signal corresponding to the input signal.
A ΣΔ AD converter, comprising a trigger control circuit for controlling the timing of generation of a trigger signal given to the flip-flop. 2. The trigger control circuit according to claim 1, wherein the trigger signal of the flip-flop is limited for a preset period of time to suppress the frequency of change of the pulse density signal. Item 4. The ΣΔ AD converter according to Item 1. 3. The trigger control circuit detects a rising edge of an output of the comparator and generates a trigger component signal a. A trigger processing circuit detects a falling edge of an output of the comparator and generates a trigger component signal b. Is driven in accordance with the timing of an externally input clock signal, and the OR signal of the trigger component signal a and the trigger component signal b generated by the signal processing circuit B is output as a trigger signal of the flip-flop. ΣΔ according to claim 1, characterized in that:
AD converter. 4. When the output of the comparator changes from low to high within a delay time corresponding to n clocks of the clock signal, the signal processing circuit A detects the output of the trigger component signal a for n clocks after the previous generation of the trigger component signal a. Trigger component signal a is generated after a delay time of, and when the output of the comparator changes from low to high after n clocks from the previous generation of the trigger component signal a, the trigger component signal a is generated at the clock timing immediately after that. 4. The ΣΔ AD converter according to claim 3, wherein the す る Δ AD converter is configured to perform the following. 5. When the output of the comparator changes from high to low within a delay time of n clocks of the clock signal, the signal processing circuit B outputs the signal for n clocks from the previous generation of the trigger component signal b. A trigger component signal b is generated after a delay time of, and when the output of the comparator changes from high to low after a delay time of n clocks from the previous generation of the trigger component signal a, the trigger component is generated at the clock timing immediately after that. 4. The ΣΔ AD converter according to claim 3, wherein the ΣΔ AD converter is configured to generate a signal b. 6. The ΣΔ AD converter according to claim 3, wherein the signal processing circuit B is configured by adding an inverter to an input of a circuit having the same configuration as the signal processing circuit A. 7. The trigger control circuit according to claim 2, wherein:
The ΣΔ AD converter according to claim 1, wherein the ΣΔ AD converter is applicable to an AD converter.