JP2000243846A - Clock distribution layout method of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor integrated circuit to be lessened in clock skew that causes a malfunction enhancing it in degree of integration without deteriorating it in wiring properties and to be improved in reliability. SOLUTION: A F/F(flip-flop) dedicated layout lattice where the clock input terminals of the F/F as a load are lined up on the same straight line is previously formed (S101), and a cell layout region is divided into sub-regions of the same size (S102). A route driver is arranged at the center of the divided sub-region, relay buffers are uniformly arranged and wired like a tree corresponding to the number of the divided sub-regions, and the F/F is arranged on the layout lattice (S103 to S105). The total capacitance of the clock input terminals of the F/F connected to the relay buffers in a final stage is equalized by controlling the positions of cut lines among the divided sub-regions (S106 and S107), clock signal wirings extending from the output terminals of the relay buffers in a final stage to the clock input terminals of the F/F are radially and rectilinearly connected (S108).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit manufacturing technique, and more particularly to a layout of a clock distribution circuit for supplying a clock signal operating in synchronization with loads such as a plurality of F / Fs (flip-flops) and latches. About the method.

[0002]

2. Description of the Related Art When designing a semiconductor integrated circuit, a circuit for operating loads such as a plurality of F / Fs and latches in synchronization with one clock signal is required in some cases. A layout is required. Conventionally,
As such a layout method, Japanese Patent Application Laid-Open No. H10-229
There is a technique described in JP-A-310-310. In this technique, a library in which clock tree-type clock lines having an equal wiring length are wired in advance is prepared, and an order such as F / F of a target circuit is provided with respect to the clock tree-type clock line that is wired in advance. When test placement is performed with circuit cells overlapped with the last stage of the clock tree, and the next unused clock line is deleted so that the original load of the clock line does not change, and there is an error in the placement and routing results. Has proposed a layout method having a configuration for returning to the test arrangement processing again. The advantage of this technique is that it replaces previously prepared relay buffers and sequential circuit cells, such as F / F, which are arranged at equal distances, makes all clock lines the same wiring length, and completely eliminates clock skew. is there.

[0003] Another technique is disclosed in Japanese Patent No.
No. 5078 describes that once a branch point of a clock wiring path on a binary tree is set, a sibling branch point having a common parent branch point is connected, and R is set at a point on the actual wiring path.
The location where the C delay is balanced is updated as a new parent branch point position, and this is repeated bottom-up to determine a detailed wiring route. Further, in the hierarchical clock distribution method by buffer cell insertion, after determining the detailed position of the buffer cell, detailed wiring is performed by including a detour portion in the path near the buffer cell so that the delay in the same layer is equalized.
Further, a clock distribution method has been proposed in which wiring is performed by a dedicated wiring layer for a portion other than the intra-cluster path. An advantage of the present invention is that it is possible to minimize the skew by equalizing the delay for each layer on the binary tree.

[0004]

However, the above-mentioned prior art has the following problems. In the first prior art, the F / F can be arranged only on the clock tree type clock line prepared in advance, and the number of branches of the output of the relay buffer is limited, so that the arrangement of the F / F is restricted. When the number of F / Fs is increased or when it is desired to arrange F / Fs in some areas like a shift register circuit, the number of relay buffers and the number of connection wirings are increased, and the wiring property is reduced, thereby coping with high integration. Can not. Also, although the clock skew is reduced, the F / Fs are distributed and placed with restrictions on the placement of the F / Fs in order to replace the F / Fs with relay buffers arranged at equal distances. The length of wiring to other cells becomes longer, delays occur in signals other than clocks, delay elements and buffers must be inserted for timing adjustment, and signal wiring needs to be routed extra. Is reduced.

On the other hand, in the second prior art, since a detour wiring is used for delay adjustment for each hierarchy of the binary tree, the detour wiring becomes an extra wiring, and the wiring property is reduced. In addition, since the area where the terminal cells are present is clustered in a grid and the load is adjusted by moving and exchanging the terminal cells between adjacent clusters, the wiring length other than the clock signal increases, and in this respect, the wiring performance decreases. May be. Further, when there are two or more clock signals, the delay is adjusted independently for each system. However, when a plurality of clock signals are to be operated in synchronization, the delay position is adjusted by adjusting the buffer insertion position. Therefore, the delay differs depending on the clock signal, and the delay of two or more clock signals cannot be matched.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a layout method for realizing high integration of a semiconductor integrated circuit, reducing a clock skew which causes a malfunction of the semiconductor integrated circuit without deteriorating wiring properties, and improving reliability. It is to provide.

[0007]

According to a layout method of the present invention, a cell arrangement area is divided into a grid with a predetermined size, and a relay buffer is arranged in a tree form from a root driver in accordance with the number of the plurality of divided areas. Are arranged and routed uniformly, and the positions of the division lines between the division areas are adjusted to evenly arrange the loads connected to the final stage relay buffer. In this case, an arrangement grid dedicated to the load is created so that the clock input terminal positions of the load are aligned on the same straight line, and the output terminals of the relay buffer at the last stage are arranged on the arrangement grid from the output terminals of the loads. The clock signal wiring up to the clock input terminal is radially and linearly connected.

A more specific layout method of the present invention is as follows.
Creating a load-specific placement grid on which the loads are placed, determining the number of placement grids, dividing the placement grid into powers of 2 in each of the vertical and horizontal directions, and providing a route to the plurality of divided areas. Arranging a relay buffer in a tree form from the driver and the root driver and wiring them together; arranging the load using an automatic arrangement tool for each of the divided areas; Calculate the clock input terminal capacity of the load, finely adjust the divided lines of each divided area so that the loads connected to the final-stage relay buffer of each divided area are equal, and adjust the number of the relay buffers. And a step of performing other wiring.

Further, in this case, a step of preparing a load-specific placement grid in which the loads are to be placed and arranging the loads, a step of extracting a range in which the loads are placed, and A step of calculating the number of arrangement grids and dividing the obtained arrangement grid into powers of 2 in each of the vertical and horizontal directions;
Arranging and routing interconnect buffers in the form of a tree from the root driver and the root driver to the plurality of divided areas, and reducing the load by using an automatic arrangement tool for each of the divided areas. Arranging and calculating the clock input terminal capacity of the load in each of the divided areas, and fine-tuning the divided lines of each of the divided areas so that the loads connected to the final-stage relay buffer of each of the divided areas become equal. In addition, the method may include a step of adjusting the number of the relay buffers and a step of performing other wiring.

Further, in the layout method according to the present invention, the fine adjustment of the divided lines and the adjustment of the number of the relay buffers are performed by calculating a total sum of clock input terminal capacitances of loads connected to each final-stage relay buffer. Calculating the average clock input terminal capacity connected to one of the final-stage relay buffers from the sum calculated by the calculation; and calculating the average clock input terminal capacitance connected to a certain final-stage relay buffer. If the sum is not more than の of the average clock input terminal capacitance, the divided line is adjusted so that the load of the divided region is included in the adjacent divided region, and use of the last-stage relay buffer of the divided region is prohibited. And the sum of the clock input terminal capacitances connected to a certain final stage relay buffer is 3/2 or more of the average clock input terminal capacitance. Adjusting the divided lines for dividing the divided area into two and adding a final-stage relay buffer, wherein the sum of the clock input terminal capacitances of the loads connected to each final-stage relay buffer is equal to the average clock input. The divided line is finely adjusted so that the terminal capacitance falls within a range of ± 1/2 of a preset target value.

In the layout method according to the present invention, the cell placement area is divided into a certain size, and the route driver and the relay buffer are equally arranged and wired in a tree form from the root driver according to the number of divided areas. Align clock signal wiring delays between them. Further, the load connected to the relay buffer at the last stage is equalized by adjusting the position of the cut line between the divided areas. The loads are arranged so that the clock input terminal positions of the loads are aligned on the same straight line, and the clock signal wiring from the output terminal of the final stage relay buffer to the clock input terminal of each load is connected radially and linearly. In addition, the difference in the wiring length of the clock signal wiring can be minimized, the clock skew can be reduced, and the extra bypass wiring is eliminated, so that the wiring property is improved. By creating an arrangement grid dedicated to the load, the arrangement of only the origin position of the load is restricted, so that cells other than the load can be freely arranged and high integration can be realized.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. A first embodiment of the present invention will be described with reference to FIG. First, in step S101, a layout grid 1 dedicated to F / F is created such that the clock input terminal positions of the F / F are arranged on the same straight line in the cell layout area as shown in FIG. 2, and the number of layout grids is obtained. . Next, in step S102, the number of grids in the X and Y directions is divided by a power of 2 as shown in FIG. Here, as shown by the bold line in FIG. 3, four 2 × 2 divided areas 10a are given by 2 (= 2).
-10d. At this time, the capacity of the clock input terminal of the F / F arranged in each of the divided areas 10a to 10d is about the driving capacity of the relay buffer to be arranged, and is divided so that the influence of the delay due to the wiring resistance is reduced. Adjust the number. Next, in step S103, as shown in FIG. 4, the root driver 11 is arranged at the center of the cell arrangement area, here, at a position where each of the divided areas 10a to 10d is in contact, and connected to the root driver 11 in the same row. The relay buffers 12 are divided one by one for the four divided regions 10a to 10d so that the divided regions 10a to 10d are equidistant from the route driver 11.
placed in the center of d. Further, in step S104, a wiring 13 is connected from the output of the route driver 11 to the input of each of the relay buffers 12.

In this embodiment, the relay buffer is 1
5B, the route driver 11 has a two-stage configuration of the upper relay buffer 14 and the lower relay buffer 12 with respect to the route driver 11, or a multistage configuration of more than two. In FIG. 5A, as shown in an example of a two-stage configuration, a higher-order relay buffer 14 connected to the route driver 11 is arranged for each of the divided areas 10a to 10d, and each divided area is further divided. Divided area 10
A lower relay buffer 12 connected to an upper relay buffer 14 is connected to each of aa to 10ad, ..., and 10da to 10dd, and each of the relay buffers 14, 12 is arranged and wired.

Next, in step S105, according to the connection information of the circuit to be designed, the load (F / F here) is set in each divided area of the cell arrangement area as shown in FIG. Place cells. At this time, in step S101, the F / F arrangement grid 1 is created. In order to arrange the F / Fs according to this arrangement grid, the F / Fs have the clock input terminal positions on the same straight line. The cells other than the F / F are freely arranged regardless of the arrangement grid dedicated to the F / F.

Subsequently, step S106 is executed as load (F / F) equalization processing. This step S10
6, the details will be described later, but each of the divided areas 10a to 10d
Calculate the sum of the capacitances of the clock input terminals of the F / Fs in each of the sub-regions, fine-tune the cut lines in each divided area, equalize the load connected to the last-stage relay buffer, and Clock signal wiring. After a while
In step S107, unnecessary relay buffers are deleted as long as the load from the root driver to each F / F does not change. Further, in step S108, other signal wiring is performed. This completes the clock distribution layout.

The detailed procedure of the load equalization process in step S106 will be described with reference to the flowchart shown in FIG. In step S201, one final-stage relay buffer, the relay buffer 12 in the embodiment of FIG.
Of the clock input terminal capacity of the F / F connected to
x) and the minimum (Min) target values are set within a range where the delay in the relay buffer 12 does not become too large. Then, in step S202, in each of the divided areas 10a to 10d, the total sum of the clock input terminal capacity of the F / F connected to each of the last-stage relay buffers 12 is calculated. In step S203, the “average clock input terminal capacity” connected to one of the last-stage relay buffers 12 is determined. That is, (average clock input terminal capacity) = (total of clock input terminal capacities of all F / Fs) ÷ (number of last-stage relay buffers) The "sum of input terminal capacitances" is compared with the "average clock input terminal capacitance" obtained above.

According to this comparison, in step S204,
The “sum of the clock input terminal capacitances connected to the final stage relay buffer” is １ ／ of the “average clock input terminal capacitance”
In the following cases, the F / F in the divided area is included in the adjacent divided area, and the use of the last-stage relay buffer of the divided area is prohibited. For example, in the example of FIG. 6, as shown in FIG. 8, the divided area 10a is included in the divided area 10c and integrated, and the use of the last-stage relay buffer 12a arranged in the divided area 10a is prohibited. On the other hand, step S
In 205, when the “sum of the clock input terminal capacitances connected to the final-stage relay buffer” is 3/2 times or more the “average clock input terminal capacitance”, the divided region is divided into two, and the new divided region is divided into two. Generate and add a final-stage relay buffer as shown in FIG. For example, in the example of FIG. 6, as shown in FIG. 8, the divided area 10b is divided into the divided areas 10e and 10f.
And the final stage relay buffer 12b is added to the new divided area 10f. In the method of dividing into two, the sum of the clock input terminal capacitances of the F / F is calculated while moving the cut line of the divided region in the vertical direction and the horizontal direction, and the average clock input terminal capacitance is determined in either the vertical direction or the horizontal direction. , And adopt a closer division method.

Here, in step S206, when the number of final-stage relay buffers is changed by the processing of steps S204 and S205, "the sum of the capacitances of the clock input terminals connected to each final-stage relay buffer" The "average clock input terminal capacitance" is recalculated and compared again as described above. As a result, the “sum of the clock input terminal capacitances connected to each final-stage relay buffer” is set to fall within a range of ２〜 to ／ of the “average clock input terminal capacitance”.

In step S207, the maximum value is extracted from the "sum of the capacitances of the clock input terminals connected to the final-stage relay buffer" obtained for each of the final-stage relay buffers. , (Maximum value) ≦ (average clock input terminal capacitance) + (target value ÷ 2). If this is not satisfied, one region 1 as schematically shown in FIG.
"Average clock input terminal capacitance" including upper, lower, left and right regions 10B to 10E adjacent to 0A is calculated, and all five divided regions including the upper, lower, left, and right sides are closest to the average clock input terminal capacitance. Then, as shown in FIG. 10B, the cut line of the target divided area is moved inward, and this processing is repeated until the maximum value satisfies the condition.

Conversely, a minimum value is extracted from the "sum of the clock input terminal capacitances connected to the final-stage relay buffer" obtained for each of the final-stage relay buffers. Check if (minimum value) ≧ (average clock input terminal capacitance) − (target value ÷ 2). When this condition is not satisfied, as shown in FIG. 10C, the average clock input terminal capacitance including the adjacent upper, lower, left, and right divided regions is calculated, and all five divided regions including the upper, lower, left, and right regions are equal to the average. The cut line of the target divided area is moved outward so as to come closest to the clock input terminal capacitance, and this processing is repeated until the minimum value satisfies the condition. As a result of performing this processing, fine adjustment of the cut line between the divided areas is performed as shown in FIG.

Then, in step S208, each F /
The clock input terminals of the F-th column are connected in a straight line, and the lines are connected to the output terminal of the final-stage relay buffer.
As shown in FIG. 1, the clock signal wiring 15 is radiated from the output terminal of the final stage relay buffer.

As described above, by arranging and wiring the relay buffers evenly, the route driver 11
The delay between the two can be equalized. That is, the clock input terminal capacity of the F / F connected to each final-stage relay buffer is equalized, and the clock input terminals of the F / F are arranged so as to be aligned on the same straight line. A clock signal line is radially connected linearly from the terminal to the clock input terminal of each F / F column, and each F / F
By minimizing the difference in the wiring length between them, the difference between the wiring resistance and the wiring capacitance is also reduced, and the clock skew can be reduced. Further, by controlling the size of the divided area and adjusting the difference between the wiring resistance and the wiring capacitance from the output terminal of the final-stage relay buffer to the clock input terminal of the F / F, a target clock skew can be realized. Furthermore, by aligning the clock input terminal positions of the F / F and connecting the clock signal wiring in a straight line, the clock signal wiring does not meander and wrap around, and the bypass wiring for delay adjustment as in the second conventional example is provided. This eliminates the necessity, and improves the wiring properties without consuming an extra wiring area.

When the positions of the route driver 11 and the relay buffer 12 are determined before arranging other cells, the size of the divided area and the size of the load are adjusted to reduce the delay between a plurality of clock signals. Adjust the skew,
A plurality of clock signals can be operated in synchronization. Also, if the position of the last-stage relay buffer, the size of the divided region, and the size of the load are determined, the skew of the clock signal can be adjusted. It becomes possible.

Further, since only the cell origin position of the F / F is fixed and the other cells can be freely arranged, there is no restriction on the arrangement of the F / F as in the first conventional example, and the number of relay buffers used is reduced. Therefore, high integration is possible. Here, the fact that the number of relay buffers can be reduced in the present invention will be described in comparison with the first conventional example and the second conventional example. The reason why high integration in the first conventional example is difficult is that
Since the F / Fs are overlapped and arranged at the last stage of the clock tree, at least the total number of the F / Fs is required for the last stage relay buffers. Since each relay buffer branches in three directions, the number of relay buffers is reduced. That is, the number of relay buffers is tripled with each increase. The number of relay buffers at the final stage is 2 × 3 ⁿ and needs to be equal to or more than the total number of F / Fs.
2 + 2 × (3+... +3 ^{n -1} +3 ⁿ ), and the number of F / F = 1
In the case of 000, the number of final stage relay buffers is 2 × 3 ⁶ =
1458 are required, and the total number of relay buffers is 2 + 2
× (3 ¹ +3 ² +3 ³ +3 ⁴ +3 ⁵ +3 ⁶ ) = 2186
In this case, the last stage is replaced with F / F, and unused buffers that are not deleted remain, so that the total number of relay buffers actually arranged is 2186-1000 = 1186 at the maximum. In the minimum case, 1000 F / Fs are connected, and the minimum number of relay buffers required at each stage to equalize the load on each relay buffer is 1000 → 334 → 112 → 38 → 13
→ 5 → 2, and the total number of relay buffers after deleting unnecessary relay buffers is 2 + 6 +
15 + 39 + 114 + 336 + 2 = 514.

In order to correspond to the first embodiment of the present invention, when the first conventional example is branched into four directions, the number of final stage relay buffers is 45 ⁵ = 1024, which is actually arranged. The maximum number of relay buffers is 4 + 16 + 64
+ 256 + 24 = 364. In the minimum case, the number of relay buffers required for each stage is 1000 → 250 → 63 → 16
→ 4, and the total number of relay buffers for which the load is not changed is 4 + 16 + 64 + 252 = 336. In the first embodiment, although it depends on the driving capacity of the relay buffer, assuming that the relay buffer can drive 40 F / Fs, the number of final-stage relay buffers is 1000１０００4
Since 0 = 25 or more is required, 4 ³ = 64, and
The total number of relay buffers actually arranged is 4 + 1 at the maximum.
In the case of 6 + 64 = 84, which is the minimum, the number of relay buffers required for each stage is 1000 → 25 → 7 → 2, and the total number of relay buffers for which the load is not changed is 2 + 8 + 28 = 38.
Individual. The above is summarized in Table 1 below. By using the present invention, the number of relay buffers can be significantly reduced,
It can be seen that high integration can be realized because there is no restriction on the arrangement of the F / F.

[0026]

[Table 1]

Next, a second embodiment of the present invention will be described.
In the first embodiment, the procedure for distributing the clock signal of one system has been described. In the second embodiment, the processing for distributing the clock signal of two or more systems will be described. In the case of two or more systems, as shown in FIG. 12, the route drivers 11A and 11B
The relay buffers 12A and 12B are arranged and wired adjacent to each other, and thereafter, the same processing procedure as that of the first embodiment is performed on each relay buffer, thereby adjusting the delay and skew of the clock signals of a plurality of systems. Becomes possible. When it is not necessary to match the delays of the clock signals of a plurality of systems, the arrangement and wiring can be performed by changing the number of stages of the relay buffer according to the load to be driven.

In the first embodiment, when the layout position is determined for each layer of the circuit connection information and the layout is performed, and the F / Fs are concentrated in a part of the cell layout area, the root driver is used in the first embodiment. At the center of the terminal F /
It is conceivable that the wiring length up to F increases and the delay of the entire clock signal increases. A third embodiment will be described as a method for solving this. FIG. 13 is a flowchart illustrating a clock signal distribution processing procedure according to the third embodiment of the present invention. First, in step S301, the layout grid 1 dedicated to the F / F is created such that the clock input terminal positions of the F / F are aligned on the same straight line in the cell layout area as shown in FIG. 2, and the number of layout grids is obtained. Next, in step S302, all cells are automatically arranged. Step S3
At 03, the range in which the F / Fs are arranged is extracted, and the arrangement grid within the range is divided into powers of 2 in each of the vertical and horizontal directions. Next, at step S304, a route driver and a relay buffer are arranged, and at step S305, cell overlap is removed. Further, step S30
At 6, the route driver and the relay buffer are wired. In the subsequent steps S307 to S309, the load is equalized and other wiring is performed in the same procedure as in the first embodiment, that is, in the same procedure as step S106 in FIG. FIG. 14 shows a state in which the route driver and the relay buffer according to the third embodiment of the present invention are arranged and wired.

Here, in each of the above embodiments, an example is shown in which an F / F is used as a load, but the present invention is not limited to the F / F, and a latch or the like operated based on a clock signal may be used. The present invention can be similarly applied to a semiconductor integrated circuit having a circuit configuration in which a plurality of loads including circuit elements are connected in a tree shape and operated synchronously.

[0030]

As described above, according to the present invention, a cell arrangement area is divided into a grid with a fixed size, and a relay buffer is arranged and wired evenly in a tree form from a root driver according to the number of divided areas. And, by adjusting the cut line position between the divided regions, the load connected to the final stage relay buffer is equalized, so that the clock skew is reduced while realizing high integration of the semiconductor integrated circuit, A highly reliable clock distribution layout of a semiconductor integrated circuit can be realized. Also, an arrangement grid dedicated to the load is created so that the clock input terminal positions of the load are aligned on the same straight line, and the clocks of the loads arranged on the arrangement grid from the output terminals of the final stage relay buffer are arranged. Since the clock signal wiring to the input terminal is connected radially and linearly, the clock signal wiring does not meander and wrap around, and the clock distribution layout of the semiconductor integrated circuit with high wiring performance without consuming extra wiring area. Can be realized.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a processing procedure according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of an arrangement grid dedicated to F / F as a load.

FIG. 3 is a diagram showing a state where a cell arrangement area is divided into powers of 2;

FIG. 4 is a diagram showing a state in which a route driver and a relay buffer are arranged and wired.

FIG. 5 is a simplified diagram showing an example of a tree structure in which relay buffers are inserted in multiple stages.

FIG. 6 is a diagram showing a state where all elements are arranged.

FIG. 7 is a flowchart illustrating a processing procedure for equalizing loads according to the first embodiment of the present invention.

FIG. 8 is a diagram showing an initial state after reconstruction of a divided area.

FIG. 9 is a diagram illustrating a state after load adjustment after reconstructing a divided area.

FIG. 10 is a simplified diagram of a load adjustment method for a divided area.

FIG. 11 is a diagram illustrating a connection example between an output terminal of a final-stage relay buffer and a clock input terminal of an F / F.

FIG. 12 is a diagram illustrating a state in which a route driver and a relay buffer according to a second embodiment of the present invention are arranged and wired;

FIG. 13 is a flowchart illustrating a processing procedure according to the third embodiment of the present invention.

FIG. 14 is a diagram showing a state in which a route driver and a relay buffer are arranged and wired according to a third embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Arrangement grid dedicated to load (F / F) 10a to 10d Divided area 10aa to 10ad,..., 10da to 10dd Divided area 11, 11A, 11B Route driver 12, 12A, 12B Last stage relay buffer 13 Route driver and relay buffer 14 Relay buffer 15 Signal wiring

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA06 DA02 FA12 5F064 AA04 BB19 BB26 DD03 DD04 DD13 DD14 DD18 DD25 EE08 EE16 EE42 EE43 EE47 EE54 HH06

Claims (5)

[Claims] 1. A cell arrangement area is divided into a grid with a certain size, and a relay driver is arranged and wired evenly in a tree form from a root driver according to the number of the divided areas. A clock distribution layout method for a semiconductor integrated circuit, characterized in that the positions of divided lines are adjusted to evenly distribute loads connected to the final stage relay buffer. 2. An arrangement grid dedicated to the load is created so that the clock input terminal positions of the load are arranged on the same straight line, and the output lattice of the last stage is arranged on the arrangement lattice from the output terminal of the relay buffer. 2. The clock distribution layout method for a semiconductor integrated circuit according to claim 1, wherein clock signal wirings to a clock input terminal of the load are connected radially and linearly. 3. A step of creating an arrangement grid dedicated to loads on which loads are arranged, calculating the number of arrangement grids, and dividing the arrangement grid into powers of 2 in each of the vertical and horizontal directions;
Arranging and routing interconnect buffers in the form of a tree from the root driver and the root driver to the plurality of divided areas, and reducing the load by using an automatic arrangement tool for each of the divided areas. Arranging and calculating the clock input terminal capacity of the load in each of the divided areas, and fine-tuning the divided lines of each of the divided areas so that the loads connected to the final-stage relay buffer of each of the divided areas become equal. And a step of adjusting the number of the relay buffers and a step of performing other wiring. 4. A step of creating an arrangement grid dedicated to loads on which loads are arranged, arranging the loads, extracting a range in which the loads are arranged, and the number of arrangement grids in the extracted range. And dividing the determined arrangement grid into powers of 2 in each of the vertical and horizontal directions, arranging a relay driver in a tree shape from the root driver and the root driver for the divided plurality of divided areas, and interconnecting them. And allocating the load using an automatic placement tool for each of the divided areas; calculating a clock input terminal capacity of a load in each of the divided areas; Finely adjusting the divided lines of each divided region so that the loads connected to the divided regions are equal, and adjusting the number of the relay buffers, and a process of performing other wiring. And a clock distribution layout method for a semiconductor integrated circuit. 5. The fine adjustment of the division line and the adjustment of the number of relay buffers are performed by calculating a total sum of clock input terminal capacitances of loads connected to the final-stage relay buffers, and by the calculation. Calculating an average clock input terminal capacitance connected to one of the last-stage relay buffers from the sum; and calculating a sum of the clock input terminal capacitances connected to a certain last-stage relay buffer to the average clock input terminal capacitance. When the value is equal to or less than 1/2, a step of adjusting the divided line so that the load of the divided area is included in the adjacent divided area and prohibiting use of the last-stage relay buffer of the divided area; When the sum of the connected clock input terminal capacitances is 3/2 or more of the average clock input terminal capacitance, the division line for dividing the divided region into two is adjusted. And adding a final-stage relay buffer, the sum of the clock input terminal capacitances of the loads connected to each final-stage relay buffer is added to the average clock input terminal capacitance by ± 1 / １ ／ of a preset target value. 5. The clock distribution layout method for a semiconductor integrated circuit according to claim 3, wherein the division line is finely adjusted so as to fall within a range of 2.