JP2000242754A - Ic card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To insure a stable data writing operation to a built-in EEPROM even when power supply energy is insufficient when a non-contact type IC card is made to be separated from a host. SOLUTION: This non-contact type IC card includes an IC chip where an antenna coil performing the transmission and reception of an RF signal, a semiconductor memory and a control circuit are formed. In such a case, the IC chip contains a circuit 82 generating an interval power supply voltage from an RF signal input, a circuit 85 restoring a received data signal, a circuit 84 generating a system clock, an EEPROM 87c, a circuit 12 which receives an internal power supply and generates a boosted voltage for EEPROM supply, a detection circuit 11 which detects when the internal power supply voltage falls below a fixed value and outputs a detection flag and a control circuit 15 which controls so that data rewriting to the EEPROM can not be performed when the detection flag signal is received.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card, and more particularly to an internal power supply voltage drop detecting circuit, a power supply boosting circuit, and a random number generating circuit. It is used for a contact-type card or a contact-type IC card.

[0002]

2. Description of the Related Art FIG. 7A shows a non-contact tag identification (RadioFrequency Identif) for transmitting and receiving data using radio waves.
1 shows an example of the overall configuration of a communication (RFID) system.

[0003] This RFID system comprises a host comprising a personal computer, a controller, an antenna and the like, and a non-contact tag called a transponder or a data carrier.

As shown in FIGS. 7 (b) and 7 (c), a non-contact type tag includes an antenna coil 71 for both power reception and data reception / transmission, and a monolithic RFID chip 72 in which a memory and an ASIC are integrated into one chip. , And is hereinafter referred to as a wireless card.

According to the above-described RFID system, the host transmits commands and data on a carrier signal of a radio wave as necessary, and the wireless card generates necessary power based on the carrier signal to generate data. Since information is returned to the host side for use in writing, reading, and transmission of data, a battery is unnecessary.

[0006] Therefore, the host can use the RFID system for management of entry and exit of a person by reading the stored contents of the memory of the wireless card in a non-contact manner using radio waves and rewriting the contents of the memory. It is.

[0007] For example, a ticket gate with a wireless card for a commuter pass in a clothes pocket, a ticket with a wireless card, and a running, so that it is not necessary to stop at a tollgate on an expressway without having to stop. Applications such as monitoring and managing the entrance and exit of parking lots without human intervention are conceivable.
It can also be used to manage the behavior of livestock and migratory fish.

FIG. 8 specifically shows a conventional example of the wireless card shown in FIG.

That is, the antenna coil 71 is connected to an externally input radio wave (for example, A-wave modulated by a data signal).
LC circuit (L) that detects an SK signal and generates an RF signal
Acts as an inductance, and C acts as a capacitance.

The chip 72 includes an internal power supply generating circuit 82 for rectifying, smoothing, and converting the RF signal input from the antenna coil to the RF signal input terminal 81 to generate an internal power supply (DC voltage) of the wireless card. A power-on circuit 83 for detecting a rise of the power supply voltage generated by the internal power supply generation circuit and outputting a power-on signal; a waveform shaping of the RF signal input; A clock generation circuit 84 for generating the clock signal;
A data demodulation circuit 85 for restoring a command signal and a data signal by filtering the F signal input, a transmission pulse generation circuit 86, a semiconductor memory unit 87, and a control circuit 88 are provided.

The control circuit 88 has a CPU (central processing unit) (or control logic circuit), and receives the internal power supply and a system clock signal.

The transmission pulse generating circuit 86 is provided with the RF
For example, an NMOS transistor connected between the signal input terminal 81 and the ground potential terminal is connected, and transmission data is given to a gate of the gate from a transmission data output port of the CPU 88.

The semiconductor memory unit 87 has a ROM (read only memory) storing programs and fixed data.
87a, RAM (random access memory) 87b for temporarily storing data, nonvolatile memory and memory address selection circuit 87d capable of storing data for a long period of time
including.

As the nonvolatile memory, for example, EEP
ROM (electrically erasable / rewritable memory) or F
A RAM (ferroelectric memory) is used. In this example, an EEPROM 87c that requires a boosted voltage for data rewriting (erasing and writing) is used. Correspondingly, a power supply boosting circuit 89 for receiving the internal power supply and generating the boosted voltage is provided.

As described above, when the wireless card is used, the wireless card is approached to the host (read / write side) for transmitting radio waves to receive the supply of energy and to exchange data.
Write data to

At this time, when the wireless card is close to the host, the supplied electric field is strong, and the EEPRO
There is no danger of power shortage in the middle of writing data to M87c, but when the wireless card moves away from the host, the supplied electric field weakens, and in the middle of data writing, power supply becomes insufficient and the writing operation is stopped. There was a problem that the user had to do this.

As an example of this measure, the conventional EEP
By adding a function of checking whether or not the power supply voltage of the wireless card does not drop before the regular writing operation, the wireless card is not actually stored in the ROM 87c but performing a pseudo write operation. There is a way to maintain stable operation of

However, such a method has a problem that extra time is required for writing data to the wireless card.

As another example of the above countermeasure, there is a method of detecting the power supply voltage generated by the internal power supply generation circuit 82 and stopping the data writing operation to the EEPROM 87c when the power supply voltage drops below a certain level.

However, such a method has a problem in that the response to the power supply voltage drop tends to be delayed due to the response delay of the internal power supply generation circuit 82.

On the other hand, the boosting characteristic of the power supply boosting circuit 89 for supplying a pulsed boosted voltage to the EEPROM 87c is that the rising and falling slopes are relatively gentle as shown in FIG. is important. The reason is that if the rising of the pulse-like boost voltage is steep, energy shock is applied to the memory cell of the EEPROM 87c, and the memory cell is damaged, and the number of rewriting of the EEPROM 87c is greatly reduced (for example, 10 ⁵ order). To 10 ⁴ orders).

Therefore, conventionally, as shown in the boosting characteristic shown in FIG. 9, the rising and falling slopes of the pulsed boosted voltage are set to be relatively gentle. There is a problem that it takes extra time and data processing time.

Such a problem is caused by a contact type IC.
The same applies to the case where the boosting characteristic of the power boosting circuit for supplying the boosted voltage to the EEPROM incorporated in the card is as shown in FIG.

On the other hand, for example, when generating a random number signal to control the generation timing of identification number data,
Since the random number signal is generated by software processing using the CPU 88, the random number is not always generated irregularly. That is, if the initial values at the start of random number generation are made to match, the same random number is generated.

In general, a random number signal is used for various purposes in an IC card. For example, a random number signal is generated in a contact type IC card by using a CPU to control writing of encryption key data. In such a case, the above-mentioned problem still exists.

[0026]

As described above, when the wireless card moves away from the host, the electric field supplied becomes weaker, the power supply energy becomes insufficient during data writing, and the writing operation must be stopped. The conventional countermeasures to prevent such a problem are that the processing time for writing data to the wireless card takes extra time, or the response to the power supply voltage drop tends to be delayed due to the response delay of the internal power supply generation circuit. There was a problem.

The conventional IC card has a built-in EE
Due to the boosting characteristic of the power supply boosting circuit for supplying the boosted voltage to the PROM, there is a problem that extra data writing time and extra data processing time are required.

Also, in the conventional IC card, the random number is not always generated irregularly because the built-in random number signal generation circuit generates a random number signal by software processing by the CPU. There was a problem.

The present invention has been made in order to solve the above problems, and ensures a stable data write operation to a built-in EEPROM even when power supply energy is insufficient during data write as the distance from the host increases. An object of the present invention is to provide a non-contact type IC card to be obtained.

Further, the present invention provides an IC card capable of improving a boosting characteristic of a power supply boosting circuit for supplying a pulsed boosted voltage to a built-in EEPROM and shortening a data writing time and a data processing time. The purpose is to do.

Another object of the present invention is to provide an IC card which can generate a random number signal irregularly by hardware processing by a built-in random number signal generation circuit.

[0032]

According to a first aspect of the present invention, there is provided a non-contact type IC card including an antenna coil, a semiconductor memory, and an integrated circuit chip on which a control circuit is formed for both receiving power and transmitting and receiving data. In the IC card, the integrated circuit chip includes an internal power supply generating circuit for generating an internal power supply voltage from a high-frequency signal input from the antenna coil, and a data demodulation circuit for restoring a received data signal from the high-frequency signal input from the antenna coil A clock generation circuit that generates a system clock signal based on a high-frequency signal input from the antenna coil; an electrically erasable / rewritable memory; and a memory for receiving the internal power supply voltage and supplying the memory to the memory. A power supply booster circuit for generating a boosted voltage, and detecting when the internal power supply voltage drops below a certain value; An internal power supply voltage drop detection circuit that outputs a lag signal; and operates by receiving the internal power supply voltage, and controls so that data can be rewritten to the memory during a period in which the detection flag signal is not received. A control circuit for controlling so that rewriting of data in the memory becomes impossible when a flag signal is received.

A second IC card according to the present invention comprises an electrically erasable / rewritable memory, a power supply boosting circuit for receiving a power supply voltage, boosting the power supply voltage in response to a clock signal, and supplying the boosted voltage to the memory. Generating a clock signal based on a system clock signal, generating a first clock signal having a first cycle at the beginning of the rising of the boosted voltage, and thereafter generating a first clock signal having a first cycle longer than the first cycle. A boost clock generating circuit that generates a second clock signal having a cycle of 2; and a control circuit that operates in response to the power supply voltage and controls rewriting of data in the memory. In addition, the supply of the clock signal has a step-up characteristic in which the slope becomes steep at the initial stage when the boosted voltage rises, and thereafter becomes gentler thereafter.

According to the third IC card of the present invention, a first clock signal having a first frequency is input to a data input terminal of a first stage, and a second clock signal having a second frequency lower than the first frequency. A shift register composed of a plurality of stages of shift circuits for inputting the clock signal to the shift clock input terminal of each stage, and a data register composed of a plurality of latch circuits for latching the output of each stage of the shift register at a predetermined timing. A control circuit for controlling the latch timing of the data register.

The fourth IC card according to the present invention comprises a third IC card.
The card includes a first clock generation circuit for generating the first clock signal and a second clock generation circuit for generating a second clock signal.

A fifth IC card according to the present invention comprises a fourth IC card.
In the card, the first clock generation circuit and the second clock generation circuit are also used as a clock generation circuit used for another purpose.

A sixth IC card according to the present invention comprises a third IC card.
In the card, at least one of the first clock signal and the second clock signal uses a system clock signal.

A seventh IC card according to the present invention comprises a sixth IC card.
In the card, it is preferable that the system clock signal is used as the first clock signal, and a frequency dividing circuit that divides the system clock signal to generate a second clock signal is used as the second clock generating circuit. Features.

[0039]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an example of an IC chip of a wireless card according to the first embodiment of the present invention.

The wireless card shown in FIG. 1 is used as a non-contact type tag of the RFID system described above with reference to FIG. 7, and is different from the conventional wireless card described above with reference to FIG. (1) Internal power supply voltage drop detection circuit 11
Are added, (2) the configuration and the boost characteristic of the boost clock generation circuit 13 for supplying the clock signal to the power supply boost circuit 12, and (3) the configuration of the random number signal generation circuit 14 are different, and the others are almost the same. It is.

That is, the wireless card shown in FIG. 1 has a monolithic RFID chip 10 in which a memory and an ASIC are integrated into one chip, and an antenna coil 71 (for example, a 13.57M input from outside, which receives and transmits power and receives / transmits data).
(Which acts as an LC circuit that detects RF radio waves and generates an RF signal).

The monolithic RFID chip 10 includes:
An internal power supply generation circuit 82 for rectifying, smoothing, and constant voltage the RF signal input from the antenna coil to the RF signal input terminal 81 to generate an internal power supply (DC voltage) of the wireless card.
A power-on circuit 83 for detecting a rise of a power supply voltage generated by the internal power supply generation circuit and outputting a power-on signal; a waveform shaping of the RF signal input; Signal (13.5 in this example)
7 MHz), and a clock generation circuit 84 for generating the R
A data demodulation circuit 85 for filtering an F signal input to restore a command signal and a data signal; a transmission pulse generation circuit 86; a semiconductor memory unit 87;
4, a control circuit 15 is provided.

The control circuit 15 has a CPU or a control logic circuit, and receives the internal power supply and a system clock signal.

The transmission pulse generation circuit 86 is provided with the RF
For example, an NMOS transistor connected between the signal input terminal 81 and the ground potential terminal is connected, and the transmission data is supplied from the transmission data output port of the control circuit 15 to its gate.

The semiconductor memory unit 87 includes a ROM (read only memory) 8 storing programs and fixed data.
7a, a RAM (random access memory) 87b for temporarily storing data, a nonvolatile memory (EEPROM or FRAM) capable of storing data for a long time, and a memory address selection circuit 87d.

In this embodiment, an EEPROM 87c that requires a boosted voltage for rewriting (erasing and writing) data is used as the nonvolatile memory. Correspondingly, a power supply booster circuit 12 for receiving the internal power supply and generating the boosted voltage is provided.

Further, a boosting clock generation circuit 13 for supplying a clock signal to the power supply boosting circuit 12 and a detection flag signal for detecting when the internal power supply voltage falls below a predetermined value as the external input level decreases. An internal power supply voltage drop detection circuit (external input level drop detection circuit) 11 for outputting the detection flag and inputting the detection flag to the flag input port of the control circuit 15 is provided.

The internal power supply voltage drop detection circuit 11 includes a current detection resistor 111 inserted in a signal path between the RF signal input terminal 81 and the internal power supply generation circuit 82, and a band gap receiving the internal power supply. A bandgap reference power supply 112 for generating a reference voltage, and the internal power supply is used as an operation power supply, and a voltage drop (current detection voltage) generated in the current detection resistor 111 is compared with a bandgap reference voltage.
A voltage comparison circuit 1 that detects when the internal power supply voltage drops below the bandgap reference voltage and outputs a detection flag signal.
13.

The control circuit 15 allows data writing to the EEPROM 87c while the detection flag signal is not input.
When the wireless card is separated from the host and the electric field supplied from the host is weakened to the extent that the power energy required for writing data to the M87c is insufficient, the EEPROM is determined.
It has a control function to stop the operation of writing data to 87c.

On the other hand, the power supply boosting circuit 12 comprises, for example, a switch element SW group and a capacitor C group as shown in FIG. 2, and the switch element SW group is switch-controlled by complementary clock signals φ and / φ. . Since this configuration and operation are well known, description thereof will be omitted, but the boosted voltage is controlled according to the cycle of the clock signal.

The boost clock generation circuit 13
Is configured as shown in FIG. 3, for example, and uses an internal power supply voltage as an operation power supply and generates a clock signal based on the system clock signal.

That is, the boosting clock generation circuit 13 shown in FIG. 3 includes a timing counter 131 for generating a switching timing signal for inverting a logic level after counting the system clock signal input by a predetermined number, and the system clock signal input. Binary counter 132 to count
And a selector 133.

The selector 133 converts a complementary signal having a first cycle and a complementary signal having a second cycle output from two different circuit stages of the binary counter 132 into a logic of a switching timing signal of the timing counter 131. Switching is selected according to the level, and the first clock signal φ1, / φ1 or the second clock signal φ2, /
Output as φ2.

That is, as shown in FIG. 4, boost clock generation circuit 13 generates first clock signals φ1 and / φ1 having the first cycle at the beginning of the rise of the internal power supply voltage, and thereafter. Second cycle (longer than the first cycle)
To generate the second clock signals φ2 and / φ2.

The clock signal φ1, / φ1 or φ2, / φ2 whose cycle is controlled in this manner is supplied to the power supply booster circuit 12.
5, the boosted voltage output from the power supply boosting circuit 12 has a steep slope at the beginning of the rise, as shown in FIG. (Including the area near the completion) almost has a step-up characteristic in which the slope becomes gentle.

Therefore, when data is written to the EEPROM 87c, the impact on the EEPROM 87c can be suppressed because the voltage changes gently in the vicinity of an increase in the boosted voltage. Processing time can be reduced.

The means for controlling the cycle of the clock signal output from the boosted clock generation circuit 13 is not limited to the above embodiment, and the means for controlling the boosting characteristic of the boosted voltage output from the power supply boosting circuit 12 Is not limited to the above embodiment.

On the other hand, the random number signal generation circuit 14 generates a random number signal used for controlling the generation timing of the identification number data by hardware, for example.
For example, it is configured as shown in FIG.

That is, in FIG. 6, a first clock generation circuit 61 generates a first clock signal CK1 having a first frequency (for example, a frequency in the range of 1 to several tens of MHz) and a second clock signal CK1. The generation circuit 62 generates a second clock signal CK2 having a second frequency sufficiently lower than the first frequency.

In this case, each of the clock generation circuits 61 and 62
The circuit size of the chip can be increased by also using a clock generation circuit having another purpose used in another part of the wireless card, or by using an external clock signal input as at least one of the clock signals. May be suppressed.

For example, when the system clock signal input is used as the first clock signal CK1, the first clock generation circuit 61 is omitted and the system clock signal input is divided by the second clock generation circuit 62. Then, a frequency dividing circuit (not shown) for generating the second clock signal CK2 may be used.

Alternatively, when the system clock signal input is used as the second clock signal CK2, the second clock generation circuit 62 is omitted, and the system clock signal input is multiplied by the first clock generation circuit 61. Then, a multiplying circuit for generating the first clock signal CK1 may be used.

The first clock signal CK1 is input to a first stage data input terminal D of a shift register 63 composed of a plurality of (n) stages of shift circuits (the number n of stages is determined by the number of digits of a random number to be generated). The second clock signal CK2 is input to the shift clock input terminal CK of each stage.

In this case, the frequency of the second clock signal CK is sufficiently lower than that of the first clock signal CK1, and the frequency of the second clock signal CK is different from that of the first clock signal (the phase is different).
2, the timing at which the first clock signal CK1 is fetched is controlled, so that a random number signal (uncorrelated data) is generated at each stage output of the shift register 63.

If the frequency relationship between the first clock signal CK1 and the second clock signal CK2 is opposite to the above, all the outputs of the shift register 63 become "H" or "L". And a random number signal is not generated.

The output of each stage of the shift register 63 is n
Input to the data register 64 composed of latch circuits,
It is latched by a latch signal supplied from the control circuit 15 at a predetermined timing. This data register 64
(Random number signal) is output to the data bus via an output gate circuit 65 controlled by an output enable signal supplied at a predetermined timing from the control circuit 15 and used.

According to the random number signal generation circuit shown in FIG. 6 as described above, the random number signal is generated irregularly and the generation timing of the identification number data is controlled even though the hardware configuration is very simple. , It is possible to generate encryption key data having a large number of bits.

In the above embodiment, the radio wave transmitted to and received from the host is an AS signal amplitude-modulated by the data signal.
Although the case where the signal is a K signal is shown, the present invention is not limited to this, and the present invention can be applied to a case where the signal is an FSK signal frequency-modulated by a data signal.

Although the application of the internal power supply voltage lowering circuit 11 in the above embodiment is limited to a non-contact type IC card, the power supply booster circuit 12, booster clock generation circuit 13, and random number signal generation circuit 14 The present invention can be applied not only to a contact type IC card but also to a contact type IC card.

[0071]

As described above, according to the present invention, even if power supply energy becomes insufficient during data writing as the distance from the host increases, the built-in EEPROM can be used.
A non-contact type IC card which can guarantee a stable data write operation for the IC card.

According to the present invention, the built-in EEPR
It is possible to provide a contact type or non-contact type IC card capable of improving a boosting characteristic of a power supply boosting circuit for supplying a boosted voltage to the OM and shortening a data writing time and a data processing time.

Further, according to the present invention, it is possible to provide a contact type or non-contact type IC card which can randomly generate a random number signal by hardware-based processing by a built-in random number signal generation circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of an IC chip of a wireless card according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a power supply boosting circuit in FIG. 1;

FIG. 3 is a circuit diagram showing an example of a boost clock generation circuit in FIG. 1;

4 is a waveform chart showing an example of an output signal of the boost clock generation circuit of FIG.

FIG. 5 is a waveform chart showing an example of a boosted voltage when the clock signal of FIG. 4 is supplied to the power supply boosting circuit of FIG. 2;

FIG. 6 is a circuit diagram showing an example of a random number signal generation circuit in FIG. 1;

FIG. 7 is a block diagram showing an example of a configuration of a non-contact type tag identification system (RFID system).

8 is a circuit diagram specifically showing a conventional example of an internal circuit of the wireless card in FIG. 7;

FIG. 9 is a waveform chart showing boost characteristics of the power boost circuit in FIG. 8;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... RFID chip, 11 ... Internal power supply voltage drop detection circuit, 12 ... Power supply boost circuit, 13 ... Boost clock generation circuit, 14 ... Random number signal generation circuit, 15 ... Control circuit, 71 ... Antenna coil, 81 ... RF signal input terminal 82, an internal power supply generation circuit, 83, a power-on circuit, 84, a clock generation circuit, 85, a data demodulation circuit, 86, a transmission pulse generation circuit, 87, a semiconductor memory unit, 87c, an EEPROM.

Claims (5)

[Claims] 1. A non-contact type IC card including an antenna coil for receiving power and transmitting and receiving data and an integrated circuit chip on which a semiconductor memory and a control circuit are formed, wherein the integrated circuit chip includes: An internal power supply generation circuit that generates an internal power supply voltage from a high-frequency signal input from the antenna coil; a data demodulation circuit that restores a received data signal from a high-frequency signal input from the antenna coil; and a high-frequency signal input from the antenna coil. A clock generation circuit that generates a system clock signal by using the same, an electrically erasable and rewritable memory, a power supply booster circuit that receives the internal power supply voltage and generates a boosted voltage to be supplied to the memory, Internal power supply voltage drop that detects when the power supply voltage drops below a certain value and outputs a detection flag signal A detection circuit, which operates upon receiving the internal power supply voltage, controls so that data can be rewritten to the memory during a period in which the detection flag signal is not received, and controls the memory when receiving the detection flag signal. An IC card, comprising: a control circuit for controlling data rewriting to be impossible. 2. The IC card according to claim 1, wherein the internal power supply voltage drop detection circuit includes a current detection resistor inserted in a signal path between a terminal to which the high-frequency signal is input and the internal power supply generation circuit. A bandgap reference power supply that receives the internal power supply voltage and generates a bandgap reference voltage; and compares a current detection voltage generated in the current detection resistor with the bandgap reference voltage, and determines that the internal power supply voltage is a bandgap reference. An IC card, comprising: a voltage comparison circuit that detects when the voltage drops below a voltage and outputs the detection flag signal. 3. A memory capable of electrically erasing and rewriting, a power supply boosting circuit for receiving a power supply voltage, boosting the power supply voltage according to a clock signal and supplying the boosted power supply to the memory, and a system clock signal. Generating the clock signal, generating a first clock signal having a first cycle at an initial stage when the boosted voltage rises, and then generating a second clock signal having a second cycle longer than the first cycle. A boost clock generation circuit that generates a clock signal; and a control circuit that operates in response to the power supply voltage and controls rewriting of data in the memory. The power supply booster circuit is supplied with the clock signal. Accordingly, an IC card having a boosting characteristic in which the slope becomes steep at an early stage when the boosted voltage rises, and thereafter becomes gentler thereafter. 4. The IC card according to claim 3, wherein the boost clock generation circuit generates a switching timing signal for inverting a logic level after counting a predetermined number of system clock signal inputs, and the system clock signal. A binary counter for counting inputs, and a signal having a first cycle and a signal having a second cycle output from two different circuit stages of the binary counter are switched according to a logic level of a switching timing signal of the timing counter. A selector for selecting and outputting as a first clock signal or a second clock signal. 5. A first clock signal having a first frequency is input to a first stage data input terminal, and a second clock signal having a second frequency lower than the first frequency is shifted by each stage. A shift register including a plurality of stages of shift circuits input to a clock input terminal, a data register including a plurality of latch circuits for latching the output of each stage of the shift register at a predetermined timing, and controlling a latch timing of the data register An IC card, comprising: