JP2000236086A - Field-effect transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce contact resistance of a field-effect transistor extending from cap layer to a channel layer. SOLUTION: A superlattice layer 110 is laminated onto the upper part of an electronic supply layer (Schottky layer) via a Schottky gate contact layer 109, thus reducing the bending of a conduction band which is generated on an interface to a GaAs embedded layer 111, and hence reducing sheet resistance at the part. Also, since the superlattice layer 110 is scraped when a gate recess is formed, ϕB (the height of the Schottky barrier in units of electron volt) that becomes effective on the formation of the Schottky layer is set to Al0.2Ga0.8 As, thus reducing the on-resistance by 0.1 Ωmm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field-effect transistor (Field Effect Transistor).
r; “FET”) and a method of manufacturing the same, and more particularly, to a heterojunction field-effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art An example of this kind of conventional technology is "Electronic Information Communication Society 1996 Electronics Society Conference Park Papers Collection 2: Naoto Yoshida, Hideaki Katayama, Akira Inoue, Kazuo Hayashi, Takahiro Nakamoto, Tomoyuki Asada, Yutaka Torihime , Noriyuki Tanino, Masahide Yamauchi, 8
Line 0, line 18 and Figure 1, Date of issue August 30, 1996
Date.

[0003] GaAs FETs are widely and generally used as high frequency devices. In particular, in the high-output device, a multi-stage recess structure is adopted to reduce source resistance and secure gate breakdown voltage.

The "recess structure" refers to a structure in which the source and drain regions are masked and the vicinity of the gate is dug by etching, and the "multi-step recess structure" refers to a structure in which a plurality of steps are dug.

[0005] Such a multi-step recess structure is, for example, Ga
Using selective etching of As / AlGaAs stacked structure
It is formed. FIG. 18 shows a conventional field effect transistor.
FIG. 801 in FIG. 18 is a semi-insulating GaAs group
802, a GaAs buffer layer having a thickness of 400 nm;
03 is undoped Al_0.2 Ga_0.8 As buffer
Layer 804 is Si-doped Al_0.2 Ga_0.8 As Den children
Feed layer, 805 is undoped Al_0.2 Ga_0.8 As Spec
Layer 806 is undoped In_0.2 Ga_0.8As Chi
Channel layer, 807 is undoped Al _0.2 Ga_0.8 As
Spacer layer, 808 is Si-doped Al_0.2 Ga_0.8 
As electron supply layer, 809 is undoped Al _0.2 Ga_0.8
 As gate contact layer, 810 is GaAs gate buried
Embedded layer, 811 is Si-doped Al_0.2 Ga_0.8 As
Wide recess stopper layer, 812 is Si-doped GaAs
A cap layer, 813 is a gate electrode, 814 is a source electrode.
The pole 815 is a drain electrode.

In such a recess structure, first, a mask (not shown) in which a first recess (wide recess) portion 821 is opened is formed, and the GaAs layer 812 is selectively etched using the AlGaAs layer 811 as a wide recess stopper.
Next, a mask (not shown) having an opening in the second recess (gate recess) portion 822 is formed, and the GaAs layer 810 is selectively etched using the AlGaAs layer 809 as a gate recess stopper layer.

FIG. 18 schematically shows a distribution constant electric resistance generated in each portion of the FET having the conventional structure.
R1 is the contact resistance from the ohmic electrodes (source electrode 814 and drain electrode 815) to the cap layer 812, R2 is the contact resistance from the cap layer 812 to the channel layer 806, and R3 is the sheet resistance below the gate 813. The on-resistance of the FET is equal to the source electrode 814.
To the drain electrode 815.

[0008] Another document "1996 IEEE Ga"
As described in “As IC Symposium, page 119”, low on-resistance is important for obtaining high output and high efficiency in low voltage operation.

[0009] Other examples of this type of prior art are disclosed in Japanese Patent Application Laid-Open No. 9-102600 and Japanese Patent No. 2626213.

[0010]

However, the prior art has a disadvantage that the contact resistance R2 from the cap layer to the channel layer is high. The reason is that the potential barrier of the AlGaAs stopper layer used for forming the multi-stage recess structure is high, and the tunnel probability from the cap layer to the channel layer is small. However, it is difficult to make this layer thin because it is used as a stopper layer for selective etching.

An object of the present invention is to provide a field effect transistor capable of reducing the contact resistance from the cap layer to the channel layer and a method for manufacturing the same.

[0012]

In order to solve the above-mentioned problems, the present invention provides a channel layer made of InGaAs or GaAs, a first AlGaAs layer, AlGaAs / Ga.
An As superlattice layer, a GaAs layer, a second AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode are sequentially laminated, and a second AlGaAs layer and a cap layer formed in the cap layer are further formed. 1 recess and in said first recess and said AlGaAs
/ GaAs superlattice layer and second layer formed in the GaAs layer
And a gate electrode provided in the second recess to form a field effect transistor.

Another invention according to the present invention relates to InGaAs.
channel layer made of s or GaAs, first AlG
aAs layer, AlGaAs / GaAs superlattice layer, GaAs
Layer, second AlGaAs layer and In for ohmic electrode
A first step of sequentially laminating a cap layer made of GaAs or GaAs; a second step of forming a first recess in the second AlGaAs layer and the cap layer after the first step; Following the two steps, a third recess is formed in the first recess and in the AlGaAs / GaAs superlattice layer and the GaAs layer.
And a fourth step of providing a gate electrode in the second recess after the third step.

According to the present invention and another invention according to the present invention, AlGaAs / Ga is formed on the first AlGaAs layer.
Since the As superlattice layer is stacked, the contact resistance can be reduced.

[0015]

Embodiments of the present invention will be described below with reference to the accompanying drawings. First, the first embodiment will be described. The first embodiment relates to the first and eighth aspects of the present invention.

FIG. 1 is a cross-sectional view showing the structure of the first embodiment of the present invention, FIGS. 2 to 4 are cross-sectional views in the manufacturing process of the same embodiment, and FIG. 5 is a flowchart showing the manufacturing process of the same embodiment. . Hereinafter, the first embodiment will be described with reference to FIGS.

First, on a semi-insulating GaAs substrate 101,
GaAs buffer layer 102 having a thickness of 400 nm and a thickness of 10
0 nm undoped Al _0.2 Ga _0.8 As buffer layer 103, 4 n thick doped with 4 × 10 ¹⁸ cm ^{−3 of} Si
m Al _0.2 Ga _0.8 As electron supply layer 104, thickness 2
nm undoped Al _0.2 Ga _0.8 As spacer layer 1
05, undoped In _0.2 Ga _0.8 A with a thickness of 15 nm
s channel layer 106, undoped Al _{0.2 with} a thickness of 2 nm
Ga _0.8 As spacer layer 107, Si is 4 × 10 ¹⁸
9 nm thick Al _0.2 Ga _0.8 As doped with cm ^-3
Electron supply layer 108, undoped Al _{0.2 having} a thickness of 17 nm
Ga _0.8 As Schottky gate contact layer 10
9, Al _0.2 Ga _0.8 As (0.5 nm) / GaAs
(0.5 nm) × 3-period superlattice layer 110, film thickness 30n
m undoped GaAs buried layer 111, 4 ×
10 ¹⁸ cm ^-3 doped thickness 6nm of Al _0.2 Ga _0.8
As wide recess stopper layer 112, 4 × 10 Si
^A 100 nm-thick GaAs cap layer 113 doped with ¹⁸ cm ^-3 is sequentially epitaxially grown by molecular beam epitaxy or metalorganic vapor phase epitaxy (S1). FIG. 2 shows the structure after the epitaxial growth.

Next, a mask 901 having a wide recess is formed on the wafer prepared as shown in FIG.
2), a GaAs cap layer 113 using the Al _0.2 Ga _0.8 As wide recess stopper layer 112 as a stopper layer.
Is selectively etched (S3). Such selective etching uses an ECR etching apparatus or an RIE apparatus, and uses a mixed gas (for example, B2) of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine as a halogen element.
Cl ₃ ⁺ SF _6, etc.) can be by dry etching was introduced.

After the mask is removed, a mask 902 having a new gate recess is formed as shown in FIG. 4 (S4), and the GaAs gate buried layer is formed by using the Al _0.2 Ga _0.8 As gate contact layer 109 as a stopper layer. 1
10, Al _0.2 Ga _0.8 As (0.5 nm) / GaAs
The superlattice layer 110 of s (0.5 nm) × 3 periods is selectively etched (S5).

Next, Al _0.2 exposed as a result of the etching is used.
Exposed part 1 of Ga _0.8 As gate contact layer 109
09A, a gate electrode 114 is formed (S6), and AuGe
By vapor deposition lift-off and alloy (for example, 400 ° C./mi
n) is performed to form a source electrode 115 and a drain electrode 116 as ohmic electrodes (S7).

According to the structure of the first embodiment, A acts as a potential barrier between the source and the drain.
AlGaAs / G is formed on the lGaAs Schottky layer 108.
Since the aAs superlattice layer 110 is laminated, Ga
The bending of the conduction band occurring at the interface with the As buried layer 111 is reduced, and the sheet resistance at this portion is reduced. Immediately below the gate Schottky, φB (Schottky barrier height; unit electron volt, hereinafter the same) which is effective in forming the Schottky layer since the AlGaAs / GaAs superlattice layer 110 is shaved during gate recess formation is Al _0.2 Ga _0.8 As. Take the value of
As a result, the 0.1 Ω · mm on-resistance is reduced.

Next, a second embodiment will be described. The second embodiment relates to the second and ninth aspects of the present invention.

FIG. 6 is a sectional view showing the structure of the second embodiment of the present invention, and FIG. 7 is a flowchart showing the manufacturing process of the same embodiment. In the following embodiments, a cross-sectional view of the same embodiment in a manufacturing process is omitted. Hereinafter, FIG.
A second embodiment will be described with reference to FIG.

On a semi-insulating GaAs substrate 201, a film thickness of 4
GaAs buffer layer 202 of 00 nm, film thickness of 100 nm
Undoped Al_0.2 Ga_0.8 As buffer layer 20
3, 4 × 10 Si¹⁸cm^-34 nm thick doped A
l_0.2 Ga_0.8 As electron supply layer 204, 2 nm thick
Undoped Al_0.2 Ga_0.8 As spacer layer 205,
Undoped In with a thickness of 15 nm_0.2 Ga_0.8 As Cha
Tunnel layer 206, undoped Al having a thickness of 2 nm_0.2 Ga
_0.8 As spacer layer 207, 4 × 10 Si¹⁸cm^-3
Al doped 9nm thick_0.2 Ga_0.8 As Den children
Supply layer 208, undoped Al with a thickness of 17 nm_0.2 Ga
_0.8 Schottky gate contact layer 209, thickness 30
undoped GaAs buried layer 210 nm,
× 10¹⁸cm ^-3Al doped 3nm thick_0.2 Ga
_0.8 As wide recess stopper layer 211, Si is 4 ×
10¹⁸cm^-3Al doped 3nm thick_0.1 Ga_0.9
 As layer 212, 4 × 10 Si¹⁸cm^-3Doped film thickness
A 100 nm GaAs cap layer 213 is sequentially formed with a molecular beam.
Epitaxial growth by long method or metalorganic vapor phase epitaxy
(S11).

A wide recess is opened on the formed wafer.
A mask is formed (S12). _0.2 Ga_0.8 As
Using the wide recess stopper layer 211 as the stopper layer,
l_{0. 1} Ga_0.9 As layer 212, GaAs cap layer 2
The 13 layers are selectively etched (S13).

For such selective etching, an ECR etching apparatus or an RIE apparatus is used, and a mixed gas of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine (for example, BCl ₃ ⁺ SF ₆ ). This can be achieved by dry etching in which is introduced.

[0027] After removing the mask, to form a new mask gate recess is opened (S14), Al _0.2 G
The GaAs gate buried layer 210 is selectively etched using the a _0.8 As gate contact layer 209 as a stopper layer (S15). A gate electrode 214 is formed on the gate contact layer 209 exposed on the surface (S1)
6). Next, AuGe is vapor-deposited by lift-off and alloying (for example, 400 ° C./min) to form an ohmic electrode.
A source electrode 215 and a drain electrode 216 are formed (S17).

According to the structure of the second embodiment, AlG
Since the aAs wide recess stopper layer has a two-stage structure (211 layers and 212 layers), the sheet resistance in this portion is reduced. As a result, 0.05Ω · mm
ON resistance is reduced.

Next, a third embodiment will be described. The third embodiment relates to the third and tenth aspects of the present invention.

FIG. 8 is a sectional view showing the structure of the third embodiment of the present invention, and FIG. 9 is a flow chart showing the manufacturing process of the third embodiment. Hereinafter, the third embodiment will be described with reference to FIGS.

On a semi-insulating GaAs substrate 301, a film having a thickness of 4
GaAs buffer layer 302 of 00 nm, thickness of 100 nm
Undoped Al_0.2 Ga_0.8 As buffer layer 30
3, 4 × 10 Si¹⁸cm^-34 nm thick doped A
l_0.2 Ga_0.8 As electron supply layer 304 having a thickness of 2 nm
Undoped Al_0.2 Ga_0.8 As spacer layer 305,
Undoped In with a thickness of 15 nm_0.2 Ga_0.8 As Cha
Flannel layer 306, 2 nm-thick undoped Al_0.2 Ga
_0.8 As spacer layer 307, 4 × 10 Si¹⁸cm^-3
Al doped 9nm thick_0.2 Ga_0.8 As Den children
Supply layer 308, undoped Al with a thickness of 17 nm_0.2 Ga
_0.8 As Schottky gate contact layer 309, thickness
30 nm undoped GaAs buried layer 310, Si
Is 4 × 10¹⁸cm^-3Al doped 3nm thick_0.2 
Ga_0.8 As layer 311, Si is 4 × 10¹⁸cm^-3Do
0.5nm thick Al_0.18Ga_0.82As layer 31
2, 4 × 10 Si¹⁸cm^-30.5nm doped film thickness
Al_0.15Ga_0.85As layer 313, Si is 4 × 10¹⁸c
m^-30.5 nm thick doped Al_0.12Ga_0.88As
Layer 314, 4 × 10 Si¹⁸cm^-3Doped film thickness
5nm Al_0.09Ga_0.91As layer 315, Si 4 × 1
0¹⁸cm^-30.5 nm thick doped Al_0.06Ga
_0.94As layer 316, 4 × 10 Si¹⁸cm^-3Doped
0.5 nm thick Al_{0. 03}Ga_0.97As layer 317, Si
Is 4 × 10¹⁸cm^-3100 nm doped GaAs
The s cap layer 318 is sequentially formed by a molecular beam growth method or
Epitaxial growth is performed by a phase growth method (S21).

A wide recess is opened on the formed wafer.
A mask is formed (S22). _0.2 Ga_0.8 As
Using the wide recess stopper layer 311 as a stopper layer,
lGaAs layers 312-317, GaAs cap layer 31
The three layers are selectively etched (S23).

For such selective etching, an ECR etching apparatus or an RIE apparatus is used, and a mixed gas of a chlorine gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine (for example, BCl ₃ ⁺ SF ₆ ). This can be achieved by dry etching in which is introduced.

[0034] After removing the mask, to form a new mask gate recess is opened (S24), Al _0.2 G
The GaAs gate buried layer 310 is selectively etched using the a _0.8 As gate contact layer 309 as a stopper layer (S25).

Gate contact layer 309 exposed on the surface
A gate electrode 319 is formed thereon (S26). Then Au
Ge is vapor-deposited by lift-off and alloy (for example, 400 ° C./m
in), and the source electrode 32 is formed as an ohmic electrode.
0 and a drain electrode 321 are formed (S27).

According to the structure of the third embodiment, AlG
Since the aAs wide recess stopper layer has a two-stage structure (311 layers and 312 to 317 layers), the sheet resistance in this portion is reduced. As a result, 0.05
Ω · mm ON resistance is reduced.

Next, a fourth embodiment will be described. The fourth embodiment relates to the fourth and eleventh inventions.

FIG. 10 is a sectional view showing the structure of the fourth embodiment of the present invention, and FIG. 11 is a flowchart showing the manufacturing steps of the fourth embodiment. Hereinafter, the fourth embodiment will be described with reference to FIGS.

On a semi-insulating GaAs substrate 401, a film having a thickness of 4
GaAs buffer layer 402 having a thickness of 100 nm and a thickness of 100 nm
Undoped Al _0.2 Ga _0.8 As buffer layer 40
3, 4 nm thick A doped with 4 × 10 ¹⁸ cm ^{−3 of} Si
l _0.2 Ga _0.8 As electron supply layer 404, undoped Al _0.2 Ga _0.8 As spacer layer 405 having a thickness of 2 nm,
Undoped In _0.2 Ga _0.8 As channel layer 406 with a thickness of 15 nm, undoped Al _0.2 Ga with a thickness of 2 nm
_0.8 As spacer layer 407, Si is 4 × 10 ¹⁸ cm ⁻³
A doped 9-nm thick Al _0.2 Ga _0.8 As electron supply layer 408, a 17-nm thick undoped Al _0.2 Ga
_0.8 As Schottky gate contact layer 409, undoped Al _0.1 Ga _0.9 As layer 410 having a thickness of 3 nm,
An undoped GaAs buried layer 411 having a thickness of 30 nm;
3 nm thick Al _0.2 G doped with 4 × 10 ¹⁸ cm ⁻³ of Si doped with 4 × 10 ¹⁸ cm ⁻³ of Si
a _0.8 As wide recess stopper layer 412, 4 × Si
10 ¹⁸ cm ^-3 Al _0.1 Ga _0.9 of doped thickness 3nm
An AsAs layer 413 and a 100 nm-thick GaAs cap layer 414 doped with Si at 4 × 10 ¹⁸ cm ⁻³ are sequentially epitaxially grown by molecular beam growth or metal organic chemical vapor deposition (S31).

A wide recess is opened on the created wafer.
A mask is formed (S32). _0.2 Ga_0.8 As
Using the wide recess stopper layer 412 as a stopper layer,
aAs cap layer 414 layer and AlGaAs 413 layer were selected.
It is selectively etched (S33).

For such selective etching, an ECR etching apparatus or an RIE apparatus is used, and a mixed gas of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine (for example, BCl ₃ ⁺ SF ₆ ). This can be achieved by dry etching in which is introduced.

[0042] After removing the mask, to form a new mask gate recess is opened (S34), Al _0.2 G
a _0.8 As gate contact layer 409 is used as a stopper layer to form a GaAs gate buried layer 411 and Al _0.1 G
a _0.9 As layer 410 is selectively etched (S3
5).

Gate contact layer 409 exposed on the surface
A gate electrode 415 is formed thereon (S36). Then Au
Ge is vapor-deposited by lift-off and alloy (for example, 400 ° C./m
in), and the source electrode 41 is formed as an ohmic electrode.
6 and a drain electrode 417 are formed (S37).

According to the structure of the fourth embodiment, A which acts as a potential barrier between the source and the drain is used.
The lGaAs Schottky layer has a two-stage structure (41).
With two layers and 413 layers), the sheet resistance in this portion is reduced. Moreover, [phi] B come into play in the Schottky layer formed since the scraping Schottky layer 410 layer at the gate recess formed in the gate Schottky immediately below Al _0.2
Take the value of Ga _0.8 As. As a result, 0.15Ω
mm on-resistance is reduced.

Next, a fifth embodiment will be described. The fifth embodiment relates to the fifth and twelfth aspects.

FIG. 12 is a sectional view showing the structure of the fifth embodiment of the present invention, and FIG. 13 is a flowchart showing the manufacturing steps of the fifth embodiment. Hereinafter, the fifth embodiment will be described with reference to FIGS.

On a semi-insulating GaAs substrate 501, a film thickness of 4
GaAs buffer layer 502 of 00 nm, thickness of 100 nm
Undoped Al _0.2 Ga _0.8 As buffer layer 50
3, 4 nm thick A doped with 4 × 10 ¹⁸ cm ^{−3 of} Si
l _0.2 Ga _0.8 As electron supply layer 504, undoped Al _0.2 Ga _0.8 As spacer layer 505 having a thickness of 2 nm,
Undoped In _0.2 Ga _0.8 As channel layer 506 with a thickness of 15 nm, undoped Al _0.2 Ga with a thickness of 2 nm
_0.8 As spacer layer 507, Si is 4 × 10 ¹⁸ cm ⁻³
Doped 9 nm thick Al _0.2 Ga _0.8 As electron supply layer 508, 17 nm thick undoped Al _0.2 Ga
_0.8 As Schottky gate contact layer 509, Al
_0.2 Ga _0.8 As (0.5 nm) / GaAs (0.5
nm) × 3 periods of the superlattice layer 510, an undoped GaAs buried layer 511 having a thickness of 30 nm, Si and 4 × 10 ¹⁸ c
Al _0.2 Ga _0.8 As wide recess stopper layer 512 with a thickness of 3 nm doped with m ⁻³ doped Si with a thickness of 4 nm and 4 × 10 ¹⁸ cm ^−3, and a 3 nm thick Si doped with 4 × 10 ¹⁸ cm ⁻³ doped Si with a thickness of 4 × 10 ¹⁸ cm ⁻³ . Al _0.1 Ga _0.9 As layer 513, S
i is 4 × 10 ¹⁸ cm ⁻³ doped Ga having a thickness of 100 nm
The As cap layer 514 is sequentially epitaxially grown by a molecular beam growth method or a metal organic chemical vapor deposition method (S41).

A wide recess is opened on the formed wafer.
A mask is formed (S42). _0.2 Ga_0.8 As
Using wide recess stopper layer 512 as a stopper layer,
a Cap layer 514 and AlGaAs layer 513 are selected.
It is selectively etched (S43).

For such selective etching, an ECR etching apparatus or an RIE apparatus is used, and a mixed gas of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine (for example, BCl ₃ ⁺ SF ₆ ). This can be achieved by dry etching in which is introduced.

[0050] After removing the mask, to form a new mask gate recess is opened (S44), Al _0.2 G
Using the a _0.8 As gate contact layer 509 as a stopper layer, the GaAs gate buried layer 511, Al _0.2 G
a _0.8 As (0.5 nm) / GaAs (0.5 nm)
The superlattice layer 510 of × 3 periods is selectively etched (S45).

Gate contact layer 509 exposed on the surface
A gate electrode 515 is formed thereon (S46). Then Au
Ge is vapor-deposited by lift-off and alloy (for example, 400 ° C./m
in), and the source electrode 51 is formed as an ohmic electrode.
6 and a drain electrode 517 are formed (S47).

According to the structure of the fifth embodiment, A acts as a potential barrier between the source and the drain.
The 1-GaAs Schottky layer has a two-stage structure (51).
With two layers and 513 layers), the sheet resistance in this portion is reduced. Moreover, [phi] B come into play in the Schottky layer formed since the scraping AlGaAs layer 510 layer at the gate recess formed in the gate Schottky immediately below Al _0.2
Take the value of Ga _0.8 As. As a result, 0.15Ω
-Mm-on resistance is reduced.

Next, a sixth embodiment will be described. The sixth embodiment relates to the sixth and thirteenth inventions.

FIG. 14 is a sectional view showing the structure of the sixth embodiment of the present invention, and FIG. 15 is a flowchart showing the manufacturing steps of the sixth embodiment. Hereinafter, the sixth embodiment will be described with reference to FIGS. 14 and 15.

On a semi-insulating GaAs substrate 601, a film thickness of 4
00 nm GaAs buffer layer 602, 100 nm thick
Undoped Al _0.2 Ga _0.8 As buffer layer 60
3, 4 nm thick A doped with 4 × 10 ¹⁸ cm ^{−3 of} Si
l _0.2 Ga _0.8 As electron supply layer 604, an undoped Al _0.2 Ga _0.8 As spacer layer 605 having a thickness of 2 nm,
Undoped In _0.2 Ga _0.8 As channel layer 606 with a thickness of 15 nm, undoped Al _0.2 Ga with a thickness of 2 nm
_0.8 As spacer layer 607, 4 × 10 ¹⁸ cm ^{−3 of} Si
Doped 9 nm thick Al _0.2 Ga _0.8 As electron supply layer 608, 17 nm thick undoped Al _0.2 Ga
_0.8 As Schottky gate contact layer 609, undoped Al _0.1 Ga _0.9 As layer 610 having a thickness of 3 nm,
An undoped GaAs buried layer 611 having a thickness of 30 nm;
3 nm thick Al doped with 4 × 10 ¹⁸ cm ^{−3 of} Si
_0.2 Ga _0.8 As layer 612, Si is 4 × 10 ¹⁸ cm ⁻³
0.5 nm doped Al _0.18 Ga _0.82 As layer 6
13. Film thickness 0.5n doped with 4 × 10 ¹⁸ cm ^{−3 of} Si
m Al _0.15 Ga _0.85 As layer 614, Si is 4 × 10 ¹⁸
0.5 nm thick Al _0.12 Ga _0.88 A doped with cm ^-3
s layer 615, Al _0.09 Ga _0.91 As layer 616 with a thickness of 0.5 nm doped with 4 × 10 ¹⁸ cm ^{−3 of} Si, 4
× 10 ¹⁸ cm ^-3 doped Al _0.06 G with a thickness of 0.5 nm
a _0.94 As layer 617, Al _0.03 Ga _0.97 As layer 618 doped with Si at 4 × 10 ¹⁸ cm ^-3 and having a thickness of 0.5 nm, S
i is 4 × 10 ¹⁸ cm ⁻³ doped Ga having a thickness of 100 nm
The As cap layer 619 is epitaxially grown sequentially by a molecular beam growth method or a metal organic chemical vapor deposition method (S51).

A wide recess is opened on the created wafer.
A mask is formed (S52). _0.2 Ga_0.8 As
Using the wide recess stopper layer 612 as a stopper layer,
aAs cap layer 614, AlGaAs layers 613-6
18 is selectively etched (S53).

For such selective etching, an ECR etching apparatus or an RIE apparatus is used, and a mixed gas of a chlorine gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine (for example, BCl ₃ ⁺ SF ₆ ). This can be achieved by dry etching in which is introduced.

[0058] After removing the mask, to form a new mask gate recess is opened (S54), Al _0.2 G
Using the a _0.8 As gate contact layer 609 as a stopper layer, the GaAs gate buried layer 611, Al _0.1 G
a _0.9 As layer 610 is selectively etched (S5
5).

Gate contact layer 609 exposed on the surface
A gate electrode 620 is formed thereon (S56). Then Au
Ge is vapor-deposited by lift-off and alloy (for example, 400 ° C./m
in) to form a source electrode 62 as an ohmic electrode.
1 and a drain electrode 622 are formed (S57).

According to the structure of the sixth embodiment, A acts as a potential barrier between the source and the drain.
The lGaAs Schottky layer has a two-stage structure (61).
With two layers and 613 to 618 layers), the sheet resistance in this portion is reduced. Immediately below the gate Schottky, since the AlGaAs layer 610 is shaved during the formation of the gate recess, φB effective for forming the Schottky layer has a value of Al _0.2 Ga _0.8 As. As a result, 0.
15 Ω · mm on-resistance is reduced.

Next, a seventh embodiment will be described. The seventh embodiment relates to the seventh and fourteenth aspects of the present invention.

FIG. 16 is a sectional view showing the structure of the seventh embodiment of the present invention, and FIG. 17 is a flow chart showing the manufacturing steps of the seventh embodiment. Hereinafter, the seventh embodiment will be described with reference to FIGS. 16 and 17.

On a semi-insulating GaAs substrate 701,
GaAs buffer layer 702 of 00 nm, thickness of 100 nm
Undoped Al_0.2 Ga_0.8 As buffer layer 70
3, 4 × 10 Si¹⁸cm^-34 nm thick doped A
l_0.2 Ga_0.8 As electron supply layer 704 having a thickness of 2 nm
Undoped Al_0.2 Ga_0.8 As spacer layer 705,
Undoped In with a thickness of 15 nm_0.2 Ga_0.8 As Cha
Flannel layer 706, undoped Al 2 nm thick_0.2 Ga
_0.8 As spacer layer 707, 4 × 10 Si¹⁸cm^-3
Al doped 9nm thick_0.2 Ga_0.8 As Den children
Feed layer 708, undoped Al with a thickness of 17 nm_0.2 Ga
_0.8 As Schottky gate contact layer 709, Al
_0.2 Ga_0.8 As (0.5 nm) / GaAs (0.5
nm) × 3 period superlattice layer 710, 30 nm thick
Doped GaAs buried layer 711, 4 × 10¹⁸c
m^-3Al doped 3nm thick_0.2 Ga_0.8 As layer
712, 4 × 10 Si¹⁸cm^-30.5 doped film thickness
nm Al_0.18Ga_0.82As layer 713, Si is 4 × 10
¹⁸cm^-30.5 nm thick doped Al_0.15Ga_0.85
As layer 714, Si 4 × 10¹⁸cm^-3Doped film thickness
0.5 nm Al_0.12Ga_0.88As layer 715, Si 4
× 10¹⁸cm^-30.5 nm thick doped Al _0.09G
a_0.91As layer 716, 4 × 10 Si¹⁸cm^-3Dope
Al with a thickness of 0.5 nm_0.06Ga_0.94As layer 717, S
i is 4 × 10¹⁸cm^-30.5 nm thick doped Al
_0.03Ga_0.97As layer 718, 4 × 10¹⁸cm^-3Do
GaAs cap layer 719 with a thickness of 100 nm
Epitaxy by sequential molecular beam epitaxy or metalorganic vapor phase epitaxy
It grows axially (S61).

A wide recess is opened on the formed wafer.
A mask is formed (S62). _0.2 Ga_0.8 As
Using wide recess stopper layer 712 as a stopper layer,
aAs cap layer 714, AlGaAs layers 713 to 71
8 is selectively etched (S63).

For such selective etching, an ECR etching apparatus or an RIE apparatus is used, and a mixed gas of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine (for example, BCl ₃ ⁺ SF ₆ ). This can be achieved by dry etching in which is introduced.

[0066] After removing the mask, to form a new mask gate recess is opened (S64), Al _0.2 G
Using the a _0.8 As gate contact layer 709 as a stopper layer, the GaAs gate buried layer 711 and the Al _0.2 G
a _0.8 As (0.5 nm) / GaAs (0.5 nm)
The superlattice layer 710 of × 3 periods is selectively etched (S65).

Gate contact layer 709 exposed on the surface
A gate electrode 720 is formed thereon (S66). Then Au
Ge is vapor-deposited by lift-off and alloy (for example, 400 ° C./m
in), and the source electrode 72 is formed as an ohmic electrode.
1 and a drain electrode 722 are formed (S67).

According to the structure of the seventh embodiment, A acts as a potential barrier between the source and the drain.
The 1-GaAs Schottky layer has a two-stage structure (71).
With two layers and 713 to 718 layers), the sheet resistance in this portion is reduced. Immediately below the gate Schottky, when forming the second recess, the AlGaAs layer 710 is formed.
ΦB which is effective for Schottky layer formation because the layer is shaved
Takes a value of Al _0.2 Ga _0.8 As. As a result, 0.
15 Ω · mm on-resistance is reduced.

[0069]

According to the present invention, InGaAs or Ga
A channel layer composed of As, a first AlGaAs layer,
An AlGaAs / GaAs superlattice layer, a GaAs layer, a second AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode are sequentially laminated, and further formed in the second AlGaAs layer and the cap layer. A first recess formed in the first recess and in the AlGaAs / GaAs superlattice layer and the GaAs.
Since the field effect transistor was configured to include the second recess formed in the layer and the gate electrode provided in the second recess, an Al layer was formed on the first AlGaAs layer.
A GaAs / GaAs superlattice layer will be laminated,
Thereby, the contact resistance can be reduced.

According to another aspect of the present invention, In
A channel layer composed of GaAs or GaAs, a first AlGaAs layer, an AlGaAs / GaAs superlattice layer,
a first step of sequentially laminating an aAs layer, a second AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode; and, after the first step, a second step is formed in the second AlGaAs layer and the cap layer. A second step of forming the first recess, and following the second step, in the first recess and in the AlGaAs / Ga
A third step of forming a second recess in the As superlattice layer and the GaAs layer; and a fourth step of providing a gate electrode in the second recess after the third step. Because the manufacturing method is configured, the first
The AlGaAs / GaAs superlattice layer is laminated on the AlGaAs layer of the above, so that the contact resistance can be reduced.

More specifically, according to the present invention, first, the Al of the Schottky barrier layer is changed as in the conventional structure.
Providing a superlattice layer between the GaAs rather than a constant GaAs composition as described above lowers the potential barrier and can reduce the contact resistance between the channel and the gate by 0.1 Ω · mm. At this time, since the gate electrode is provided in a portion having a high Al composition, a high φB can be maintained. As a result, the structure of the present invention enables a high-output operation and a high-efficiency operation of the field-effect transistor while maintaining a high reverse breakdown voltage.

Second, the potential barrier is lowered by reducing the AlGaAs composition of the wide recess stopper layer to a two-stage structure instead of the conventional structure as in the conventional structure, thereby reducing the contact resistance between the channel gates by 0.05 Ω · mm. it can. This enables a high-output operation and a high-efficiency operation of the field-effect transistor.

Third, unlike the conventional structure, the composition of the AlGaAs of the wide recess stopper layer is not constant, but a gradient Al composition structure is used as described above to lower the potential barrier and reduce the contact resistance between the channel gates to 0.0.
5 Ω · mm can be reduced. This enables a high-output operation and a high-efficiency operation of the field-effect transistor.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the same embodiment in a manufacturing process.

FIG. 3 is a sectional view of the same embodiment in a manufacturing process.

FIG. 4 is a sectional view of the same embodiment in a manufacturing process.

FIG. 5 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 6 is a sectional view showing a configuration of a second exemplary embodiment of the present invention.

FIG. 7 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 8 is a sectional view showing a configuration of a third exemplary embodiment of the present invention.

FIG. 9 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 10 is a sectional view showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 11 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 12 is a sectional view showing a configuration of a fifth exemplary embodiment of the present invention.

FIG. 13 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 14 is a sectional view showing a configuration of a sixth exemplary embodiment of the present invention.

FIG. 15 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 16 is a sectional view showing a configuration of a seventh embodiment of the present invention.

FIG. 17 is a flowchart showing a manufacturing process of the same embodiment.

FIG. 18 is a sectional view of a conventional field-effect transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Substrate 102,103 Buffer layer 104,108 Electron supply layer 105,107 Spacer layer 106 Channel layer 109 Schottky gate contact layer 110 Super lattice layer 111 Undoped GaAs buried layer 112 Wide recess stopper layer 113 Cap layer 114 Gate electrode 115 Source electrode 116 Drain electrode 212 AlGaAs layer 312 to 317 AlGaAs layer 410 AlGaAs layer

Claims (14)

[Claims] 1. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, an AlGaAs / G
an aAs superlattice layer, a GaAs layer, a second AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode are sequentially laminated.
A first recess formed in the AlGaAs layer and the cap layer, and the first recess formed in the first recess and the AlGaAs layer.
A field effect transistor including a second recess formed in the s / GaAs superlattice layer and the GaAs layer, and a gate electrode provided in the second recess. 2. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, a GaAs layer, and a second layer.
AlGaAs layer, a third AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode are sequentially laminated, and the second and third A layers are further stacked.
a first recess formed in the lGaAs layer and the cap layer; a second recess formed in the first recess and in the GaAs layer; and a gate electrode provided in the second recess. And a field-effect transistor. 3. A channel layer composed of InGaAs or GaAs, a first AlGaAs layer, a GaAs layer, and a second layer.
AlGaAs layer and InGaAs for ohmic electrode
Alternatively, a cap layer made of GaAs is sequentially laminated, and a first recess formed in the second AlGaAs layer and the cap layer, and a first recess formed in the first recess and in the GaAs layer. A second recess, and a gate electrode provided in the second recess, and the second AlGaAs layer is formed in a tilted structure in which an Al composition ratio is gradually increased from the cap layer toward the GaAs layer. A field effect transistor characterized by the above-mentioned. 4. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, and a second AlGaAs layer.
s layer, GaAs layer, third AlGaAs layer, fourth Al
InGaAs or G for GaAs layer and ohmic electrode
a cap layer composed of aAs is sequentially laminated, further comprising a first recess formed in the third and fourth AlGaAs layers and the cap layer, and a first recess formed in the first recess and the second recess formed in the first recess. A field effect transistor comprising: a second recess formed in the AlGaAs layer and the GaAs layer; and a gate electrode provided in the second recess. 5. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, AlGaAs / G
aAs superlattice layer, GaAs layer, second AlGaAs layer,
InGa for third AlGaAs layer and ohmic electrode
A cap layer made of As or GaAs is sequentially laminated, and further, a first recess formed in the second and third AlGaAs layers and the cap layer, and a first recess formed in the first recess and in the first recess. A second recess formed in the AlGaAs / GaAs superlattice layer and the GaAs layer;
And a gate electrode provided in the recess. 6. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, and a second AlGaAs.
an AlGaAs layer, a GaAs layer, a third AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode.
A first recess formed in the As layer and the cap layer;
In the first recess and in the first and second AlGa
A second recess formed in the As layer and the GaAs layer;
A gate electrode provided in the second recess,
The field effect transistor is characterized in that the third AlGaAs layer is formed in a tilted structure in which the Al composition ratio increases in the direction of the GaAs layer from the cap layer. 7. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, AlGaAs / G
an aAs superlattice layer, a GaAs layer, a second AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode are sequentially laminated.
A first recess formed in the AlGaAs layer and the cap layer, and the first recess formed in the first recess and the AlGaAs layer.
a second recess formed in the s / GaAs superlattice layer and the GaAs layer; and a gate electrode provided in the second recess. The second AlGaAs layer has an Al composition ratio of the cap layer. A field-effect transistor formed in an inclined structure in which the height gradually increases in the direction of the GaAs layer. 8. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, AlGaAs / G
a first step of sequentially laminating an aAs superlattice layer, a GaAs layer, a second AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode; and, after the first step, the second AlGaAs layer and A second step of forming a first recess in the cap layer; and forming a second recess in the first recess and in the AlGaAs / GaAs superlattice layer and the GaAs layer following the second step. A third step of providing a gate electrode in the second recess after the third step.
And a step of manufacturing the field-effect transistor. 9. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, a GaAs layer, and a second layer.
A first step of sequentially laminating an AlGaAs layer, a third AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode; and, after the first step, the second and third AlGaAs layers and a cap. A second step of forming a first recess in the layer, and following said second step in said first recess and said Ga
A method for manufacturing a field effect transistor, comprising: a third step of forming a second recess in an As layer; and a fourth step of providing a gate electrode in the second recess after the third step. . 10. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, a GaAs layer, a second AlGaAs layer, and InGaAs for an ohmic electrode.
a first step of sequentially laminating a cap layer composed of s or GaAs, and the second step after the first step.
A second step of forming a first recess in the GaAs layer and the cap layer; and a third step of forming a second recess in the first recess and in the GaAs layer following the second step. And the second step after the third step.
A step of providing a gate electrode in the recess, and wherein the second AlGaAs layer is formed in a tilted structure in which the Al composition ratio increases gradually from the cap layer toward the GaAs layer. A method for manufacturing a transistor. 11. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, and a second AlGas layer.
As layer, GaAs layer, third AlGaAs layer, fourth A layer
a first step of sequentially laminating an lGaAs layer and a cap layer made of InGaAs or GaAs for an ohmic electrode, and following the first step, the third and fourth A
a second step of forming a first recess in the lGaAs layer and the cap layer; and following the second step, in the first recess and in the second AlGaAs layer and the GaAs.
manufacturing a field effect transistor, comprising: a third step of forming a second recess in the s layer; and a fourth step of providing a gate electrode in the second recess after the third step. Method. 12. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, an AlGaAs /
GaAs superlattice layer, GaAs layer, second AlGaAs
Layer, third AlGaAs layer and In for ohmic electrode
A first step of sequentially laminating a cap layer made of GaAs or GaAs; and a second step of forming a first recess in the second and third AlGaAs layers and the cap layer after the first step. After the second step, in the first recess and in the AlGaAs / Ga
A third step of forming a second recess in the As superlattice layer and the GaAs layer; and a fourth step of providing a gate electrode in the second recess after the third step. A method for manufacturing a field effect transistor. 13. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, and a second AlGa
A first step of sequentially laminating an As layer, a GaAs layer, a third AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode, and, after the first step, the third AlGaAs layer and the cap layer. Forming a first recess in the first recess, and forming a second recess in the first recess and in the first and second AlGaAs layers and the GaAs layer after the second step. A third step, followed by the second step
And a fourth step of providing a gate electrode in the recess. The third AlGaAs layer is formed in a tilted structure in which the Al composition ratio increases gradually from the cap layer toward the GaAs layer. A method for manufacturing a field effect transistor. 14. A channel layer made of InGaAs or GaAs, a first AlGaAs layer, an AlGaAs /
A first step of sequentially stacking a GaAs superlattice layer, a GaAs layer, a second AlGaAs layer, and a cap layer made of InGaAs or GaAs for an ohmic electrode, and, after the first step, the second AlGaAs layer and A second step of forming a first recess in the cap layer;
Following the second step, a third step of forming a second recess in the first recess and in the AlGaAs / GaAs superlattice layer and the GaAs layer; and, following the third step, the second step. A step of providing a gate electrode in the recess, and wherein the second AlGaAs layer is formed in an inclined structure in which the Al composition ratio increases sequentially from the cap layer toward the GaAs layer. A method for manufacturing a field effect transistor.