JP2000236031A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory of a control system which can make narrow a threshold distribution of a memory cell in a data erase state. SOLUTION: Based on a local self boost(LSB) system, erase threshold distribution of a cell is set at higher side of a readable range in an erase state to be made sufficiently narrow. Batch write in is carried out for each block of a memory cell array which is to be erased (S11), and thereafter soft erase is carried out for each block with a predetermined voltage as a start voltage (S12). The threshold of the cell is compared with a decision reference value (S14) through an erase verify reading operation. When the threshold of the cell fails to reach the decision reference, value, soft erase is repeated (loop S15). The predetermined voltage of the soft erase is varied from the start voltage. When the thresholds of all the cells reach the decision reference value, the soft erase is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device using an electrically rewritable memory cell in which a floating gate (charge storage layer) and a control gate are stacked. EEPROM). Further, in particular, one memory cell stores one of a plurality of types of data of more than two types of 1, 0, NAN.
It relates to a D-type multi-valued memory.

[0002]

2. Description of the Related Art Conventionally, a nonvolatile semiconductor memory device (EEPRO) which is electrically programmable and can be highly integrated.
M, a flash memory) is a NAND cell type EEPROM in which a plurality of memory cells are connected in series.

FIGS. 13 (a) and 13 (b) show a NAND
FIG. 2 is a plan view and an equivalent circuit diagram of one NAND cell portion relating to a memory cell array of a cell type EEPROM. FIG.
4A is a cross-sectional view taken along line AA shown in FIG. 13A, and FIG. 14B is a sectional view taken along line BB shown in FIG.
It is sectional drawing along the line. Also, FIG.
FIG. 14B shows another example in which the LOCOS element isolation (312) is used, while FIG. 15 is a cross-sectional view in the case of using the trench element isolation insulating film (322) ( The dashed-dotted line portion corresponds to the same portion shown in FIG.

A memory cell array composed of a plurality of NAND cells is formed on a P-type silicon substrate (here, a P-well) 311 surrounded by an isolation oxide film. Here, one NAND cell has, for example, 8
Memory cells MCx connected in series (x is 1 to
8).

In each memory cell MCx, a floating gate 314x and a control gate 3
16x (x is 1 to 8) has a stacked gate structure in which an insulating film 315 is interposed therebetween. A plurality of such memory cells MCx (x is 1 to 8) are connected in series in such a manner that the source and drain are shared between adjacent ones, and this is one unit of the NAND cell.

The drain on one side of the NAND cell is connected to a bit line BL (318) via a select gate transistor. The other end of the NAND cell is also connected to a source line via a select gate transistor. The gate electrode of each select gate transistor has a form in which a floating gate 314x and a control gate 316x (x is 9 or 10) are electrically connected at a portion not shown.

The control gate of the memory cell, ie, 316x
(X is 1 to 8), and the gate electrode of the select gate transistor, that is, 316x (x is 9 or 10) (314x
(X is connected to 9 or 10)) is the control gate line CGx (x is 1 to 8), that is, the word line W
Lx (x is 1 to 8) is commonly connected to NAND cells in the row direction as select gate lines SGD and SGS.
The substrate on which the elements are formed is covered with a CVD oxide film 317 and the like, and a bit line 318 (BL) is provided thereon.

In such a write operation method of the NAND cell type EEPROM, a local self-boost method (LSB method) has recently been regarded as promising. This L
The SB method will be described below with reference to FIG.

In the NAND cell of FIG. 13B, data stored in one memory cell is binary (“1”,
"0" is stored in one memory cell), or another multi-value is set. For example, in the case of multi-valued quaternary storage, normally, “1” data is replaced with “11”.
Data (negative threshold), “0” data to “10”,
The data may be replaced with either “01” or “00” data (the threshold value is positive and each data is separated into a certain threshold range).

Also, in a multi-valued memory having no threshold distribution as described above, it is only necessary that the threshold is divided into a plurality of thresholds, and the dividing method does not need to have the polarity.

{Data Erase Operation} Data erase is performed by NAN
Either it is performed simultaneously for all memory cells in the D-type cell (batch erase) or it is performed for each block (block erase). Usually, the blocks are arranged in the row direction, and for example, each predetermined control gate is a group of common NAND cells.

That is, all the control gates CGx (word lines WLx) (x is 1 to 8) (x is 1 to 8) are set to 0 V (in the case of block erase, the control gates of the non-selected blocks and A high voltage Vpp (for example, 20 V) is applied to the selection gate, a non-selected bit line and a source line are floated, and a high voltage (for example, 20 V) is applied to the P well.

As a result, in all (or all in the selected block) memory cells, electrons of the floating gate are emitted to the P well, and the threshold value shifts in the negative direction. As described above, the data erasing operation is performed simultaneously on the entire memory cell (batch erasing) or on a block basis (block erasing), or before the data writing operation on the entire memory cell or on a block basis. Is always implemented.

{Data Write Operation} Assuming that the selected control gate of the selected block, that is, the word line is, for example, WL2, a high write voltage Vpp is applied to the selected word line WL2 during the write operation. . 0V is applied to the unselected word lines (here, both sides) WL1 _and WL3 adjacent to the selected word line WL2.
Vpass (0 V lower than Vpp and a substantially intermediate voltage between Vpp) is applied to other unselected word lines. In addition,
A positive voltage lower than Vpass may be applied to the unselected word lines WL1 _and WL3.

A predetermined positive voltage Vs is applied to the select gate line SGD.
gd. The selection gate line SGS is at 0V.
All word lines and all selected gate lines in unselected blocks are set to 0V
It is. The write operation is usually performed in the order from the memory cell farthest from the bit line to the memory cell closest to the bit line.

For example, when writing "0" data (here, data whose threshold value is positive), the bit line BL is set to 0V. Since the memory cells existing on the bit line side with respect to the selected memory cell are always in the erased state, even if the word line next to the selected memory cell is set to 0 V, the write selection voltage of the selected bit line (0 V) Is transferred to the selected memory cell. In the selected memory cell, electrons move from the substrate to the floating gate, and the threshold value of the selected memory cell becomes positive.

When writing "1" data (data having a negative threshold value), the bit line BL is
The write non-selection voltage is equal to or higher than sgd. Since the selection gate SGD is at Vsgd, the selection gate transistor is turned off, and the channel (and n-type diffusion layer) of each memory cell is in a floating state. As a result, the channel potential of the selected memory cell to which the high voltage Vpp is applied to the word line and the channel and diffusion layer potential of the non-selected memory cell to which the voltage Vpass is applied to the word line are increased.

The memory cells on both sides of the selected memory cell are cut off by the back bias effect due to the channel potential raised by the voltage Vpass. At this time, if the high voltage Vpp is applied to the selected memory cell, the channel potential rises due to the coupling between this one memory cell and the channel and source / drain diffusion layers of that memory cell. At this time, if Vpp is, for example, 18 V and the channel boost ratio is 0.5, the channel potential rises to about 8 to 9 V. That is, the potential difference between the word line and the channel becomes small, and becomes sufficient as the write inhibit voltage.

{Data Read Operation} Data is read by applying a read voltage (for example, 3.5 V) to the selected gate line and word lines of non-selected memory cells other than the selected memory cell in the selected block. In the on state, 0 V or a predetermined voltage is applied to the word line of the selected memory cell. At this time, by detecting the bit line potential that fluctuates due to the current flowing on the bit line side,
A decision is made on one of a plurality of types, such as "0" and "1".

[0020]

As described above, L
In the SB system, a voltage of 0 V or more and less than Vpass is applied to an unselected word line adjacent to a selected word line to which a high voltage is applied, and Vpass is applied to other unselected word lines. The LSB method is a promising technique especially as a writing method for a multi-valued memory, in which erroneous writing or a change in cell threshold voltage is extremely small.

However, the LSB method also has a problem with miniaturization and high integration of cells. The most significant feature of the LSB method is that in a write operation, unselected memory cells on both sides of a selected memory cell must be cut off regardless of the data held therein. Since the memory cells on both sides have an arbitrary threshold value (one on either side has a positive threshold value or both have a negative threshold value), they may be in an erased state.

As described above, in order to cut off by the back bias effect due to the channel potential, the voltage Vpass
Is required to be sufficiently large or the distribution of the erase threshold is controlled, and the memory cell having the lowest threshold needs to be sufficiently high.

The former cannot be made too large in order to suppress threshold fluctuation due to the voltage Vpass of a memory cell connected to an unselected word line and a selected bit line. Conversely, the smaller the voltage Vpass is for the memory cell, the smaller the threshold fluctuation becomes,
Erroneous writing can be prevented.

Therefore, it is essential that the erase threshold distribution is set to a higher value and the distribution is sufficiently narrowed within the latter range in which the erase state can be read. To give an example,
The purpose is to suppress the threshold distribution of the erased cell to a range of -3V to -0.5V. For this reason, the applicant first erases data, and then applies a write pulse to each word line for each block while repeatedly stepping up this voltage and verifying each block using a sufficiently small voltage as a start voltage. We have proposed a soft writing method that creates an erased state with a narrow distribution width.

The following literature describes in detail the technique of controlling the write operation of the NAND cell type EEPROM by the LSB (local self boost) method and the threshold value of the cell in the erased state by the soft write.

Japanese Patent Application No. 10-104652 (Japanese Patent Application No. 9-104652)
Japanese Patent Application No. 124493) discloses a technique of performing a so-called soft write in which a write operation is performed little by little after erasing data in a NAND cell to make a memory cell in an over-erased state normal (of course, erase verification is also performed). Is disclosed.

Japanese Patent Application No. 9-340971 discloses a NAND
By performing writing (soft writing) and erasing verification little by little after erasing the data in the cell, it is determined that a predetermined number of memory cells have reached a specified threshold value, and the soft writing is terminated. A technique for bringing a memory cell into a normal state has been disclosed.

Japanese Patent Application No. 9-224922 discloses NAND.
During data erasure of the cell, the threshold voltage of the memory cell is monitored by erasure verification and over-erase detection read, and the erasure is performed so that the threshold voltage in the erased state falls between the desired upper limit value and lower limit value. A technique for performing soft writing is disclosed.

FIGS. 16A and 16B show the concept of the above-mentioned software writing method. As shown, the erase distribution after block erasure is very wide (the solid line in FIG. 17B).
INITIAL). However, in most memory cells, a memory cell that is easy to erase is easy to write (slope Tb in FIG. 16A).

Therefore, it is possible to optimize the voltage for batch erasure, the start voltage for soft writing thereafter, and the step-up width, and narrow the erase distribution while repeating the verification for each block (dotted line SOFT in FIG. 16B).
W). The reason why verification is performed for each block is that verification can be performed in a much shorter time than when verifying for each bit.

Thus, it is possible to create a threshold distribution in an erased state having a very narrow distribution as compared with the time of the batch erase. However, this distribution width is naturally greatly affected by variations in the write characteristics within each block.

Therefore, in the control of the erase distribution by the soft writing method, it is considered that the following problem will occur as the miniaturization is advanced in the future.

FIGS. 17A and 17B show the dependence of the write / erase characteristics on the gate length L when the applied voltage and the write / erase pulse width during data write / erase of the cell are constant. Is shown. As shown in FIG. 17A, especially in a region where L is 0.25 μm or less, the L dependence of the writing characteristics becomes very large. This is due to process variations, short channel effects, and the like.

As shown in FIG. 17A, the fact that the L dependency is large means that the write characteristics in a wafer, a chip, and a block vary as L becomes smaller. Since verification at the time of soft programming cannot be performed for each bit due to the restriction of the erase time,
Verify is performed for each block. Therefore, the variation in the write characteristics greatly affects the erase threshold distribution after the soft write. As a result, erroneous write is performed especially on a memory cell miniaturized to a gate length L = 0.25 μm or less. And the fluctuation of the threshold value tends to increase.

As described above, in the NAND cell write method, the LSB (local self-boost) method is a promising method for suppressing erroneous write and threshold fluctuation that occur during a write operation. On the other hand, with the progress of miniaturization and large capacity, it is very difficult to control the threshold distribution in the data erase state, which is important for the LSB method. As a result, the distribution of the threshold voltage of the cells in the erased state is widened, and the reliability such as erroneous writing in the subsequent writing operation is reduced.

The present invention has been made in view of the above circumstances, and the problem is that even if the miniaturization, high integration, and large capacity of the memory cell are advanced, erroneous writing of the memory cell or fluctuation of the threshold value is performed. It is an object of the present invention to provide a nonvolatile semiconductor memory device having a control method capable of further narrowing a threshold distribution of a data erase state of a memory cell in order to reduce the number of times.

[0037]

According to the present invention, there is provided a semiconductor memory device including at least one electrically rewritable nonvolatile memory cell having a charge storage region and a control gate on a semiconductor substrate; A first signal line electrically connected to one end of the memory cell portion and transmitting a potential related to a state of the nonvolatile memory cell; and a second signal line electrically connected to the other end of the memory cell portion A data erase operation for making the threshold value of the nonvolatile memory cell negative, wherein a soft erase operation of gradually moving the threshold value of the nonvolatile memory cell in the negative direction is performed. I do.

According to the present invention, a control method which can further narrow the threshold distribution of the data erased state of the memory cell can be achieved, thereby stabilizing data of a finer memory cell and a multi-valued memory cell. Contribute.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In an LSB (local self-boost) system, an erase threshold distribution is set to a higher value (elimination of over-erasure) and a sufficient distribution is provided within a range where a cell can be read as an erased state. It has already been mentioned that narrowing is important.

As shown in FIG. 17B, the dependence of the erase characteristic on the gate length is much smaller than that of the write characteristic. Therefore, even if the gate length is reduced, the threshold fluctuation due to erasure can be suppressed to a sufficiently small value. The present invention takes advantage of this property.

FIG. 1 is a flowchart showing a method for controlling a data erase operation in a memory cell of a NAND cell type EEPROM according to the nonvolatile semiconductor memory device of the first embodiment of the present invention.

In the present invention, when controlling the threshold distribution of the memory cells to be in the erased state, first, collective writing is performed for each block of the memory cell array to be erased as shown in step S11. Thereafter, as shown in step S12, soft erase is performed for each block using a predetermined voltage as a start voltage. After the erase verify reading in step S13, the threshold value of the cell and the criterion value are compared as shown in step S14. Therefore, when the threshold value of the cell has not reached the determination reference value, the soft erase is further repeated (loop S15). The predetermined voltage of the soft erase is changed from the start voltage. When the threshold values of all the cells reach the determination reference value, the soft erase ends.

The control including the operation of converging the erase threshold of the cell as described above is called a soft erase system. The soft erase method refers to erasure of particularly useful data and erase verification in units of blocks in conjunction with the LSB method, and is essentially different from the erase operation conventionally used.

FIG. 2 is a characteristic diagram showing the concept of the soft erase method. A difference ΔVth in the threshold value between the fastest erased cell and the slowest erased cell is obtained at the time of writing in the process S11 in FIG. This difference ΔVth is considered as the distribution width of the threshold value, and control is performed so as to approach a point where the distribution width is minimized by soft erasure. The details will be described below.

FIG. 3 is a circuit diagram showing a configuration example of a memory cell array in which NAND cells as memory cell units (memory cell units) are arranged in a matrix. In addition,
Here, an example is shown in which eight memory cells are connected in series to form a NAND cell. However, four, sixteen, or thirty-two memory cells may be connected in series to form a NAND cell. The number of memory cells in a NAND cell is not particularly limited.

The control gate of the memory cell (word line WLx
(x = 1, 2,... 8)), the first selection gate line SGD, and the second selection gate line SGS are arranged in the row direction. Usually 1
A set of memory cells connected to one control gate is called one page, and a set of pages sandwiched between a pair of drain-side and source-side select gate lines (SGD and SGS) is referred to as one NAND block or simply one block. Call. 1
The page is composed of, for example, 256 bytes (256 × 8) memory cells. Writing is performed almost simultaneously on the memory cells for one page. One block is, for example, 2048
It is composed of byte (2048 × 8) memory cells. Memory cells for one block are erased almost simultaneously.

FIGS. 4A to 4D are explanatory diagrams sequentially showing the soft erase method of the present invention performed on the NAND cell as shown in FIG.

As shown in FIG. 4A, for example, a predetermined high voltage Vpp, for example, 20 V is applied to the word lines (WL1 to WL8) connected to all the bits in the block to be erased in FIG. Then, writing is performed (corresponding to the processing S11 in FIG. 1). At this time, each bit line BL is set to 0V,
The select gate line SGD on the bit line side has a predetermined positive voltage Vsg.
d, the source line SRC is at 0 V or V
s, the select gate line SGS on the source line side is 0V.

At this time, the write voltage Vpp is set to 20
Not only V, but all the bits have a sufficiently high threshold voltage (preferably, for example, about 1.5 V, which is highly dependent on the erasing speed, the neutral threshold value of the memory cell, etc., and is therefore optimized. Vpp is selected.

Next, as shown in FIG. 4B, 0 V is applied to all the word lines (WL1 to WL8) of the block to be erased.
Alternatively, a sufficiently small voltage is applied even if the voltage is positive or negative, and a start voltage of Vpp, for example, 12 V is applied to the well substrate to perform erasing (corresponding to the process S12 in FIG. 1). At this time, for example, the same voltage as that of the well is applied to the word line of the block where erasing is not performed to prevent erasing.

Next, the erased state of this block is read out for each block (corresponding to the processing S13 in FIG. 1). As a method for this, for example, all the word lines (WL
For example, 0V is applied to 1 to 8), and a positive voltage is applied to the channel of the memory cell in this block from the source line SL.

At this time, if the memory cell with the highest threshold value among the memory cells in this block is still in the written state, the potential of the bit line does not rise sufficiently. Therefore, it is determined that the soft erasure is not yet sufficient (corresponding to the processing S14 in FIG. 1). Figure 4 in that case
As shown in FIG. 1C, another soft erase is performed (FIG. 1).
Loop S15). The second erase voltage is different from the start voltage, and is performed at, for example, 12.2 V higher than the start voltage by 0.2 V (the step voltage is 0.2 V).

The start voltage and the step voltage of Vpp are selected so that the threshold distribution width after the soft erase is minimized and the soft erase time is minimized, and is not limited to the above. Specifically, it depends on the neutral threshold value of the memory cell, the coupling ratio that determines the write / erase characteristics, and the like.

Thereafter, the verify read of the memory cell is similarly performed for each block. If the memory cell having the highest threshold value in the block does not reach a certain reference value, the memory cell is further subjected to, for example, 0.2V. Step-up V
The soft erase is performed at pp, and this is repeated (loop S15 in FIG. 1).

Here, assuming that the threshold voltage for judging the end of the soft erase is, for example, -0.5 V, the bit line is shifted from the source line by 0.5 at the step S13 in FIG.
V potential is applied. Thereby, the processing S14 of FIG.
And whether the potential of the bit line is 0.5 V or more,
A verify operation after data erasure may be performed by monitoring whether the voltage is 5 V or less. That is, the memory cell having the highest threshold value is the desired threshold value (determination reference value).
, The potential of the bit line sufficiently rises to 0.5 V or more, and it is determined that the soft erase is completed (FIG. 4).
(D)).

In the above example, the desirable erase distribution is such that the highest threshold voltage is about -0.5 V and the lowest threshold voltage is about -2.5 V, but the narrower the distribution width, the better. . Here, the reason why the desirable threshold distribution at the time of erasing is -0.5 to -2.5 V is because the threshold distribution width is desirably 2 V or less. Therefore, it is not particularly limited to the values of -0.5V and -2.5V.

In the above example, an example of the operation control of the erase verify read has been described. However, the present invention is not limited to this.
In short, any method may be used as long as it can read the negative threshold value for each block. Further, in the above example, it is detected that the higher erasing threshold is below the desired upper limit, but it may be detected that the lower erasing threshold is above the desired lower limit.

In the conventional method, the control of the erasing threshold is performed by soft writing, and therefore, as shown in FIG.
The write characteristics are largely dependent on the gate length. Therefore, particularly when the gate length is reduced to 0.25 μm or less, the threshold distribution width after writing in the block becomes large, and it becomes extremely difficult to control the erase threshold suitable for miniaturization. .

On the other hand, as shown in FIG. 17B, the dependence of the erase characteristic on the gate length is very small, so that the soft erase method of the present invention becomes very effective. As a result, for example, even when the gate length is reduced to 0.25 μm or less, the threshold distribution width after soft erasure can be sufficiently suppressed. Further, since the control of the erase threshold value is performed with high precision, the soft erase method of the present invention is very effective also in a multi-valued memory in which the threshold value needs to be separated into a plurality.

By using the soft erase method of the present invention, the distribution of threshold values for erasing data is made very narrow. A small number of memory cells can be realized.

The data writing to the cell is performed by converging the distribution of the erase threshold value by the soft erase of the present invention.
It is performed subsequently. That is, the LS described in the prior art
This is data writing using the B (local self boost) method.

FIG. 5 shows a unit 2 of the NAND cell shown in FIG.
FIG. 4 is a circuit diagram of the extracted data, showing a relationship between voltages at respective terminals in data writing using the LSB method.

In FIG. 5, when the selected control gate of the selected block, that is, the selected word line is, for example, WL2, at the time of the write operation, the high voltage Vpp (for example, 18
V) is applied. 0 V is applied to the unselected word lines (here, both sides) WL1 and WL3 adjacent to the selected word line WL2. Vp is applied to other unselected word lines.
ass (0 V lower than Vpp and a voltage approximately intermediate between Vpp, for example, 9 V) is applied. However, as described in the related art, the voltage applied to the unselected word lines WL1 and WL3 may be any positive voltage less than Vpass.

A predetermined positive voltage Vs is applied to the select gate line SGD.
gd. The selection gate line SGS has 0 V (Vs
s). All word lines and all select gates of the unselected block are at 0 V (Vss). Write operations are usually
The operation is performed in order from the memory cell farthest from the bit line to the memory cell closest to the bit line.

For example, when writing "0" data (here, data having a positive threshold value) to the memory cell MC12, the bit line BL is set to 0V. Since the memory cells existing on the bit line side of the selected memory cell are always in the erased state, even if the word line next to the selected memory cell is set to 0 V, the write voltage (0 V) of the bit line is selected. Transferred to the memory cell. In the selected memory cell, electrons move from the substrate to the floating gate, and the threshold value of the selected memory cell becomes positive.

At the same time, to write "1" data (data in which the threshold value becomes negative here) to the memory cell MC22, that is, to keep the erase state in the MC22, write the bit line BL to the non-selected positive. V which is the voltage of
bl. The selection gate line SGD is set at the positive voltage Vsgd, and usually, Vbl ≦ Vsgd.
Therefore, in this case, the transistor connected to the selection gate line SGD is turned off, and the channel (and n-type diffusion layer) of each memory cell is in a floating state. As a result, the channel potential of the selected memory cell MC22 having the high voltage Vpp applied to the word line and the channel potential of the non-selected memory cell having the voltage Vpass applied to the word line are increased.

The memory cells MC21 and MC23 on both sides of the selected memory cell MC22 are cut off by the back bias effect due to the channel potential raised by the voltage Vpass. At this time, if the high voltage Vpp is applied to the selected memory cell MC22, this one memory cell MC22
The channel potential rises due to the coupling between 22 and its channel and source / drain diffusion layers.

The channel potential at this time is such that Vpp is 18
V, if the channel boost ratio is 0.5,
It rises to about 9V. That is, the potential difference between the word line and the channel becomes small, and becomes sufficient as the write inhibit voltage.

The word lines on both sides of the selected word line are
The voltage does not necessarily need to be 0 V, and may be any voltage that is small enough to bring the memory cell into the cutoff state. A negative voltage may be applied to a word line on the source line side adjacent to the selected word line. Further, of the word lines adjacent to the selected word line, a voltage small enough to cut off the memory cell is applied only to the word line on the source line side, and writing is performed in order from an arbitrary memory cell in the NAND cell. You may do so.

The greater the Vpass voltage is, the greater the threshold voltage variation of the memory cell belonging to the non-selected bit line to which "0" is not written, that is, the memory cell to which "1" data is written, connected to the selected word line WL2. Can be kept small. However, Vp belonging to the selected bit line
The Vpass voltage cannot be increased so much because the threshold voltage of the memory cell to which the “ass” is given is greatly changed.

FIG. 6 shows the change in the threshold value of the erased state and the Vpass voltage of the memory cells (MC22) to which "1" data is written in the memory cells MC21 and MC23 to which 0 V is applied to the word line. Shows the relationship.
As can be seen from FIG. 6, for example, in order to prevent the threshold value from changing when Vpass is 8 V, the lowest threshold value (Vth) of the cell in the erased state is about-.
It needs to be higher than 2.5V.

The threshold value (Vt) of the cell in the erased state
The highest one of h) is preferably lower than, for example, -0.5 V from the viewpoint of securing a read margin. Thus, −2.5 V <Vth <−0.5 V is an allowable range of the threshold distribution here. Therefore, in this case, it is necessary to keep the threshold distribution width smaller than about 2V.

Further, as the distribution width of the threshold value in the erased state of the cell can be made smaller, the highest threshold value of the erased threshold value distribution becomes, for example, -1V.
The read margin can be further reduced, and the reliability is improved.

{Second Embodiment} FIG. 7 shows a second embodiment of the present invention.
4 is a flowchart illustrating a method of controlling a data erase state in a memory cell of a NAND cell type EEPROM according to the nonvolatile semiconductor memory device of the embodiment.

In this embodiment, in order to further converge the distribution of the erase threshold, soft erase is performed and then soft write is performed. As a result, LS with less erroneous writing
A B (local self boost) type NAND cell type nonvolatile semiconductor memory device is realized.

That is, as shown in FIG. 7, when controlling the threshold distribution of the memory cells to be erased, first, writing is performed for each block as shown in step S21. Thereafter, as shown in step S22, soft erasing is performed for each block using a predetermined voltage as a start voltage. After the verify reading in step S23, the threshold value of the cell is compared with the determination reference value as shown in step S24. Therefore, if the threshold value of the cell has not reached the determination reference value, the soft erase is further repeated (loop S25). The predetermined voltage of the soft erase is changed from the start voltage. At the time when the threshold values of all the cells reach the judgment reference value (here, when the higher erasing threshold value advances to the lower one and reaches the judgment reference value), the soft erasure is ended.

Thereafter, as shown in steps S26 to S29, soft writing and verify reading are repeated, and the lower erase threshold is guided to be higher. That is, after the verify reading in step S27,
As shown at 28, the higher threshold value of the cell is compared with the criterion value. Therefore, if the higher threshold value of the cell has not reached the determination reference value, the soft writing is further repeated (loop S29). The predetermined voltage for soft writing is changed from the start voltage. When the threshold value of at least one cell reaches the judgment reference value (here, the higher erasing threshold value advances to the higher one and reaches the judgment reference value), the soft programming ends.

FIGS. 8A and 8B are distribution diagrams of the erase threshold for explaining the above operation example. First, for soft erasure, the determination reference value is set to, for example, -0.8V. A soft erase operation is performed (S22 to S2 in FIG. 7).
5) When the memory cell having the highest threshold value in the erase threshold distribution becomes lower than -0.8 V, the soft erase is terminated (FIG. 8A).

For the subsequent soft writing, the judgment reference value is set to, for example, -0.5V. A soft write operation is performed (S26 to S29 in FIG. 7), and when the memory cell having the highest threshold in the erase threshold distribution exceeds -0.5 V, the soft write is terminated (FIG. 8B )).

As a verifying method, a margin voltage of, for example, 0.3 V is applied as a word line voltage. In this case, if the bit line potential is 0.8 V as a fixed criterion, the threshold value of the memory cell is higher than -0.8 V,-
It can be determined whether or not the threshold value does not exceed 0.5 V. That is, a failure can be determined when the threshold value is -0.5 V or more (see Japanese Patent Application No. 9-340971).

The series of operations of the soft erasure and the soft writing are performed once or several times (a loop S30 indicated by a dotted line in FIG. 7) by appropriately selecting a judgment reference value. Can also create a narrower erase threshold distribution. With the very narrow erase threshold value thus formed, writing can be performed with a very small Vpass voltage (for example, 7 V), and further erroneous writing can be further prevented. realizable.

FIG. 9A is a waveform diagram showing a control example of the start voltage and the step voltage of the soft erase applied to the present invention, and FIG. 9B is a diagram showing the soft erase for one NAND cell in one block. FIG. 4 is a circuit diagram showing an example of voltage application in FIG.

The voltage Vpwell applied to the P well is
For example, with a start voltage of 12V, the voltage is stepped up by 0.2V. Each application time is 15μs
c, the voltage Vpwell finally applied to the well
Is controlled so that it can be stepped up to 14V. Of course, in the step-up stage before reaching 14 V, if the condition of the set erase threshold is satisfied, the soft erase operation ends. Such control can be applied to the soft erase operation of the first and second embodiments.

FIG. 10A is a waveform diagram showing an example of control of a start voltage and a step voltage for soft writing applied to the present invention, and FIG. 10B shows 1N in one block.
FIG. 9 is a circuit diagram showing an example of voltage application in soft writing to an AND cell.

The voltage Vpwell applied to the well is set to 0V
And Voltage Vpp applied to word line (control gate)
Is stepped up in steps of 0.2 V, for example, with 12 V as a start voltage. Each application time is 15μ
sec, and the voltage finally applied to the word line is 1
It is controlled so that it can be stepped up to 4V. Of course, in the step-up stage before the voltage reaches 14 V, if the condition of the set erase threshold is satisfied, the soft write operation ends. Such control can be applied to the soft write operation of the second embodiment.

The start voltage and step voltage of Vpwell and Vpp are such that the erase threshold distribution width after performing soft erase and soft write is the smallest, and the time to converge the erase threshold is the shortest. It is chosen to be useful and is not limited to the above. It depends on the neutral threshold value of the memory cell and the coupling ratio that determines the write / erase characteristics.

FIG. 11 is a characteristic diagram showing a threshold distribution for classifying each storage data of a memory cell relating to a quaternary multi-level memory according to the first or second embodiment.
Here, one data (“11”) is on the erase side (threshold is negative) and three data (“10”, “01”, “00”) is on the write side (threshold is positive). Indicates that they can be divided.

A method of dividing three data having a positive threshold value is described, for example, in Japanese Patent Application No. 10-104652. As an example, this is realized by making the application time of the control voltage necessary for writing different for each data.

That is, in the data "10" write operation, the time during which the write selection voltage of 0 V is applied to the bit line is shorter than in the data "01" and "00" write operations. This is because the amount of electrons injected into the floating gate of the memory cell to store data “10” may be smaller than the amount of electrons injected to store data “01” and “00”.

Similarly, in the data “01” write operation, the time during which the 0V write selection voltage is applied to the bit line is shorter than in the data “00” write operation. At the time of the data “00” write operation, the time during which the 0V write selection voltage is applied to the bit line is set to the data “1”
0 and 01. For example, data "1"
The voltage application time for 0V write selection to the bit lines for writing “0”, “01”, and “00” is 1 μs each.
The write pulse length may be controlled to ec, 5 μsec, 25 μsec.

Data is read from the selected block in the selected block, and the read voltage Vread is applied to the word lines of non-selected memory cells other than the selected memory cell.
(E.g., 3.5 V) to turn on and apply a predetermined voltage to the word line of the selected memory cell.

As the predetermined voltage, a voltage that can use the fact that the ON voltage of the memory cell differs depending on the threshold information of the memory cell is selected. That is, the selected memory cell is rendered conductive (or non-conductive) by a predetermined voltage, and by detecting a bit line potential that fluctuates due to a current flowing on the bit line side, one of a plurality of types is determined. .

When setting the data storage of the multi-valued memory for separating each of the four-valued storage data, the soft erase method of the present invention is used. As a result, the distribution of the threshold value when data is erased (set to "11" data) can be made very narrow, and in the subsequent data write operation, there is very little threshold change and erroneous writing. A memory cell can be realized.

FIG. 12 is a block diagram showing the configuration of a quaternary storage NAND flash memory according to the first or second embodiment.

Bit lines are controlled for a memory cell array 1 including a plurality of bit lines, a plurality of word lines, and a common source line and having electrically rewritable memory cells arranged in a matrix. Line control circuit 2 and word line control circuit 6 are provided.

The bit line control circuit 2 reads data of the memory cells in the memory cell array 1 via the bit lines, detects the state of the memory cells in the memory cell array 1 via the bit lines, and controls the bit lines. A write control voltage is applied to the memory cells in the memory cell array 1 via the memory cell to write data to the memory cells.

The bit line control circuit 2 includes a plurality of data storage circuits for separating quaternary data (Japanese Patent Application No. Hei 10-1).
04652, etc.). The data of the memory cell read from the data storage circuit selected by the column decoder 3 is output to the outside from the data input / output terminal 5 via the data input / output buffer 4. Write data externally input to the data input / output terminal 5 is input via the data input / output buffer 4 to the data storage circuit selected by the column decoder 3 as initial control data.

The word line control circuit 6 selects a word line in the memory cell array 1 and applies a voltage necessary for reading, writing or erasing.

The memory cell array 1, bit line control circuit 2, column decoder 3, data input / output buffer 4, and word line control circuit 6 are controlled by a control signal and control voltage generation circuit 7. The control signal and control voltage generation circuit 7 is controlled by a control signal input to a control signal input terminal 8 from outside.

The control signal and control voltage generation circuit 7 generates a voltage used in the algorithm shown in the flowchart of FIG. 1 or 7 of the present invention. That is, the write system voltage Vpp (variable) for the block batch write or normal write for realizing the erased state in which the threshold distribution of the memory cell is very narrow, or the soft write after the soft erase, Well voltage Vpwell (variable) and read system voltage Vread for a soft erase operation realizing an erase state with a very narrow threshold distribution
(Variable) and the like from Vss (0 V) to Vcc (eg, 3.3
It is generated by boosting and controlling the power supply voltage of V).

According to the first and second embodiments, the EE
Within the range in which the PROM cell can be read as an erased state, the erase threshold distribution can be set higher (elimination of over-erasure) and the distribution can be made sufficiently narrow.

As a result, in writing in the LSB (local self-boost) method, a smaller Vp
It is possible to operate with the ass voltage, and erroneous writing of the memory cell or fluctuation of the threshold value can be greatly reduced. Therefore, the reliability at the time of writing is significantly improved as compared with the related art.

In addition, the present invention can be expected to realize a highly reliable nonvolatile semiconductor memory device which can cope with miniaturized binary and multi-level memories, particularly with a rule of 0.25 μm or less.

The technique of introducing the block collective writing → soft erasing operation of the present invention is not limited to the LSB (local self-boost) method, but also works effectively for various EEPROMs employing the self-boost writing method. .

The technique of the present invention described above relates to the structure of a memory cell, the structure of element isolation (LOCOS, trench), the number of select gate transistors, the type of data that can be stored in a memory cell (multi-valued memory), the manufacturing method, and the like. Demonstrates its effect without depending on.

Further, the technique of the present invention for converging a reference threshold value (erasing threshold value) is used when the threshold distribution of all data is on the negative side, or when the multi-valued data is more than four-valued. This is also effective when storing one of the data.

[0107]

As described above, according to the present invention, when controlling the threshold distribution of the memory cell to be erased, the threshold of the memory cell is gradually moved in the negative direction. Adopt soft erase operation. As a result, even in a miniaturized memory cell, the threshold distribution in the data erased state can be significantly narrowed. As a result, in data writing, erroneous writing of a memory cell or fluctuation of a threshold value can be greatly reduced. A reliable nonvolatile semiconductor memory device can be provided.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a method for controlling a data erase operation in a memory cell of a NAND cell type EEPROM according to a nonvolatile semiconductor memory device of a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing the concept of a soft erase method.

FIG. 3 is a circuit diagram showing a configuration example of a memory cell array in which NAND cells are arranged in a matrix.

FIGS. 4A to 4D show NAs as shown in FIG.
FIG. 4 is an explanatory view showing a soft erase method of the present invention for an ND cell in order.

FIG. 5 is a circuit diagram showing two NAND cell units extracted from FIG. 3;

FIG. 6 is a characteristic diagram showing a relationship between a threshold value in an erased state of a memory cell to which 0 V is applied to a word line, a Vpass voltage, and a threshold value variation of a memory cell into which "1" data is written.

FIG. 7 is a flowchart showing a method for controlling a data erase state in a memory cell of a NAND cell type EEPROM according to the nonvolatile semiconductor memory device of the second embodiment of the present invention.

FIGS. 8A and 8B are distribution diagrams of erase thresholds for explaining the above operation example.

9A is a waveform diagram showing a control example of a start voltage and a step voltage of soft erase applied to the present invention, and FIG. 9B is a voltage application in soft erase to one NAND cell in one block. FIG. 4 is a circuit diagram showing an example.

FIG. 10A is a waveform diagram showing a control example of a start voltage and a step voltage of soft writing applied to the present invention, and FIG. 10B is a voltage application in soft writing to one NAND cell in one block. FIG. 4 is a circuit diagram showing an example.

FIG. 11 is a characteristic diagram showing a threshold distribution for classifying each storage data of a memory cell relating to a quaternary multi-level memory according to the first or second embodiment;

FIG. 12 is a block diagram showing a configuration of a quaternary storage NAND flash memory according to the first or second embodiment.

FIGS. 13A and 13B each show one NA relating to a memory cell array of a NAND cell type EEPROM;
FIG. 2 is a plan view and an equivalent circuit diagram of an ND cell portion.

14A is a sectional view taken along line AA shown in FIG. 13A, and FIG. 14B is a sectional view taken along line B-A shown in FIG.
Sectional drawing along the B line.

FIG. 15 is a cross-sectional view of another example of FIG. 14B when trench element isolation is used.

FIGS. 16A and 16B are characteristic diagrams each showing a concept of a soft writing method.

FIGS. 17A and 17B are characteristic diagrams showing the dependence of data write / erase characteristics of a cell on the gate length L. FIGS.

[Explanation of symbols]

 S11 to S15: each processing SGD: first selection gate line SGS: second selection gate line WL: word line (control gate) SRC: source line BL, BL (O), BL (E): bit line

Claims (10)

[Claims] 1. A memory cell section including at least one electrically rewritable nonvolatile memory cell having a charge storage region and a control gate on a semiconductor substrate, and electrically connected to one end of the memory cell section. A first signal line for transmitting a potential related to a state of the nonvolatile memory cell; and a second signal line electrically connected to the other end of the memory cell portion. A non-volatile semiconductor memory device according to claim 1, wherein a soft erasing operation for gradually moving a threshold value of said non-volatile memory cell in a negative direction is performed with respect to a data erasing operation for making a threshold value negative. 2. A memory cell unit including at least one electrically rewritable nonvolatile memory cell having a charge storage region and a control gate on a semiconductor substrate, and electrically connected to one end of the memory cell unit. A first signal line for transmitting a potential related to a state of the nonvolatile memory cell; and a second signal line electrically connected to the other end of the memory cell portion. Concerning the data erasing operation for making the threshold value negative, the threshold value of the nonvolatile memory cell is gradually increased in the negative direction. A non-volatile semiconductor memory device, which performs a soft write operation in which it is gradually moved in a positive direction. 3. The soft erase operation is repeated alternately with an erase verify operation for checking an erase state of a memory cell in the memory cell section, and the soft erase operation is terminated based on the erase verify operation. The nonvolatile semiconductor memory device according to claim 1, wherein: 4. The soft write operation is alternately repeated with a verify operation for confirming an erased state of a memory cell in a previous memory cell portion, and the soft write operation is terminated based on the verify operation. Item 2
14. The nonvolatile semiconductor memory device according to claim 1. 5. A memory cell unit is formed by connecting a plurality of electrically rewritable nonvolatile memory cells each having a charge storage region and a control gate on a semiconductor substrate, and at least a plurality of the memory cell units are arranged. A memory cell array including a block constituted by: a first cell electrically connected to one end of the memory cell unit and transmitting a potential related to a state of the nonvolatile memory cell;
And a second signal line that is electrically connected to the other end of the memory cell unit. The data erase operation for setting the threshold value of the nonvolatile memory cell to a negative value is performed in block units. A nonvolatile semiconductor memory device, wherein a soft erase operation for gradually moving a threshold value of a nonvolatile memory cell in a negative direction is performed while repeating a verify operation. 6. The soft erase operation is started from a predetermined start voltage as a control voltage for soft erase, and is performed in a step-up manner in which the control voltage is increased with a predetermined step width. Wherein the soft erase operation is terminated when it is detected by the verify operation inserted before the step-up that all the memory cells in the block have become smaller than the reference value. 6. The nonvolatile semiconductor memory device according to 5. 7. A memory cell unit is formed by connecting a plurality of electrically rewritable nonvolatile memory cells each having a charge storage region and a control gate on a semiconductor substrate, and at least a plurality of the memory cell units are arranged. A memory cell array including a block constituted by: a first cell electrically connected to one end of the memory cell unit and transmitting a potential related to a state of the nonvolatile memory cell;
And a second signal line that is electrically connected to the other end of the memory cell unit. The data erase operation for setting the threshold value of the nonvolatile memory cell to a negative value is performed in block units. A soft erase operation for gradually moving the threshold value of the nonvolatile memory cell in the negative direction is performed while repeating a verify operation. A nonvolatile semiconductor memory device wherein a soft write operation to be moved is performed while repeating a verify operation. 8. The soft erase operation is started from a predetermined start voltage as a soft erase control voltage, and is performed in a step-up manner in which the soft erase control voltage is increased with a predetermined step width. The verify operation inserted before the step-up of the soft erase control voltage terminates the soft erase operation when it is detected that all the memory cells in the block have become smaller than the first determination reference value. The soft write operation is started from a predetermined start voltage as a soft write control voltage, and is performed in a step-up manner in which the soft write control voltage is increased with a predetermined step width. The verify operation inserted before the step-up of the control voltage causes the 8. The nonvolatile semiconductor memory device according to claim 7, wherein said soft write operation is terminated when it is detected that all the memory cells have become larger than a second determination reference value. 9. The data erasing operation according to claim 1, further comprising a writing operation for once moving a threshold value of the nonvolatile memory cell in a positive direction before performing the soft erasing operation. 9. The nonvolatile semiconductor memory device according to any one of items 8. 10. A nonvolatile memory cell, comprising: a plurality of nonvolatile memory cells connected in series between the first and second signal lines;
A first voltage lower than a write voltage is applied to a control gate of a memory cell adjacent to a selected memory cell in the NAND type cell during data writing performed after the data erasing. 10. The method according to claim 1, wherein a second voltage intermediate between the write voltage and the first voltage is applied to control gates of the remaining memory cells other than the selected memory cell in the pattern cell. Or a non-volatile semiconductor storage device according to the above.