JP2000235516A - Memory system with operation function, method for controlling memory to be used for the system and recording medium recording control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a memory system with an operation function capable of quickly processing much data stored in a main storage without deteriorating the performance of a processor. SOLUTION: An instruction decoded by an instruction decoder 53 is sent to a control circuit 54 and an arithmetic unit 6 is controlled as necessary. The unit 6 receives data from a system bus control circuit 51 and a memory element control circuit 52, executes operation corresponding to an instruction outputted from the circuit 54 and transfers the operation result to the circuit 52.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system with an arithmetic function, a memory control method used therefor, and a recording medium on which a control program is recorded, and more particularly to a memory system having a cache and a main memory having a hierarchical memory structure.

[0002]

2. Description of the Related Art Conventionally, in a hierarchical memory structure,
In order to improve the performance of the entire system, a high-speed and low-capacity cache is provided near the processor, and a low-speed and large-capacity memory is provided as a main memory.

In such a system as described above, a processor and a main memory are connected on a system bus. When an operation is performed on data from the main memory in accordance with an instruction (command) from the processor, the processor and the main memory are used. After taking all the data and the processor performing an operation on the data from the main memory, the result is written back to the main memory.

In such a hierarchical memory configuration, generally, the performance has been promoted by contriving to improve the speed of the processor and the hit ratio of the cache. Since the speed improvement cannot keep up, the result that access to the main memory relatively deteriorates the performance is becoming remarkable.

[0005] In order to prevent this performance degradation, in the field of image processing for handling a large amount of data, Japanese Patent Laid-Open No. 8-305625 is disclosed.
As disclosed in Japanese Unexamined Patent Publication, a method of providing an arithmetic processing function in a semiconductor memory has been proposed in order to speed up texture mapping processing in three-dimensional graphics.

In the technique disclosed in this publication, a decimal address including a decimal component of an original image which does not generally take integer coordinates is given as a memory address as it is, and data corresponding to the integer address is held in a semiconductor memory. A memory cell and an arithmetic circuit for performing an interpolation operation based on data and a decimal component corresponding to an integer component in a decimal address read from the memory cell are provided.

[0007]

In the conventional memory system described above, in the case of a hierarchical memory structure, the speed of the main memory cannot keep up with the speed of the processor. However, there is a problem that performance degradation is caused by performing the above.

[0008] The performance degradation in accessing the main memory can be prevented by using the technique described in the above publication in the field of image processing. It cannot be used in fields that make heavy use of vector calculations and scientific calculations,
In a field where vector operations and scientific calculations are frequently used, performance degradation is caused by accessing the main memory.

[0009] Further, for multimedia processing and the like, the amount of data to be handled is rapidly increased and the increase in cache capacity cannot keep up, and it is required to access the main memory at a higher speed than before. .

An object of the present invention is to provide a memory system with an arithmetic function capable of solving the above problems and processing a large amount of data in the main memory at high speed without deteriorating the performance of the processor. It is in.

[0011]

A memory system with an arithmetic function according to the present invention is a memory system with an arithmetic function comprising a main memory and a memory control device for controlling access to the main memory. In the memory control device, there is provided arithmetic means for performing an arithmetic operation on the data read from the main memory in accordance with the contents of the instruction.

Another memory system with an arithmetic function according to the present invention is a multiprocessor system in which a plurality of central processing units are connected on a common system bus, wherein a main memory and the main memory are connected to the system bus, and A memory system with an arithmetic function, comprising: a memory control device for controlling access to a main memory, wherein the memory means for performing an arithmetic operation on data read from the main memory in accordance with an instruction from the central processing unit. It is provided inside the control device.

Another memory system with an arithmetic function according to the present invention is a multiprocessor system in which a plurality of central processing units are connected to corresponding system buses, respectively. A memory system with an arithmetic function comprising a plurality of memory controllers connected to a bus and controlling access to each of said plurality of main memories, wherein said memory system reads data from said main memory in response to an instruction from said central processing unit. Operation means for performing an operation on the data is provided in each of the plurality of memory control devices.

A memory control method according to the present invention is a memory control method for a memory system having an arithmetic function comprising a main memory and a memory control device for controlling access to the main memory. The memory control device further comprises a step of performing an operation on the data read from the main memory in response.

According to another memory control method of the present invention, in a multiprocessor system in which a plurality of central processing units are connected on a common system bus, a main memory and the main memory are connected to the system bus and the main memory is connected. A memory control method for a memory system with an arithmetic function, comprising: a memory control device for controlling access to the memory. The method further comprises the step of: performing an arithmetic operation on data read from the main memory in accordance with an instruction from the central processing unit. It is provided in the memory control device.

According to another memory control method according to the present invention, in a multiprocessor system in which a plurality of central processing units are connected to corresponding system buses, a plurality of main memories and the plurality of main memories are connected to corresponding system buses. A memory control method for a memory system with an arithmetic function comprising a plurality of memory controllers connected to each other and controlling access to each of the plurality of main memories, wherein the main memory is controlled in accordance with an instruction from the central processing unit. A step of performing an operation on the data read from the plurality of memory controllers.

A recording medium on which a memory control program according to the present invention is recorded is a memory system having an arithmetic function comprising a main memory and a memory control device for controlling access to the main memory. A storage medium storing a memory control program for controlling access, wherein the memory control program causes the memory control device to perform an operation on data read from the main storage in accordance with an instruction from a central processing unit. I'm making it.

According to another aspect of the present invention, there is provided a recording medium storing a memory control program according to the present invention, wherein a main memory and the main memory are connected to the system bus in a multiprocessor system in which a plurality of central processing units are connected on a common system bus. A memory control program for causing the memory control device to control access to the main storage in a memory system with an arithmetic function comprising a memory control device for controlling access to the main storage. The memory control program causes the memory control device to perform an operation on the data read from the main storage according to an instruction from the central processing unit.

According to another aspect of the present invention, there is provided a recording medium on which another memory control program is recorded, in a multiprocessor system in which a plurality of central processing units are respectively connected to corresponding system buses, a plurality of main memories and a plurality of the main memories. A memory system having an arithmetic function, comprising a plurality of memory controllers connected to a corresponding system bus and controlling access to each of the plurality of main memories, wherein the memory controller controls the access to the main memories. A storage medium recording a memory control program, wherein the memory control program causes each of the plurality of memory control devices to perform an operation on data read from the main storage in accordance with an instruction from the central processing unit. I have.

That is, in the memory system with an arithmetic function of the present invention, in a memory system of a general information processing apparatus, an arithmetic function of relatively simple instructions is provided inside the memory control device.

More specifically, in the memory system with an arithmetic function according to the present invention, in a multiprocessor system in which a plurality of processors are connected on a common system bus,
An arithmetic unit is provided inside a memory control unit that connects the system bus and the main memory.

This arithmetic unit uses data copy, logical operation,
It has a relatively simple operation function such as addition, subtraction, multiplication, etc., performs an operation on data from the main memory according to an instruction (command) from the processor, and writes the result back to the main memory without outputting it to the system bus. The operation is called.

Therefore, the load on the processor and the bus can be reduced and the memory transfer can be reduced, as compared with a system in which all data is stored in the processor and then the result is written back to the main memory as in the conventional system. Time can be saved, and high-speed operation can be performed on a large amount of data.

[0024]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an information processing apparatus using a memory system with an arithmetic function according to one embodiment of the present invention. In the figure, an information processing apparatus according to an embodiment of the present invention includes a plurality of processors 1 and 2, a plurality of cache memories 3 and 4 corresponding to them, a memory control device 5, a memory element (main storage) 7, It is composed of an input / output control device 8 and an input / output device 9.

A plurality of processors 1 and 2, a memory controller 5 and an input / output controller 8 are connected to a system bus 100, respectively.
Connected to each other. Multiple processors 1,
2 is a high-speed and small-capacity cache memory 3,
4 are connected.

The memory control device 5 includes a cache memory 3,
4 controls the large-capacity memory element 7, reads and writes information stored in the memory element 7 according to an instruction from the system bus 100, and transfers data to the system bus 100 as necessary. Is output.

An arithmetic unit 6 for performing relatively simple arithmetic operations is stored in the memory control unit 5, which also operates on the information stored in the memory element 7 in accordance with an instruction from the system bus 100. An operation is performed in which an operation is performed and the operation result is written back to the memory element 7 again.

The input / output control device 8 controls the input / output device 9, and in order to reduce the load on the processors 1 and 2 for input / output operations, the input / output device 9 and the memory control device 5 are connected to each other. Direct data transfer (DMA: Direct Mem)
(Access Control).

FIG. 2 is a block diagram showing the configuration of the memory control device 5 of FIG. In the figure, a memory control device 5 includes a system bus control circuit 51 for controlling an interface with the system bus 100, a memory device control circuit 52 for controlling the memory device 7, and an instruction for decoding an instruction from the system bus 100. It is composed of a decoder 53, a control circuit 54 for controlling each circuit, and the arithmetic unit 6 described above.

The instruction decoded by the instruction decoder 53 is sent to the control circuit 54, and the control of the arithmetic unit 6 is performed as required. The arithmetic unit 6 includes a system bus control circuit 51
And the data is received from the memory element control circuit 52, an operation is performed according to the instruction of the control circuit 54, and the operation result is passed to the memory element control circuit 52.

FIG. 3 is a flowchart showing the processing operation of the control circuit 54 of FIG. The processing operation of the control circuit 54 in the memory control device 5 will be described with reference to FIGS. Note that the processing operation shown in FIG. 3 is realized by the control circuit 54 executing a program in a control memory (not shown), and the control memory is a ROM (read only memory).
And an IC (integrated circuit) memory.

First, the operation in the case of data copy, that is, in the case where the read address is one address and the write address is one address will be described. Since there is only one read target address, only one read address is specified from the processor 1 and a command similar to a normal read command is sent to the memory controller 5 by the system bus 100.
Sent through.

This command instructs the reading of data from the memory element 7, but the read data is not sent to the system bus 100 but sent to the arithmetic unit 6 in the memory controller 5. That is, the read command is decoded by the instruction decoder 53 and sent to the control circuit 54.

When a command is input from the processor 1 (step S1 in FIG. 3), if the command is to read data from the memory element 7 (step S2 in FIG. 3), the control circuit 54 sets the memory element control circuit 52 to The data read from memory element 7 through system bus control circuit 51
(Step S3 in FIG. 3).

If the command from the processor 1 is a data write to the memory element 7 (step S4 in FIG. 3), the control circuit 54 transfers the data received from the system bus 100 via the system bus control circuit 51 to the The data is written into the memory element 7 via the memory element control circuit 52 (step S5 in FIG. 3).

Further, if the command from the processor 1 is a command indicating processing using the arithmetic unit 6 (in this case, a data copy command), the control circuit 54 (FIG. 3)
Step S6): Instruct each of the system bus control circuit 51, the memory element control circuit 52, and the arithmetic unit 6 to perform arithmetic on read data from the memory element 7 and write it back to the memory element 7. A processing operation is performed (steps S7 to S11 in FIG. 3).

That is, the read data from the memory element 7 is sent from the memory element control circuit 52 to the system bus control circuit 51. The control circuit 54 recognizes that the data is a copy, and the system bus control circuit 51 An instruction is given to the device 6, and the system bus control circuit 51 inhibits data transmission to the system bus 100, and the arithmetic device 6 stores the data instead.

The arithmetic unit 6 performs an operation in accordance with the instruction of the control circuit 54, but in the case of data copy, it simply outputs the input data as it is, so that the input data is output as it is.

Next, in order to specify a write address,
The processor 1 sends a write address designation command. This specifies an address in the same way as a normal write command, but since it is not necessary to specify write data, the command is similar to a read command.

This write command instructs data writing to the memory element 7, but the data to be written is not sent from the processor 1 but uses the output of the arithmetic unit 6. That is, the instruction decoder 53 that has received this command sends the decoded instruction to the control circuit 54, and the control circuit 54 instructs the memory element control circuit 52 not to write data from the system bus 100 but to the arithmetic unit 6 will be used.

In this manner, data copy from a certain address to a certain address can be realized without actually sending data to the system bus 100 and without transferring data to the processor 1.

Next, a case where addition is performed between two addresses and the addition result is stored in a third address, that is, a case where there are two read addresses and one write address will be described.

In this case, since there are two read addresses, the data read from the memory element 7 is sent to the arithmetic unit 6 by the first read command from the processor 1 as in the case of data copy. However, since the operation cannot be performed without another data, it is temporarily stored in the arithmetic unit 6.

In response to the second read command issued next, the second data is similarly sent to the arithmetic unit 106, and is added to the temporarily stored first data. By the write command issued thereafter, the data of the arithmetic unit 6 is written to the address indicated by the write command of the memory element 7 as in the case of the data copy.

FIGS. 4 to 6 are flowcharts showing the processing operation of the control circuit in the memory control device of the memory system with an arithmetic function according to another embodiment of the present invention. These figures 4
The processing operation of the control circuit in the memory control device of the memory system with an arithmetic function according to another embodiment of the present invention will be described with reference to FIGS.

An information processing apparatus using a memory system with an arithmetic function according to another embodiment of the present invention is also shown in FIGS.
Has the same configuration as the information processing apparatus using the memory system with an arithmetic function according to one embodiment of the present invention shown in FIG. 1 and will be described below using the reference numerals of the respective circuits in FIGS. 4 to 6 are realized by the control circuit 54 executing a program in a control memory (not shown), and a ROM, an IC memory, or the like can be used as the control memory.

However, in an information processing apparatus using a memory system with an arithmetic function according to another embodiment of the present invention, the memory device 7 and the memory control device 5 are divided into a plurality of parts, and each of the plurality of memory control devices 5 Are connected to the same system bus 100. here,
Each of the plurality of memory controllers 5 has the same system bus 10
0 may not be connected, but in that case, each of the memory control devices 5

When a command on the system bus 100 is input (step S21 in FIG. 4), if the command reads data from the memory element 7 (step S22 in FIG. 4), the control circuit 54 controls the memory element control circuit 52. Then, the data read from the memory element 7 is transmitted to the system bus 100 via the system bus control circuit 51 (step S23 in FIG. 4).

The control circuit 54 is connected to the system bus 100
If the above command is a data write to the memory element 7 (step S24 in FIG. 4), the data received from the system bus 100 via the system bus control circuit 51 is transferred to the memory element 7 via the memory element control circuit 52. (Step S25 in FIG. 4).

Further, the control circuit 54 is connected to the system bus 10
If the command on 0 is a command indicating a process using the arithmetic device 6 (a command such as data copy or addition of an addition result between two addresses to a third address) (step S26 in FIG. 4), the memory element Data is read from the memory element 7 via the control circuit 52 (step S27 in FIG. 4).

Here, the control circuit 54 is connected to the system bus 10
A command on 0 reads data from another memory element (not shown) or writes data to another memory element, or performs an operation using only data from the memory element 7 under its own device Is determined (step S28 in FIG. 4).

The control circuit 54 is connected to the memory element 7 under its control.
In the case of performing the operation only with the data of (1), the transmission of the read data from the memory element 7 to the system bus 100 to the system bus control circuit 51 is suppressed (step S2 in FIG. 4).
9), instruct the arithmetic unit 6 to perform an arithmetic operation (step S3 in FIG. 5).
0).

Thereafter, if the control circuit 54 writes the operation result of the arithmetic unit 6 to the memory element 7 under its control (step S31 in FIG. 5), the control circuit 54 stores the arithmetic unit in the memory element 7 via the memory element control circuit 52. 6 is written (step S32 in FIG. 5).

Unless the control circuit 54 writes the operation result of the operation device 6 to the memory element 7 under its control,
That is, if the operation result of the arithmetic unit 6 is to be written into another memory element (step S31 in FIG. 5), an instruction to write data to another memory control unit is issued on the system bus 100 via the system bus control circuit 51. (Step S3 in FIG. 6)
8). The calculation result of the calculation device 6 is also sent to the system bus 100 following the instruction.

On the other hand, when the control circuit 54 does not perform the operation only with the data of the memory element 7 under its own device, it instructs the system bus 100 via the system bus control circuit 51 to read data to another memory control device. (Step S34 in FIG. 6).

When the control circuit 54 receives all data via another memory control device (step S35 in FIG. 6), it instructs the arithmetic device 6 to perform an operation (step S36 in FIG. 6). Thereafter, the control circuit 54 writes the calculation result of the calculation device 6 into the memory element 7 under its own device (step S5 in FIG. 6).
37), the memory element 7 via the memory element control circuit 52
The calculation result of the calculation device 6 is written into the memory (step S3 in FIG. 6).
9).

If the control circuit 54 does not write the operation result of the operation device 6 to the memory element 7 under its own device,
That is, if the operation result of the arithmetic unit 6 is to be written to another memory element (step S37 in FIG. 6), an instruction to write data to another memory control unit is issued on the system bus 100 via the system bus control circuit 51. (Step S3 in FIG. 6)
8). The above processing operation is repeatedly executed until all data is processed (steps S21 to S29 in FIG. 4, FIG.
Steps S30 to S33, FIG. 6 Steps S34 to S3
9).

That is, as long as the address of the data to be read is in the same memory control device 5 as the data address to be written, the processing operation is the same as that of the memory system with the arithmetic function according to the embodiment of the present invention. If it is in the controller, it is necessary to send the data to the memory controller where the data address to be written is located.

Therefore, the read command needs information indicating where the memory controller to which the data is to be written, and the memory controller that processes the read command looks at the information and sends it to the system without sending it to the internal arithmetic unit. It needs to be sent to the bus for transfer. The memory control device to be written must take in the transferred data and write the data to the memory element under its own device.

FIGS. 7 to 9 are flowcharts showing the processing operation of the control circuit in the memory control device of the memory system with an arithmetic function according to another embodiment of the present invention. These FIG.
The processing operation of the control circuit in the memory control device of the memory system with an arithmetic function according to another embodiment of the present invention will be described with reference to FIGS.

An information processing apparatus using a memory system with an arithmetic function according to another embodiment of the present invention is also shown in FIGS.
Has the same configuration as the information processing apparatus using the memory system with an arithmetic function according to one embodiment of the present invention shown in FIG. 1 and will be described below using the reference numerals of the respective circuits in FIGS. The processing operations shown in FIGS. 7 to 9 are realized by the control circuit 54 executing a program in a control memory (not shown), and a ROM, an IC memory, or the like can be used as the control memory.

However, in an information processing apparatus using a memory system with an arithmetic function according to another embodiment of the present invention, the memory element 7 and the memory controller 5 are divided into a plurality of parts, and each of the plurality of memory controllers 5 Are connected to the same system bus 100. here,
Each of the plurality of memory controllers 5 has the same system bus 10
Although it is possible that the connection is not made to 0, in such a case, it is necessary to devise a little in operation of each memory control device 5.

When a command on the system bus 100 is input (step S41 in FIG. 7), the control circuit 54 reads out data from the memory element 7 (step S42 in FIG. 7). Then, the data read from the memory element 7 is transmitted to the system bus 100 via the system bus control circuit 51 (step S43 in FIG. 7).

The control circuit 54 is connected to the system bus 100
If the above command is a data write to the memory element 7 (step S44 in FIG. 7), the data received from the system bus 100 via the system bus control circuit 51 is transferred to the memory element 7 via the memory element control circuit 52. (Step S45 in FIG. 7).

Further, the control circuit 54 is connected to the system bus 10
If the command on 0 is a command indicating a process using the arithmetic unit 6 (a command such as data copy or addition of an addition result between two addresses to a third address) (step S46 in FIG. 7), the memory element Data is read from the memory element 7 via the control circuit 52 (step S47 in FIG. 7).

Here, the control circuit 54 is connected to the system bus 10
A command on 0 reads data from another memory element (not shown) or writes data to another memory element, or performs an operation using only data from the memory element 7 under its own device Is determined (step S48 in FIG. 7).

The control circuit 54 controls the memory element 7 under its own control.
In the case of performing the operation only with the data of (1), the transmission of the read data from the memory element 7 to the system bus 100 to the system bus control circuit 51 is suppressed (step S4 in FIG. 7).
9), instruct the arithmetic unit 6 to perform an arithmetic operation (step S5 in FIG. 8).
0).

Thereafter, if the control circuit 54 writes the operation result of the operation device 6 to the memory element 7 under its control (step S51 in FIG. 8), the control circuit 54 stores the operation result in the memory element 7 through the memory element control circuit 52. 6 is written (step S52 in FIG. 8).

If the control circuit 54 does not write the operation result of the operation device 6 to the memory element 7 under its control,
That is, if the operation result of the operation device 6 is to be written to another memory element (step S51 in FIG. 8), an instruction to write data to another memory control device on the system bus 100 via the system bus control circuit 51 is issued. (Step S5 in FIG. 9)
7). The calculation result of the calculation device 6 is also sent to the system bus 100 following the instruction.

On the other hand, when the control circuit 54 does not perform the operation only with the data of the memory element 7 under its own control, the control circuit 54 transmits the data sent from another memory control device onto the system bus 100 via the system bus control circuit 51. When receiving the data and receiving all the data via another memory control device (step S54 in FIG. 9), the arithmetic unit 6 is instructed to perform the calculation (step S55 in FIG. 9). Thereafter, if the control circuit 54 writes the operation result of the operation device 6 to the memory element 7 under its own device (step S56 in FIG. 9), the operation of the operation device 6 is applied to the memory element 7 via the memory element control circuit 52. The result is written (step S58 in FIG. 9).

Unless the control circuit 54 writes the calculation result of the calculation device 6 to the memory element 7 under its control,
That is, if the operation result of the arithmetic unit 6 is to be written to another memory element (step S56 in FIG. 9), an instruction to write data to another memory control unit is issued on the system bus 100 via the system bus control circuit 51. (Step S5 in FIG. 9)
7). The above processing operation is repeatedly executed until all data is processed (steps S41 to S49 in FIG. 7, FIG. 8
Steps S50 to S53, FIG. 9 Steps S54 to S5
8).

That is, if the address of the data to be read is in the same memory control unit 5 as the data address to be written, the processing operation is the same as that of the memory system with the arithmetic function according to the embodiment of the present invention, If it is in the controller, it is necessary to send the data to the memory controller where the data address to be written is located.

Therefore, the read command needs information indicating where the memory controller to which the data is to be written, and the memory controller that processes the read command looks at the information and sends the information to the system without sending it to the internal arithmetic unit. It needs to be sent to the bus for transfer. The memory control device to be written must take in the transferred data and write the data to the memory element under its own device.

As described above, since data processing can be performed without transferring all data in the memory element 7 to the processors 1 and 2, the load on the processors 1 and 2 and the system bus 100 can be reduced. Therefore, by assigning that processing capacity to other processing, it is possible to contribute to performance improvement.

Further, since the data transfer time with the processors 1 and 2 can be saved, especially the processors 1 and 2
In a device in which the transfer time between the memory element 7 and the memory element 7 is long, high-speed operation close to the limit performance of the memory element 7 is possible.

Moreover, in a multiprocessor system having cache memories 3 and 4 as in one embodiment of the present invention or another embodiment, in order to maintain the consistency of the cache memories 3 and 4, when writing a certain address, another It is necessary to take measures such as invalidating the processor cache.

However, the processing operation increases the load on other processors and increases the processing time. However, the memory system with an arithmetic function according to one embodiment of the present invention or another embodiment is used. Since data is written without storing data in the cache memories 3 and 4, high-speed writing can be performed without imposing a load on other processors.

In a system having only small-capacity cache memories 3 and 4, if a simple instruction is applied to a large amount of data, in a conventional system, all data is brought to the processors 2 and 3. Old data required for the subsequent processing is pushed out by a large amount of data, and it is necessary to read the data to the memory element 7 again.

For this reason, access to the memory element 7 causes performance degradation. According to the memory system with an arithmetic function according to one embodiment of the present invention or another embodiment, since a large amount of data can be processed in the memory control device 5, necessary data in the cache memories 3 and 4 can be processed. However, it is possible to reduce the possibility of deteriorating performance.

Further, when performing direct data transfer (DMA) with the input / output device 9, the DMA process cannot be started unless all the data of the corresponding address remaining in the cache memories 3 and 4 is discharged. However, in the memory system with an arithmetic function according to one embodiment of the present invention or another embodiment, since the data in the memory element 7 can be rewritten immediately, the flushing process of the cache memories 3 and 4 becomes unnecessary, and Data transfer can be started.

In the memory system with an arithmetic function according to one embodiment or another embodiment of the present invention, a method of dividing the memory element into a plurality of elements and expanding the transfer amount of normal memory access may be considered. This system, which is generally called interleaving, can be realized with almost no difference from the embodiment of the present invention if there is one memory control device.

In each of the above embodiments, the operation speed of the arithmetic unit is higher than that of the memory device, so that only one arithmetic unit performs the arithmetic function. However, if an interleave technique or a higher-speed memory device is used, one arithmetic unit is used. There is a possibility that data more than the processing capacity of the arithmetic device can be supplied. In such a case, the processing capacity can be increased by forming the arithmetic unit into a pipeline, or can be dealt with by providing a plurality of arithmetic units.

In each of the above embodiments, reading and writing are instructed by separate commands in order to match consistency with the conventional memory operation instruction as much as possible. However, pointers, indexes, relative addresses and the like are used. Thus, it is also possible to instruct all addresses and operations with one command.

Further, by providing a sequential circuit in the control circuit, a change may be made so as to designate a more complicated process including a conditional branch. Furthermore, in each of the above embodiments, only one and two pieces of data are designated as input data. However, by inputting more data, it is possible to perform a change so that a complicated operation is executed at a time. Is also possible.

On the other hand, in each of the above embodiments, the output of the arithmetic unit is not output to the processor via the system bus, but the processor may want to know the operation result immediately. For such a case, a configuration in which the calculation result is stored in the memory and output to the system bus is also considered.

In addition, various methods can be devised to deal with exceptions (overflow, carry, borrow, etc.) in the arithmetic unit in the memory control device. In addition to a method of defining a fixed value when an exception occurs, a method of notifying the processor of the fact using an interrupt or a dedicated line and leaving the subsequent processing to the processor can be considered.

[0087]

As described above, according to the present invention, in a memory system having an arithmetic function comprising a main memory and a memory control device for controlling access to the main memory, a memory system according to an instruction from a central processing unit is provided. By providing an arithmetic means for calculating data read from the main memory in the memory controller, it is possible to process a large amount of data in the main memory at high speed without deteriorating the performance of the processor. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus using a memory system with an arithmetic function according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of the memory control device of FIG. 1;

FIG. 3 is a flowchart illustrating a processing operation of the control circuit of FIG. 2;

FIG. 4 is a flowchart showing a processing operation of a control circuit in a memory control device of a memory system with an arithmetic function according to another embodiment of the present invention.

FIG. 5 is a flowchart showing a processing operation of a control circuit in a memory control device of a memory system with an arithmetic function according to another embodiment of the present invention.

FIG. 6 is a flowchart showing a processing operation of a control circuit in a memory control device of a memory system with an arithmetic function according to another embodiment of the present invention.

FIG. 7 is a flowchart showing a processing operation of a control circuit in a memory control device of a memory system with an arithmetic function according to another embodiment of the present invention.

FIG. 8 is a flowchart showing a processing operation of a control circuit in a memory control device of a memory system with an arithmetic function according to another embodiment of the present invention.

FIG. 9 is a flowchart showing a processing operation of a control circuit in a memory control device of a memory system with an arithmetic function according to another embodiment of the present invention.

[Explanation of symbols]

 1, 2 processor 3, 4 cache memory 5 memory control device 6 arithmetic device 7 memory element 8 input / output control device 9 input / output device 51 system bus control circuit 52 memory element control circuit 53 instruction decoder 54 control circuit

Claims (21)

[Claims] 1. A memory system having an arithmetic function comprising a main memory and a memory control device for controlling access to the main memory, wherein a memory read from the main memory in response to an instruction from a central processing unit. A memory system with an arithmetic function, comprising an arithmetic means for performing an arithmetic operation in the memory control device. 2. The data processing apparatus according to claim 1, wherein said calculating means calculates a data copy instruction for copying data at a first address of said main memory to a second address and data at third and fourth addresses of said main memory. 2. The memory system with an arithmetic function according to claim 1, wherein arithmetic operation of a relatively simple instruction including at least an instruction to be written to the address of 5 is performed. 3. The memory control device according to claim 1, wherein when performing an arithmetic operation on the data read from the main storage using the arithmetic unit, the memory control device suppresses transmission of the data read from the main storage to the central processing unit. The memory system with an arithmetic function according to claim 1, wherein the memory system is configured. 4. A multiprocessor system in which a plurality of central processing units are connected on a common system bus,
A memory system with an arithmetic function, comprising: a main memory and a memory control device that connects the main memory to the system bus and controls access to the main memory, wherein the memory system is configured to respond to an instruction from the central processing unit. A memory system with an arithmetic function, comprising an arithmetic means for performing an arithmetic operation on data read from a main memory inside the memory control device. 5. The arithmetic means computes a data copy instruction for copying data at a first address of the main memory to a second address and data at third and fourth addresses of the main memory. 5. The memory system with an arithmetic function according to claim 4, wherein arithmetic operation of a relatively simple instruction including at least an instruction to be written to the address of 5 is performed. 6. The memory control device according to claim 1, wherein when performing an arithmetic operation on the data read from the main storage using the arithmetic unit, the memory control device suppresses transmission of the data read from the main storage to the central processing unit. The memory system with an arithmetic function according to claim 4, wherein the memory system is configured. 7. In a multiprocessor system in which a plurality of central processing units are connected to corresponding system buses, a plurality of main memories and the plurality of main memories are connected to corresponding system buses, respectively, and the plurality of main memories are connected. A memory system with an arithmetic function comprising a plurality of memory control devices for controlling access to each of the plurality of memory control devices, wherein the arithmetic means for performing an arithmetic operation on the data read from the main memory in accordance with an instruction from the central processing unit; A memory system with an arithmetic function, which is provided in each of a plurality of memory control devices. 8. The arithmetic means computes a data copy instruction for copying data at a first address of the main memory to a second address and data at third and fourth addresses of the main memory. 8. The memory system with an arithmetic function according to claim 7, wherein arithmetic operation of a relatively simple instruction including at least an instruction to be written to the address 5 is performed. 9. The memory control device, when performing an operation on the data read from the corresponding main storage by using the calculation means, suppresses transmission of the data read from the main storage to the central processing unit. 9. The memory system with an arithmetic function according to claim 7, wherein the memory system is configured as described above. 10. A memory control method for a memory system with an arithmetic function comprising a main memory and a memory control device for controlling access to said main memory, wherein said memory control method comprises the steps of: A memory control method, comprising the step of performing an operation on read data in the memory control device. 11. The step of performing an operation on the data,
At least a data copy instruction for copying data at a first address of the main memory to a second address and an instruction for calculating data at third and fourth addresses of the main memory and writing the data to a fifth address are included. 11. The memory control method according to claim 10, wherein a relatively simple operation of an instruction is performed. 12. The memory control device according to claim 1, wherein when performing an operation on the data read from the main storage, the memory control device includes a step of suppressing transmission of the data read from the main storage to the central processing unit. The memory control method according to claim 10. 13. In a multiprocessor system in which a plurality of central processing units are connected on a common system bus, a memory control for connecting a main memory and the main memory to the system bus and controlling access to the main memory. A memory control method for a memory system with an arithmetic function comprising a device, wherein the memory control device includes a step of performing an arithmetic operation on data read from the main storage in accordance with an instruction from the central processing unit. Memory control method. 14. The method according to claim 1, wherein the step of calculating the data includes: a data copy instruction for copying data at a first address of the main storage to a second address; and third and fourth data of the main storage.
14. The memory control method according to claim 13, wherein a relatively simple instruction including at least an instruction for calculating data at the address and writing the data to the fifth address is calculated. 15. The memory control device according to claim 11, wherein when performing an operation on the data read from the main storage, the memory control device includes a step of suppressing transmission of the data read from the main storage to the central processing unit. The memory control method according to claim 13 or claim 14. 16. In a multiprocessor system in which a plurality of central processing units are connected to corresponding system buses, a plurality of main memories and the plurality of main memories are connected to corresponding system buses, respectively, and the plurality of main memories are connected. A memory control method for a memory system with an arithmetic function comprising a plurality of memory control devices for controlling access to each of the plurality of memory control devices, wherein an arithmetic operation is performed on data read from the main memory in accordance with an instruction from the central processing unit. A memory control method, comprising the steps of having a plurality of steps in each of the plurality of memory control devices. 17. The method according to claim 17, wherein the step of calculating the data includes: a data copy instruction for copying data at a first address of the main storage to a second address; and a third and fourth data of the main storage.
17. The memory control method according to claim 16, wherein a relatively simple instruction including at least an instruction for calculating data at the address and writing the data to the fifth address is calculated. 18. When each of the plurality of memory controllers performs an operation on data read from a corresponding main memory, the step of suppressing transmission of the data read from the main memory to the central processing unit is included. 18. The memory control method according to claim 16, wherein: 19. A memory control program for causing the memory control device to control access to the main storage in a memory system with an arithmetic function comprising a main storage and a memory control device for controlling access to the main storage. Recording medium, wherein the memory control program causes the memory control device to perform an operation on data read from the main storage in accordance with an instruction from a central processing unit. Recording medium. 20. In a multiprocessor system in which a plurality of central processing units are connected on a common system bus, a memory control for connecting a main memory and the main memory to the system bus and controlling access to the main memory. A storage medium having a memory control program for causing the memory control device to control access to the main storage in a memory system with an arithmetic function including a device, wherein the memory control program stores the memory control device in the memory control device. A recording medium having recorded thereon a memory control program for performing an operation on data read from the main storage according to an instruction from a central processing unit. 21. In a multiprocessor system in which a plurality of central processing units are respectively connected to corresponding system buses, a plurality of main memories and the plurality of main memories are connected to respective corresponding system buses, and the plurality of main memories are connected. A recording medium recording a memory control program for causing the memory control device to control access to the main storage in a memory system with an arithmetic function including a plurality of memory control devices that control access to each of the memory control devices, A storage medium storing a memory control program, wherein the memory control program causes each of the plurality of memory control devices to perform an operation on data read from the main storage in accordance with an instruction from the central processing unit.