JP2000231797A - Method for improving reliability of non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable screening effectively a data holding characteristic and to enable coping with deterioration in the case of deterioration of a characteristic during use. SOLUTION: In this method, threshold voltage of a memory cell is gradually varied by applying a write-in pulse at the time of write-in of data before baking, and threshold voltage of a memory cell is discriminated whenever a write-in pulse is applied. Then, when this threshold voltage is the upper limit value or more, after threshold voltage is dropped by applying an erasing pulse, a write-in pulse is applied again. By repeating this operation, threshold voltage of a memory cell is converged in a range between the upper limit value and the lower limit value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor nonvolatile memory, and more particularly to a method of improving the reliability of a floating gate type semiconductor nonvolatile memory.

[0002]

2. Description of the Related Art In recent years, a floating gate type semiconductor non-volatile memory (hereinafter referred to as a non-volatile memory) is generally used as an electrically rewritable semiconductor non-volatile memory. The storage principle is that the threshold voltage of a memory cell changes depending on whether electrons are stored in a floating gate (hereinafter, referred to as FG). Therefore, when such a non-volatile memory is left as it is, electrons may be emitted from the FG for some reason, and when the emission of electrons occurs, data changes. .

[0003] Therefore, in the case of a non-volatile memory, in order to guarantee the data retention characteristics, a device including a memory cell which is subjected to baking at a high temperature in a manufacturing inspection process to allow electrons stored in the FG to escape easily. Has been screened to judge that is defective. Hereinafter, the procedure of the screening will be described with reference to FIGS.

That is, in the screening at this time, as shown in FIG. 11, data “0” is written to all memory cells of a device which is a nonvolatile memory (this is a state where electrons are stored in the FG). ),
The method comprises the steps of determining the threshold voltage VT of a memory cell based on a determination reference value VT0 after performing baking under a high temperature for a certain period of time. As shown in FIG. 12, the threshold voltage VT of the cell is distributed with a width due to the variation in the write characteristics. On the other hand, the threshold voltage VT of the memory cell after baking is distributed in a state as shown in FIG. 13, and includes the memory cell having the threshold voltage VT equal to or lower than the criterion value VT0. However, such a device will be screened as a failure for which data retention characteristics cannot be guaranteed.

[0005]

The defect determination made by the conventional schooling is not based on how much the threshold voltage VT of the memory cell has changed by baking, but on the memory cell after baking.
Since the determination is made based on whether or not the threshold voltage VT of the cell is equal to or lower than the determination reference value VT0, the following inconvenience has occurred.

That is, as shown in FIG. 13, even if there is a memory cell whose threshold voltage VT before and after baking greatly changes, if the threshold voltage VT is higher than the criterion value VT0, it is determined to be defective. The device is shipped to the market as a non-defective product, but it is considered that such a device has an inconvenience in the charge retention characteristics of the FG, and thus the data changes when left for a long time. There is a possibility that this may be a serious problem in securing the reliability of the nonvolatile memory.

Further, in a nonvolatile memory, data retention characteristics and rewriting durability are important for ensuring its reliability. However, repeated data rewriting degrades the data retention characteristics and causes a problem in writing / writing. It is known that the erasing characteristics themselves deteriorate. Therefore, even if a device with an initial failure can be screened in the manufacturing inspection process, the device whose characteristics are deteriorated during use cannot be recognized, and the failure may occur. Had become.

The present invention has been made in view of these inconveniences, and it is possible to effectively screen data retention characteristics, and to further recognize characteristic deterioration during use. It is an object of the present invention to provide a method for improving the reliability of a nonvolatile memory which can be dealt with.

[0009]

According to a first aspect of the present invention, there is provided a method for improving the reliability of a semiconductor non-volatile memory, wherein a write pulse is applied at the time of writing data before baking to reduce the threshold voltage of a memory cell. Each time a write pulse is applied, the threshold voltage (VT) of the memory cell is determined. When the threshold voltage (VT) is equal to or higher than the upper limit value (VTmax), the erase pulse is generated. After applying the voltage to lower the threshold voltage (VT), the operation of applying the write pulse again is repeated, and then the threshold voltage (VT) of the memory cell is increased to the upper limit value (VTmax) and the lower limit value (VTmin). ).

According to a second aspect of the present invention, there is provided a method for improving the reliability of a semiconductor non-volatile memory, which is performed subsequently to the first aspect of the present invention, wherein a threshold voltage (VT) of a memory cell is determined. To the upper limit (VTmax) and the lower limit (VT
b) after converging within the range of
Threshold voltage (VT) of baked memory cell
Is the maximum value (VTm) in consideration of the guarantee of the data retention characteristics.
ax ′) and the minimum value (VTmin ′).

According to a third aspect of the present invention, there is provided a method for improving the reliability of a semiconductor non-volatile memory, wherein a threshold voltage (VT) after data writing before baking matches a device upper limit value (VTmax0) which matches a device-specific writing characteristic. ) And the threshold voltage (VT) of the memory cell in which data converging within the range between the device lower limit (VTmin0) is written.
Is measured, and the device upper limit value (V) of the threshold voltage (VT) is measured.
Tmax0) is grasped and stored in another memory area, and after the data written in the memory cell is erased, a write pulse is applied to gradually change the threshold voltage (VT) of the memory cell. Each time a write pulse is applied, the threshold voltage (VT) of the memory cell is determined, and this threshold voltage (VT) is set to the device upper limit (V
If the threshold voltage (VT) is equal to or higher than Tmax0), the threshold voltage (VT) is reduced by applying an erase pulse, and then the operation of applying a write pulse again is repeated. It is characterized by converging within a range between a device upper limit value (VTmax0) and a device lower limit value (VTmin0).

According to a fourth aspect of the present invention, there is provided a method for improving the reliability of a semiconductor non-volatile memory, which is performed subsequently to the third aspect of the present invention, wherein a threshold voltage (VT) of a memory cell is determined. Is converged within the range between the device upper limit value (VTmax0) and the device lower limit value (VTmin0) and baked, and the threshold voltage (VT) of the baked memory cell is reduced to the device upper limit value (VTmax).
0) and the lower limit value (VTmin0) and the maximum value (VTmax ') and the minimum value (VTmin') corresponding to the device lower limit value (VTmin0).

According to a method for improving the reliability of a semiconductor nonvolatile memory according to a fifth aspect of the present invention, a device upper limit value (VTmax0) that matches a device-specific write characteristic is stored as it is after a manufacturing inspection, and the device upper limit value (VTmax0) is stored during use. The threshold voltage (VT) of the memory cell is measured to determine the device upper limit (VTm).
ax0), when the threshold voltage (VT) of the memory cell in use is lower than the device upper limit (VTmax0), a redundant memory cell array having an extra memory cell in use The feature is that redundancy replacement is performed by replacing the memory cell inside.

In the present invention, since the threshold voltage of the memory cell before baking is converged within a certain range, a device including a memory cell whose threshold voltage changes by baking. Can be screened as defective. Further, the range of the width in which the threshold voltage of the memory cell before baking converges is not common to all the memory cells manufactured under the same manufacturing conditions, but the memory cells included in individual devices are not used. Since the individual device upper limit value that matches the cell characteristics is set, it is possible to know the holding state of the charge accumulated in the FG by comparing the threshold voltage of the memory cell with the device upper limit value. The advantage that it becomes.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is an explanatory diagram showing a distribution state of a threshold voltage before baking of a memory cell included in a device which is a nonvolatile memory according to Embodiment 1, and FIG. 5 is a flowchart illustrating a procedure for converging a threshold voltage after a previous write operation within a range between an upper limit value and a lower limit value. The method for improving the reliability of the nonvolatile memory according to the present embodiment is a method of improving the reliability before baking. When writing data “0”, the threshold voltage V
An upper limit value VTmax and a lower limit value VTmin of T are determined, and the threshold voltage VT after writing is set to the upper limit value VTmax.
And a lower limit value VTmin.

That is, in the reliability improving method according to the present embodiment, as shown in FIG. 2, when writing data “0” to all the memory cells of a device which is a nonvolatile memory, a short write time is required. While applying a pulse, the threshold voltage VT of the memory cell is gradually changed. Each time a write pulse is applied, the threshold voltage VT of the memory cell is determined. If the threshold voltage VT is equal to or higher than the upper limit value VTmax, an erase pulse is applied to apply a threshold voltage to the memory cell. After lowering the voltage VT, the application of the write pulse again is executed.
It is needless to say that the application time of the write pulse or the erase pulse at this time is set according to the write characteristic and the erase characteristic of the memory cell.

If the threshold voltage VT when the write pulse is applied is equal to or lower than the upper limit VTmax, it is further determined whether the threshold voltage VT is equal to or higher than the lower limit VTmin. After confirming that it is equal to or higher than VTmin, shifting to the next address is executed. By repeating such operations, the memory
The threshold voltage VT of the cell has an upper limit value VTmax and a lower limit value V
It converges within the range of Tmin, and as a result, a device including a memory cell that cannot be screened by the conventional method, that is, a memory cell in which data may change if left for a long time. It is possible to screen up to

(Embodiment 2) FIG. 3 is an explanatory diagram showing a distribution state of threshold voltages after baking of a memory cell included in a device which is a nonvolatile memory according to Embodiment 2, and FIG. 4 is baking. 12 is a flowchart illustrating a procedure for determining a threshold voltage later, and a method for improving the reliability of the nonvolatile memory at this time will be adopted subsequently to the method described in the first embodiment.

That is, in the reliability improving method according to the second embodiment, a single determination reference value VT0
Instead of determining the threshold voltage VT of the memory cell, two reference values, that is, a maximum value VTmax ′ and a minimum value VTmi in consideration of the guarantee of the data retention characteristics are considered.
The determination of the threshold voltage VT of the memory cell is performed using n '. Here, a value that can guarantee the data retention characteristic of the nonvolatile memory is set as a difference between the maximum value VTmax ′ and the minimum value VTmin ′ after baking and the upper limit value VTmax and lower limit value VTmin before baking. The set value at this time naturally depends on the manufacturing conditions.

In the present embodiment, as shown in FIG. 4, a device which is a nonvolatile memory in which the threshold voltage VT of a memory cell is converged within a range between an upper limit value VTmax and a lower limit value VTmin is changed to a high temperature. Under the baked condition, the threshold voltage VT of the baked memory cell is increased to a maximum value VT.
A determination is made as to whether it is greater than or equal to max 'or less. When the threshold voltage VT of the memory cell is equal to or higher than the maximum value VTmax ', it is determined that the memory cell is defective, while the threshold voltage VT of the memory cell is equal to the maximum value VTmax'.
If it is less than x ', it is subsequently determined whether it is more than or less than the minimum value VTmin'.

Further, the threshold voltage VT of the memory cell determined according to the above procedure is the minimum value VTmi.
If it is not more than n ', it is determined to be defective, while if it is not less than the minimum value VTmin', it is determined that the device is a non-defective device and shifting to the next address is executed. That is, in the second embodiment, the threshold voltage VT of the memory cell before baking is converged within a certain range, that is, within the range between the upper limit value VTmax and the lower limit value VTmin. Cell threshold voltage V
Even if T is changed by baking, screening can be performed, and devices that cannot be screened by the conventional method can be screened.

(Embodiment 3) FIG. 5 shows the threshold voltage when data "0" before baking is written in a memory cell included in a device which is a nonvolatile memory according to Embodiment 3. It is an explanatory view showing a distribution state,
FIG. 5 shows two samples a and b having different data write characteristics. Here, sample a shown in FIG. 5 is a device having better data write characteristics than sample b, and the threshold voltage VT of the memory cell after data write in sample a is high. In other words, the higher the threshold voltage VT of the memory cell after data writing, the more electrons are accumulated in the FG and the easier it is for the electric field to escape electrons. At the time of screening, the threshold voltage VT of a memory cell in which data “0” is written before baking is set to a device upper limit value VTm that matches a device-specific write characteristic.
It is effective to set it to ax0.

FIG. 6 is a flowchart showing a procedure for converging a threshold voltage after writing before baking to a range between a device upper limit value and a device lower limit value. FIG. FIG. 8 is a plan view schematically illustrating a device which is a nonvolatile memory provided with another memory area for storing a device upper limit value. In FIG. 7, reference numeral 1 in FIG. 7 denotes a nonvolatile memory, and 2 denotes a memory area. That is, in the third embodiment, as in the first embodiment, the upper limit value VTmax and the lower limit value VTmin of the threshold voltage VT of the memory cell are common to all memory cells manufactured under the same manufacturing conditions. VTmax0 that matches the write characteristics unique to each device
And setting the device lower limit value VTmin0 individually.

Therefore, in the reliability improving method according to the present embodiment, as shown in FIG. 6, the threshold voltage VT after data writing before baking is equal to the device upper limit value VTmax0 that matches the device-specific writing characteristics. Data "0" is written to the memory cell so as to converge within the range of the device lower limit value VTmin0, and the threshold voltage VT of the memory cell to which the data "0" is written is written. After measuring the device upper limit value VTmax0 of the threshold voltage VT, the device upper limit value VTmax0 is written to another memory area 2 provided in a part of the nonvolatile memory 1 and then written. Do something to memorize.

Next, after erasing the data "0" written in the memory cell, a short-time write pulse is applied to gradually change the threshold voltage VT of the memory cell. Is read from another memory area 2 in the non-volatile memory 1 every time the threshold voltage V is applied to the memory cell.
T, and the threshold voltage VT is set to the device upper limit V
When Tmax is equal to or greater than 0, an erase pulse is applied to lower the threshold voltage VT of the memory cell, and then a write pulse is applied again. It is needless to say that the application time of the write pulse or the erase pulse at this time is set so as to match the write characteristics and the erase characteristics of the memory cell.

If the threshold voltage VT at the time when the write pulse is applied is lower than the device upper limit VTmax0, it is further determined whether the threshold voltage VT is higher than or lower than the device lower limit VTmin0. When it is confirmed that the value is equal to or more than the device lower limit value VTmin0, the process moves to the next address. When such an operation is repeated, the threshold voltage V
T is the device upper limit value VTmax0 and the device lower limit value VT
It converges within the range of min0, and a device in which the threshold voltage VT of the memory cell may change due to baking has been screened.

(Embodiment 4) FIG. 8 is an explanatory diagram showing a distribution state of a threshold voltage after baking of a memory cell included in a device which is a nonvolatile memory according to Embodiment 4, and FIG. 9 is baking. FIG. 14 is a flowchart showing a procedure for determining a threshold voltage later, according to the fourth embodiment.
Is adopted subsequently to the reliability improving method described in the third embodiment. In the method according to the fourth embodiment, the threshold voltage VT of the memory cell is not determined based on the single determination reference value VT0, but the maximum value corresponding to the device upper limit value VTmax0 and the device lower limit value VTmin0 is determined. Determination of the threshold voltage VT of the memory cell is performed using the value VTmax0 'and the minimum value VTmin0'.

In the reliability improving method according to the present embodiment,
As shown in FIG. 9, the threshold voltage VT of the memory cell is equal to the device upper limit VTmax0 and the device lower limit VTmi.
The device converged to the range of n0 is baked at a high temperature, the device upper limit value VTmax0 is read from another memory area 2 in the nonvolatile memory 1, and the threshold voltage of the baked memory cell is read. It is determined whether VT is equal to or greater than the maximum value VTmax0 '. When the threshold voltage VT of the memory cell is equal to or higher than the maximum value VTmax0 ', it is determined that the memory cell is defective. When the threshold voltage VT of the memory cell is equal to or lower than the maximum value VTmax0', the operation is continued. To the next address. Therefore, according to the reliability improvement method according to the present embodiment, the memory capacity before baking is reduced.
The threshold voltage VT of the cell can be individually set in accordance with the write characteristics unique to the device, and the reliability of the device as the nonvolatile memory can be improved.

(Embodiment 5) FIG. 10 is a plan view schematically showing a device which is a nonvolatile memory provided with an extra redundant memory cell array. Reference numeral 1 in FIG. 10 denotes a nonvolatile memory. Reference numeral 2 denotes another memory area, and reference numeral 3 denotes a redundant memory cell array. That is, in a nonvolatile memory, data retention characteristics and rewriting durability are important for ensuring reliability. However, when data is repeatedly rewritten, the data retention characteristics are degraded, and the write / erase characteristics themselves are deteriorated. It will deteriorate.

Therefore, in the reliability improving method according to the present embodiment, the device upper limit value VTmax0 of the memory cell that matches the device-specific write characteristics is stored in another memory area 2 as it is even after the production inspection. The threshold voltage VT of the memory cell during actual use is measured, and the measured threshold voltage VT of the memory cell is compared with the device upper limit value VTmax0 immediately after manufacturing. That is, according to such a comparison, the memory
This makes it possible to know the holding state of the charge accumulated in the FG of the cell.

When the threshold voltage VT of the memory cell in use is lower than the device upper limit value VTmax0, the data retention characteristic or the write / erase characteristic has deteriorated. Therefore, the redundancy repair is performed by replacing the used memory cells whose threshold voltage VT is lower than the device upper limit value VTmax0 with the memory cells in the redundant memory cell array 3 provided extra. Is performed. Therefore,
By adopting the reliability improving method according to the present embodiment, an advantage that a device failure due to deterioration of characteristics of a memory cell during use can be prevented can be prevented.

[0033]

As described above, when the method for improving the reliability of a nonvolatile memory according to the present invention is employed, a device including a memory cell whose threshold voltage changes by baking is effectively regarded as defective. Screening can be performed at a high speed, and the effect of significantly improving the reliability of the nonvolatile memory can be obtained. In addition, it is possible to know the holding state of the charge accumulated in the FG of the memory cell included in each device, and it is possible to check that the data holding characteristic and the writing / erasing characteristic of the memory cell in use have deteriorated. The memory cells in a redundant memory cell array
There is also obtained an effect that the reliability of the nonvolatile memory can be further improved by replacing the cells.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a distribution state of a threshold voltage before baking of a memory cell included in a device which is a nonvolatile memory according to a first embodiment;

FIG. 2 is a flowchart illustrating a procedure for converging a threshold voltage after writing before baking to a range between an upper limit value and a lower limit value.

FIG. 3 is an explanatory diagram showing a distribution state of a threshold voltage after baking of a memory cell included in a device which is a nonvolatile memory according to a second embodiment;

FIG. 4 is a flowchart showing a procedure for determining a threshold voltage after baking.

FIG. 5 is an explanatory diagram showing a distribution state of a threshold voltage when data “0” before baking is written in a memory cell included in a device which is a nonvolatile memory according to a third embodiment; .

FIG. 6 is a flowchart showing a procedure for converging a threshold voltage after writing before baking to a range between a device upper limit value and a device lower limit value.

FIG. 7 is a plan view schematically showing a device in which another memory area for storing a device upper limit value of a threshold voltage of a memory cell is a nonvolatile memory.

FIG. 8 is an explanatory diagram showing a distribution state of a threshold voltage after baking of a memory cell included in a device which is a nonvolatile memory according to a fourth embodiment.

FIG. 9 is a flowchart showing a procedure for determining a threshold voltage after baking.

FIG. 10 is a plan view schematically showing a device which is a nonvolatile memory provided with an extra redundant memory cell array.

FIG. 11 is a flowchart showing a screening procedure according to a conventional mode.

FIG. 12 is an explanatory diagram showing a distribution state of threshold voltages when data “0” before baking is written into a memory cell.

FIG. 13 is an explanatory diagram showing a distribution state of threshold voltages after baking of a memory cell.

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Claims (5)

[Claims] At the time of writing data before baking, a write pulse is applied to gradually change the threshold voltage of a memory cell, and each time a write pulse is applied, the threshold voltage of the memory cell is determined. If the threshold voltage is equal to or higher than the upper limit, the operation of applying an erase pulse to lower the threshold voltage, and then applying a write pulse again is repeated, and then the threshold voltage of the memory cell is reduced. A method for improving the reliability of a semiconductor non-volatile memory, comprising converging a voltage within a range between an upper limit value and a lower limit value. 2. The method according to claim 1, wherein the memory cell is baked after converging the threshold voltage of the memory cell within an upper limit value and a lower limit value, and guarantees the threshold voltage of the baked memory cell in data retention characteristics. Wherein the determination is made based on a maximum value and a minimum value that take into account the above. 3. A threshold value of a memory cell in which data in which a threshold voltage after writing data before baking converges within a range between a device upper limit value and a device lower limit value that match write characteristics unique to the device is written. After measuring the value voltage, grasping the device upper limit value of the threshold voltage, storing it in another memory area, erasing the data written to the memory cell, applying a write pulse to the memory cell
The threshold voltage of the cell is gradually changed, and the threshold voltage of the memory cell is determined each time a write pulse is applied. When the threshold voltage is equal to or higher than the device upper limit, an erase pulse is generated. After applying and lowering the threshold voltage, the operation of applying the write pulse again is repeated, and then the threshold voltage of the memory cell is converged within the range between the device upper limit value and the device lower limit value. A method for improving the reliability of a semiconductor nonvolatile memory. 4. The method according to claim 1, wherein the threshold voltage of the memory cell is converged within a range between a device upper limit value and a device lower limit value, and baking is performed, and the threshold voltage of the baked memory cell is set to the device upper limit value. A method for improving the reliability of a semiconductor non-volatile memory, wherein the determination is made based on a maximum value and a minimum value corresponding to a device lower limit value. 5. A device upper limit value that matches a device-specific writing characteristic is stored as it is even after a manufacturing inspection.
Measure the threshold voltage of the memory cell in use and compare it with the device upper limit.If the threshold voltage of the memory cell in use falls below the device upper limit, the memory cell in use is A method for improving the reliability of a semiconductor non-volatile memory, wherein redundancy replacement is performed by replacing a memory cell in an extra redundancy memory cell array.