JP2000231539A - Data transfer system and data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate control by reducing a circuit scale necessary to data transfer and also eliminating monitoring of a bus state and bus arbitration. SOLUTION: In this data transfer system which performs data transfer between plural functional devices 1 to 5 connected to an I2C bus 6 being a common bus, when a device having a need to generate a data transfer cycle between the devices 1 to 5, e.g. the device (slave) 3, transmits a signal (interrupt signal) of a data transfer request to a device (master) 1 being the opposite party performing data transfer, the device 1 receives the signal and starts a data transfer cycle so that the data transfer cycle can be performed between the devices 3 and 1. Since the monitoring of a bus state and bus arbitration consequently becomes unnecessary, not only control of data transfer is facilitate but also malfunctions are much reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system and a data transfer method in a data processing system with data transfer and various equipment systems, and more particularly to a multi-master bus system.

[0002]

2. Description of the Related Art In a data processing system or an equipment system that involves data transfer, such as a personal computer or a multimedia system that handles images and sounds, I ² C is used to connect various functional devices and boards mounted with the functional devices.
A well-known general-purpose bus such as a bus or a PCI bus is being used.

[0003] This is because, when each device is provided with the minimum necessary functions and these devices can be connected to a common bus, the versatility of the system is enhanced, so that the basic system can be constructed at low cost and easily. This is because if a board or the like that executes necessary processing is connected to the basic system according to the application, the target system can be easily constructed.

Among general-purpose buses, for example, an I ² C bus is
A kind of serial bus, which is used in a system that performs relatively low-speed data transfer. This is a serial bus proposed by Philips, and performs data transfer by two signals of a bidirectional clock line and a bidirectional data line. The PCI bus is often used in personal computers, and is used in systems that require relatively high-speed data transfer of not only mathematical data but also images and audio data.

Conventionally, a method or system for efficiently transferring data using the I ² C bus has been disclosed in, for example, JP-A-8-83243 and JP-A-8-84154. It is widely known. Here, as an example of the system, FIG.
A system configured as shown in FIG.

[0006] Devices The system includes a bi-directional clock line (SCL) 7, the provided I ² C bus 6 composed of two signal of two-way data line (SDA) 8, to the I ² C bus 6 It is configured by connecting five devices 101 to 105.

This system comprises devices 101 and 10 having both a function as a master and a function as a slave.
3 and 104 and devices 102 and 105 having only a slave function are connected, and a multi-master bus system in which a plurality of devices functioning as masters (hereinafter, referred to as “master devices”) are connected. In addition,
A plurality of devices functioning as slaves (hereinafter referred to as “slave devices”) are also connected.

[0008] Here, the master device refers to a device having a capability of designating a destination device for data transfer by an address and initiating the data transfer by itself. The slave device refers to a device having a function of performing data transfer based on an activation signal from the master device only when selected by the master device.

FIG. 7 shows a circuit of a connection portion between the I ² C bus interface of each device and the clock line 7 and the data line 8 of the I ² C bus 6. However, in the illustrated example, only the circuits 101a and 103a of the connection portion of the two devices 101 and 103 are shown.

As shown in FIG. 7, the clock line 7 and the data line 8 of the I ² C bus 6 are connected to a power supply terminal 40 (power supply voltage Vc) via pull-up resistors 30 and 31, respectively.
Since it is connected to (c) and pulled up, during the period when data is not transferred to the I ² C bus 6, the high level “H” is set.
(Equivalent to the power supply voltage Vcc).

Circuits 101a and 103a at the connection between the interfaces of the devices 101 and 103 and the I ² C bus 6
Have the same configuration. Circuit 101 of device 101
a has transistors 22 and 23, and the circuit 103a of the device 103 has transistors 24 and 25.

Each of the devices 101 and 103 is an I ² C bus 6
When signals are exchanged with the clock line 7 or the data line 8 of these circuits, these circuits 101a and 103a
Works as follows. That is, the transistor 22
To 25 are turned on when the clock line output SCL-OUT or the data line output SDA-OUT to the input terminals 22a to 25a is at a high level "H", respectively, and the clock line 7 or the data line 8
To a GND potential.

Each of the clock line outputs SCL
When -OUT or the data line output SDA-OUT is at a low level "L", it is turned off. At this time,
The clock line 7 or the data line 8 has the power supply voltage Vcc because it is pulled up.

The clock line 7 and the data line 8 are connected to input buffer circuits 26, 27 or 28, 29, respectively. These input buffer circuits 26 to 29 respectively transmit signals exchanged on the clock line 7 or the data line 8 to the SCL-I
The signal is input into the device as N (clock line input) or SDA-IN (data line input).

Next, the operation of the conventional multi-master bus system having the above configuration will be specifically described. FIG.
Means that the device 101 functions as a master device,
6 is a timing chart illustrating signals exchanged when a device 103 is designated as a slave device and 1-byte (8-bit) data is transferred. FIG.
² is a block diagram showing a circuit configuration of an I ² C bus interface portion of the device 101.

First, the main configuration of the block diagram shown in FIG. 9 will be described. The master / slave control block 40 is connected to the internal data bus 60 and controls a master function and a slave function.
1 and a bus arbitration circuit 42.

The clock control circuit 43 determines the transfer clock speed during the master function, and outputs the clock line output SCL-OUT to the clock line 7 through the transistor 22. The noise removal circuit 44 removes unnecessary signals included in the data line input SDA-IN input from the clock line 7 via the input buffer circuit 27 in the slave function.

The multiplexer 45 outputs a master clock from the clock control circuit 43 as a control clock when in the master function, and outputs a clock line input SCL-IN from which noise has been removed by the noise removing circuit 44 when in the slave function.

The shift register 46 stores main data such as a slave address. The output control circuit 47
This circuit outputs data from the shift register 46 to the data line 8 via the transistor 23 as a data line output SDA-OUT in accordance with the control clock.

The bus arbitration circuit 42 operates as follows. That is, when two or more master devices connected to the same I ² C bus 6 are about to start a bus cycle at the same time, the right to cause a bus cycle as a master device from the state of the clock line 7 or the data line 8 Determine if there is. When it is determined by the address comparator 48 that the self has been selected as the slave, the interrupt signal generation circuit 50 notifies the CPU 13 inside the device shown in FIG.
This is a circuit to notify by RQ.

In the block diagram described above, a description will be given on the assumption that the CPU 13 (see FIG. 6) provided inside the device 101 attempts to write data to the device 103 serving as a slave device. Hereinafter, the operation will be described with reference to these drawings.
Since the circuit configuration of the I ² C interface portion is common to the device 101, the common portion has the device 101
Description will be made using the same reference numerals as in FIG.

First, the CPU 13 outputs a signal for notifying the master / slave control block 40 connected thereto via the internal data bus 60 that data is to be written to the external device 103. Next, the CPU 13 specifies the address of the write destination device 103 (7-bit signal from A6 to A0).
And a write signal (read / write bit: RWB =
An “L”) 8-bit signal is transmitted to the internal data bus 6
0 and output to the shift register (SR) 46.

When the master control block 40 receives these signals through the internal data bus 60, first, the bus state detection circuit 41 causes the clock line input SCL-IN and the data line input SDL-IN shown in FIG.
It is checked whether or not the I ² C bus 6 is in use from the state of FIG.

As a result, when the I ² C bus is not in use, the master control block 40 sets the data line output SD
A-OUT is set to low level “L” to notify the device 103 of the start of data transfer through the I ² C bus 6. At this time, the I ² C bus 6 changes the data line 8 from the high level “H” to the low level “L” when the clock line 7 is at the high level “H”. 103 also notifies other devices.

Thereafter, the master / slave control block 40 periodically outputs a clock through the clock line 7 and outputs the slave address (A6 to A6) stored in the shift register 46 through the data line 8.
0) is output from the upper bit A6, one bit at a time, for a total of 7 bits. After that, a 1-bit signal (read / write bit: RWB) indicating the data transfer direction is output.
Since writing is performed in this case, as shown in FIG. 8, the signal of the eighth bit becomes low level “L”.

On the other hand, the device 103 for receiving data
Captures the above 8-bit signal (slave address and read / write bit) from the input buffer circuit 29 connected to the data line 8 and stores it in the shift register 46. Then, the comparator 48 stores the fetched slave address in advance in the slave address register (SA).
R) Compare with the slave address stored in 49,
The result is output to the master / slave control block 40.

At this time, if the comparison results match, that is, if the device 101 has selected itself as a slave device, the data line 8
Acknowledgment signal (ACKB) is output (set to low level), thereby notifying the device 101 that the device 103 has responded as a slave device.

Next, as shown in FIG.
The shift register 46 writes data (write data) to be written in the same manner as data specifying the slave device.
And outputs it to the data line 8 bit by bit.

Then, the device 103 selected as the slave device receives the signal output to the data line 8 bit by bit and stores it in the shift register 46. The device 103 executes 1
When data is received bit by bit, and data of 8 bits is received, an acknowledgment signal (AC
KB) at a low level "L". Next, the 8-bit write data stored in the shift register 46 is transferred to the CPU 1 inside the device via the internal data bus 60.
Output to 3.

On the other hand, when the data writing is completed, the device 101 raises the data line 8 from the low level "L" to the high level "H" while the clock line 7 is at the high level, thereby transferring the data. The end is notified to the device 103.

[0031]

However, the above-mentioned conventional multi-master bus transfer system has the following problems. That is, in the conventional circuit configuration, as shown in FIG. 9, the control block 4 in which both the master function and the slave function are mounted in the circuit of the interface portion.
Since it is necessary to provide 0, not only the circuit becomes large, but also the control thereof becomes complicated.

Further, since a plurality of master devices are allowed to be connected to the common bus, it is necessary to monitor whether a data transfer cycle is simultaneously activated by each master device. Moreover, as a countermeasure when it is found that they are running at the same time,
There is also a problem that a bus arbitration circuit for detecting a transfer cycle finally executed must be provided.

According to the I ² C bus standard, in such a case,
When the transfer system of the multi-master bus is constituted by the I ² C bus, the data transfer cycle is started from the master device which has output the high level “H” when the data line goes to the low level “L”. Although they were supposed to lose their qualifications, in reality, due to time constraints, some efforts were made to leave the highest priority data transfer cycle, and control was considerably complicated. .

The present invention has been made to solve such a problem. In the above-described data transfer system, the circuit scale can be reduced, and a plurality of devices can be master devices. It is also an object of the present invention to provide a multi-master bus system in which monitoring of a bus state by a master device and bus arbitration are omitted, and control is facilitated.

[0035]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a data transfer system and a data transfer method configured as follows.

The data transfer system according to the present invention is a data transfer system wherein a plurality of functional devices are connected to a common bus and data is transferred between the devices via the common bus. The device that needs to cause a data transfer cycle has means for transmitting a data transfer request signal to the device that performs the data transfer, and the device that performs the data transfer includes the data transfer request signal. It has means for receiving a transfer request signal, and means for activating a data transfer cycle upon receiving the signal.

According to this data transfer system, when data transfer is performed between a plurality of functional devices connected to a common bus, a device that needs to generate a data transfer cycle is transferred to a device that is a data transfer partner. When the request signal is transmitted, the data transfer cycle is started by the partner device, so that only one device having the ability to initiate the data transfer cycle is sufficient. Further, since the monitoring of the bus state and the bus arbitration become unnecessary, not only the circuit configuration required for data transfer and its control become easy, but also a malfunction is less likely to occur.

The means for transmitting the data transfer request signal may be a means for transmitting an interrupt signal, and the means for receiving the data transfer request signal may be a means for receiving the interrupt signal. Further, it is preferable that a device that needs to cause the transfer cycle be a slave device and a device that performs data transfer be a master device.

Further, the common bus is an I ² C bus,
Preferably, the master device has means for outputting a slave address, and the slave device specified by the slave address has means for transmitting a signal indicating a subsequent data transfer direction to the master device.

The data transfer method according to the present invention comprises:
In a data transfer method for performing data transfer between a plurality of functional devices connected to a common bus through the common bus, a device that needs to cause a data transfer cycle among the plurality of devices is a partner that performs data transfer. Sends a data transfer request signal to the device
The data transfer partner device receives the signal and starts a data transfer cycle.

[0041] Moreover, between at least one master device and a plurality of slave devices are connected to a common I ² C bus, a data transfer method for transferring data through the I ² C bus, in said plurality of slave devices so,
A slave device that needs to cause a data transfer cycle sends a data transfer request signal to a master device that performs data transfer, and the master device receives the signal and starts a data transfer cycle. Together with the slave address, and the slave device specified by the slave address can transmit a signal indicating the subsequent data transfer direction to the master device that is the data transfer partner.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of a data transfer system according to the present invention. In addition, in order to avoid repetition of description, the same reference numerals are given to portions common to the conventional configuration shown in FIG.

[0043] Shown in FIG. 1, the provided I ² C bus 6 consisting of two lines of bidirectional clock line 7 and bidirectional data line 8, the device 5 from the device 1 to the I ² C bus This is a multi-master bus system connecting up to five devices.

Here, the device 1 has only a master function for causing the four devices from the device 2 to the device 5 to perform data read / write access, and functions as a master device. It is configured to start a data transfer cycle in response to a transfer request signal. The I ² C bus 6 is a multi-master bus to which a plurality of master devices can be connected. In this embodiment, only the device 1 is the master device.

The devices 2 and 5 have only the slave function and respond only to the data transfer cycle started by the device 1, but do not start the data transfer cycle by themselves. Same as 102 and 105.

The device 3 and the device 4 are connected to the I ² C bus 6
Although the device has only a slave function as an interface function with the device, the device of the data transfer system according to the present embodiment is configured so that it can be activated as a request device that requests a transfer cycle for transferring data by itself. is there.

That is, when it is necessary for the device 3 and the device 4 to initiate data transfer, the device 3 and the device 4 output a signal for notifying the device 1 of the fact instead of causing the data transfer. For this purpose, interrupt signal (IRQ) generating circuits 3a and 4a are provided, respectively. The interrupt signals are generated by the interrupt signal generating circuits 3a and 4a and transmitted to the device 1 through the data buses 9 and 10. Output.

When the device 3 or the device 4 generates an interrupt signal by the interrupt signal generating circuit 3a or 4a and outputs it to the device 1, the device 1 functions as a passive device which is a partner of both transfer cycles, and 3 or the device 4 recognizes that data transfer is requested.

At this time, the device 1 starts a data transfer cycle for the device 3 or the device 4 which has output the interrupt signal, and executes the transfer of the target data. However, at this point, it is unclear whether the device 3 or the device 4 requests data reading (read) or writing (write). Therefore, in this embodiment, signals are transmitted and received as follows. The operation in this case will be described later in detail with reference to the timing chart shown in FIG.

Each of the devices 1 to 5 includes an I ² C
The circuit at the connection between the bus interface and the external I ² C bus 6 has the same configuration as shown in FIG. FIG. 2 shows circuits 1a and 3a of a connection portion between a device 1 having only a master function and a device 3 having only a slave function.
Only shows. The circuits 1a and 3a have exactly the same configuration as the circuits 101a and 103a shown in FIG. 7 and have the same operation, and therefore description thereof is omitted.

Next, the operation of the data transfer system according to the present invention having the above-described configuration will be specifically described. FIG. 3 is a timing chart showing signal exchange in a data transfer cycle performed between the device 1 having only the master function and the device 3 having only the slave function.

That is, in the timing chart shown in FIG. 3, the device 1 starts a data transfer cycle and transmits 1-byte (8-bit) data by inputting the interrupt signal output by the device 3 to the device 1. is there. In this case, the device 3 does not activate the data transfer by itself when it is necessary to initiate the data transfer, but instead outputs an interrupt signal for notifying the device 1 of the request. . The device 1 inputs this interrupt signal.

FIG. 4 is a block diagram showing the circuit configuration of the I ² C bus interface portion of the device 1, and FIG. 5 is a block diagram showing the circuit configuration of the I ² C bus interface portion of the device 3.

First, the configuration of these circuits will be described. In the I ² C bus interface of the device 1 shown in FIG. 4, a master control block 51 is connected to an internal data bus 60. The master control block 51 controls the master function, but is configured without including any of the bus state detection circuit and the bus arbitration circuit therein.

The master control block 51 receives an interrupt signal (IRQ signal) 55 as shown in FIG. The clock control circuit 43 determines the transfer clock speed during the master function, and outputs the clock line output SCL-OU.
T is output to the lock line 7 via the transistor 22.

The shift register 46 stores a slave address and other necessary data. The data is stored in the input buffer circuit 2 as a data line input SDA-IN.
7 through a data line 8. The output control circuit 47 is a circuit that outputs data from the shift register 46 in accordance with a control clock, and the data is output to the data line 8 through the transistor 23 as a data line output SDA-OUT.

In the I ² C bus interface of the device 3 shown in FIG. 5, a slave control block 52 is connected to an internal data bus 60. The slave control block 52 controls the slave function, but does not include any of the bus state detection circuit and the bus arbitration circuit.

This slave control block 52 outputs an interrupt signal (IRQ signal) 55 as shown in FIG. This interrupt signal 55 is input to the device 1 through the data bus 9 shown in FIG. The noise removing circuit 44 removes an unnecessary signal included in the clock line input SCL-IN input from the clock line 7 via the input buffer circuit 28.

In addition, a shift register 46 and an output control circuit 47 similar to the I ² C bus interface shown in FIG.
Having. The address comparator 48 compares the fetched slave address with the slave address stored in the slave address register 49, and outputs the result to the slave control block 52. The slave address register 49 stores a slave address and other necessary data.

In the block diagram described above, the operation will be described on the assumption that the device 1 becomes a passive device that starts a data transfer cycle in accordance with the transfer request of the device 3 functioning as the requesting device.

At this time, the device 3 sends an interrupt signal 5 as a transfer request signal when requesting a data transfer cycle.
5 is generated by the interrupt signal generation circuit 3a shown in FIG.
This is output to the device 1 via the data bus 9. On the other hand, upon input of the interrupt signal 55, the device 1 recognizes that the device 3 that has output the interrupt signal 55 requests a data transfer cycle (want to cause data transfer), The data transfer cycle to be performed is executed as follows.

That is, the CPU 13 of the device 1 receives a notification that the interrupt signal 55 has been input from the master control block 51, whereby the master control block 51 is sent to the device 3 via the internal data bus 60. A signal for notifying that data is to be written is output. Next, the CPU 13 similarly outputs a signal (7-bit signal from A6 to A0) designating the address of the device 3 to which the data is to be written via the internal data bus 60 and causes the shift register (SR) 46 to store the signal.

When the master control block 51 receives a signal from the CPU 13 through the internal data bus 60,
² Without performing the process of checking whether the C bus 6 is in use or not,
The output of the transistor 23 is set to low level “L” by the data line output SDA-OUT, and the start of data transfer is notified to the device 3 through the I ² C bus 6. At this time, when the data line 8 changes from the high level “H” to the low level “L” when the clock line 7 of the I ² C bus 6 is at the high level “H”, the start of the transfer cycle is sent to the device 3. Notice.

Thereafter, the master control block 51 periodically outputs the clock through the clock line 7 and also transmits the slave address (A6 to A0) stored in the shift register 46 through the data line 8 from the upper bits A6. A total of 7 bits are output one bit at a time.

Then, following the output of the 7-bit slave address, a 1-bit signal (read / write bit: RWB) indicating the data transfer direction is output by the device 3.
Is output. By inputting the read / write bit to the device 1, the device 1 can know the data transfer direction, that is, whether the data is written or read. That is, the data transfer direction is controlled by the 1-bit read / write bit output from the device 3 following the 7-bit slave address, and the subsequent data transfer cycle can be executed.

On the other hand, the device 3 takes in the 7-bit signal (slave address) via the buffer circuit 27 connected to the data line 8 and
To be stored. The slave address fetched by the comparator 48 is stored in advance in a slave address register (SA
R) Compare with the slave address stored in 49,
The result is output to the slave control block 52.

At this time, if the comparison results match, that is, if the device 1 has selected itself as a slave device, an acknowledgment signal (ACKB) is output to the data line 8 (low level and low level). This causes the device 1 to notify the device 1 that the device 3 has responded as a slave device.

Next, as shown in FIG. 3, the device 1 stores data to be written (write data) in the shift register 46 in the same manner as the data of the slave address for specifying the slave device, and then stores it in one bit. The data is output to the data line 8 at a time.

Then, the device 3 selected as the slave device sends the signal output to the data line 8 to 1
It is received bit by bit and stored in the shift register 46. The device 3 receives the data one bit at a time while executing the same processing, and when receiving the data for 8 bits, in order to inform the device 1 that the data has been correctly received, the acknowledge signal (ACKB) is set to a low level. Output.

Then, the 8-bit write data stored in the shift register 46 is output to the CPU 13 inside the device via the internal data bus 60. On the other hand, when the data writing is completed, the device 1 raises the data line 8 from the low level to the high level while the clock line 7 is at the high level, thereby notifying the device 3 of the end of the data transfer. With the above processing, the transfer cycle ends.

As described above, the devices 1 to 5
Only the device 1 can start a bus cycle as a master device. Therefore, FIGS. 4 and 5
Looking at the circuit configuration of the I ² C bus interface shown in (1), it is not necessary for the device 1 to provide the master control block 51 with a bus state detection circuit for detecting whether or not the I ² C bus 6 is in use. It is not necessary to provide a bus arbitration circuit for judging whether or not the user has the right to cause a bus cycle.

Since the device 1 does not need to be a slave function only with a master function, there is no need to provide a noise removing circuit. In addition, the circuit configuration does not require a slave address register, a comparator, a multiplexer, and the like. Note that the interrupt signal generation circuit may not be provided, but if this is done, an interrupt signal input processing circuit will be provided in the master control block 51, which will offset the scale of the circuit.

As for the device 3, as in the case of the device 1, not only is it not necessary to provide a bus state detection circuit and a bus arbitration circuit, but also the slave function alone does not make the master function. It is not necessary to provide a noise removing circuit. In addition, a circuit configuration that does not require a slave address register, a comparator, a multiplexer, and the like can be provided. It is to be noted that an interrupt signal input processing circuit is provided in the master control block instead of providing an interrupt signal generation circuit, similarly to the device 1.

As described above, since the circuit configuration of each of the device 1 and the device 3 is simplified, the control thereof is also simplified. Moreover, the common I ² C
Since only the device 1 is connected to the bus as the master device, there is no need to monitor that the data transfer cycle is simultaneously activated by each device, and it is not necessary to perform bus arbitration. Further, since the circuit configuration is simplified, there is an advantage that the design of the control block is facilitated and malfunctions are less likely to occur.

In the above description of the embodiment, I ² C
Although the description has been made using the bus, it goes without saying that the present invention can be similarly applied to a master / slave type data transfer system using another common bus and a data transfer method using the same.

However, for example, in the case of the PCI bus standard,
It is a parallel bus instead of a serial bus, and the device that initiates a data transfer cycle is the initiator, not the master device, and the device that responds to the data transfer cycle is called the target, not the slave, but only called differently. The concept of the bus transfer method is the same.

[0077]

According to the data transfer system of the present invention, the number of devices capable of initiating a data transfer cycle by itself is one.
Only one device can be used, and the other devices can be configured with the devices that request them. Therefore, monitoring of the bus state and bus arbitration are not required, and the devices can be configured without providing a circuit for that. Therefore, the scale of the interface circuit of each device can be reduced, the circuit on the LSI or the substrate can be reduced, and the cost can be reduced. Further, since the monitoring of the bus state and the bus arbitration become unnecessary, not only the control for data transfer becomes easy, but also a malfunction is less likely to occur.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a data transfer system according to the present invention.

FIG. 2 is a diagram showing I of device 1 and device 3 in FIG.
FIG. 2 is a circuit diagram showing a configuration example of a connection portion between a ² C bus interface and a clock line 7 and a data line 8 of an I ² C bus.

FIG. 3 is a timing chart showing exchange of signals in a data transfer cycle performed between the device 1 and the device 3;

FIG. 4 is a block diagram illustrating a configuration example of an I ² C bus interface portion of the device 1;

FIG. 5 is a block diagram showing a configuration example of an I ² C bus interface part of a device 3;

FIG. 6 is a block diagram illustrating a configuration example of a conventional data transfer system.

FIG. 7 shows I ² C of devices 101 and 103 in FIG.
Bus interface and clock line 7 of I ² C bus 6
FIG. 2 is a circuit diagram showing a configuration example of a connection portion with a data line 8.

FIG. 8 is a timing chart showing exchange of signals in a data transfer cycle similarly performed between the devices 101 and 103.

FIG. 9 is a block diagram showing a configuration example of an I ² C bus interface of the device 101;

[Explanation of symbols]

1: device (master) 2 to 5: device (slave) 3a, 4a: interrupt signal generation circuit 6: I ² C bus 7: clock line 8: data line 9, 10: data bus 22 to 25: transistor 26 to 29: Input buffer circuit 43: Clock control circuit 44: Noise removal circuit 46: Shift register 47: Output control circuit 48: Comparator 49: Slave address register 51: Master control block 52: Slave control block 55: Interrupt signal 60: Internal data bus

Claims (6)

[Claims] 1. A data transfer system in which a plurality of functional devices are connected to a common bus and configured to perform data transfer between the devices via the common bus, wherein a data transfer cycle is performed in the plurality of devices. The device that needs to cause the data transfer has a means for transmitting a data transfer request signal to a device that performs data transfer, and the device that performs the data transfer transmits the signal of the data transfer request. A data transfer system comprising: means for receiving; and means for activating a data transfer cycle by receiving the signal. 2. The data transmission request signal transmitting means is an interrupt signal transmitting means, and the data transfer request signal receiving means is an interrupt signal receiving means. 2. The data transfer system according to 1. 3. The device that needs to generate the transfer cycle is a slave device, and the device that performs the data transfer is a master device.
Or the data transfer system according to 2. 4. The common bus is an I ² C bus, and the master device has means for outputting a slave address, and the slave device specified by the slave address outputs a signal indicating a data transfer direction thereafter. 4. The data transfer system according to claim 3, further comprising: means for transmitting to the master device. 5. A data transfer method for performing data transfer between a plurality of functional devices connected to a common bus through the common bus, wherein a device which needs to cause a data transfer cycle among the plurality of devices is: A data transfer method comprising: transmitting a data transfer request signal to a device that performs data transfer; and receiving the signal and initiating a data transfer cycle. . 6. between at least one master device and a plurality of slave devices are connected to a common I ² C bus, a data transfer method for transferring data through the I ² C bus, it said in the plurality of slave devices A slave device that needs to cause a data transfer cycle transmits a data transfer request signal to the master device with which data transfer is to be performed, and the master device receives the signal and receives a data transfer cycle. And outputting a slave address specified by the slave address, and the slave device specified by the slave address transmits a signal indicating a subsequent data transfer direction to a master device with which the data transfer is performed. Transfer method.