JP2000231362A - Driving method for plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the driving method of a plasma display panel capable of enhancing the contrast with low power consumption even while suppressing spurious profile. SOLUTION: The display period of one field is divided into N pieces of subfields and a first pixel data pulse which generates discharge initializing all discharging cells into either state of light emitting cells or non-light emitting cells only in the subfield of the leading parts in subfield groups consisting of M pieces (2<=M<=N) of continuously arranged subfields among the divided subfields and generates discharge setting the discharging cells into either state of non-light emitting cells or light emitting cells in either of subfields among subfields in the subfield groups is impressed on a plasma display panel. Then, thereafter, only above described light emitting cells are made to emit light only for luminous periods made to correspond to weights of subfields in respective subfields by impressing a second pixel data pulse which is the same as the above described pixel data pulse in at least one subfield among existing subfields.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a plasma display panel (hereinafter, referred to as PDP) of a matrix display system.

[0002]

2. Description of the Related Art As one of such matrix display type PDPs, an AC (AC discharge) type PDP is known.
The AC type PDP includes a plurality of column electrodes (address electrodes),
They are arranged orthogonally to these column electrodes and
And a plurality of row electrode pairs forming a scanning line.
Each row electrode pair and column electrode is covered with a dielectric layer with respect to the discharge space, and has a structure in which a discharge cell corresponding to one pixel is formed at the intersection of the row electrode pair and the column electrode. .

At this time, since the PDP utilizes a discharge phenomenon, the discharge cell has only two states of “light emission” and “non-light emission”. Therefore, a subfield method is used to realize halftone luminance display in such a PDP. In the subfield method, one field period is divided into N subfields, and each subfield has pixel data.
Emission period corresponding to the weight of each bit digit of (N bits)
(The number of times of light emission) is assigned, and light emission driving is performed.

For example, when one field period is divided into six subfields SF1 to SF6 as shown in FIG. 1, SF1: 1 SF2: 2 SF3: 4 SF4: 8 SF5: 16 SF6: 32 Light emission driving is performed at a light emission period ratio.

[0005] For example, when the discharge cells emit light at a luminance of "32", the SFs in the subfields SF1 to SF6 are used.
In the case where light emission is performed only in the subfield SF6 and light emission is performed at the luminance “31”, light emission is performed in the other subfields SF1 to SF5 except the subfield SF6. As a result, it is possible to express halftone luminance in 64 steps. Here, the light emission driving pattern in one field period is inverted between the case where the discharge cell emits light at the luminance “32” as described above and the case where light emission occurs at the luminance “31”.
That is, within one field period, during the period when the discharge cells to be lit at the luminance "32" are emitting light, the luminance "
At 31 ", the discharge cells to emit light are turned off,
During the period in which the discharge cells to emit light at the luminance "31" emit light, the discharge cells to emit light at the luminance "32" are in a non-light emitting state.

Therefore, if a discharge cell to emit light at a luminance of "32" and a discharge cell to emit light at a luminance of "31" are adjacent to each other, a false contour may be visually recognized in this area. Occurs. That is, luminance "
Just before the discharge cells to emit light at 32 "shift from the non-light-emitting state to the light-emitting state, the eyes are shifted to the discharge cells to emit light at the luminance" 31 ". Since they are viewed continuously, a dark line is visually recognized on the boundary between the two, and this appears on the screen as a false contour having no relation to the pixel data, and the display quality is reduced. Lower it.

Further, as described above, since the PDP utilizes a discharge phenomenon, it is necessary to perform a discharge (with light emission) irrelevant to the display content, thereby lowering the image contrast. There was a problem. Furthermore, at present, when commercializing such a PDP, realizing low power consumption is a general problem.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a plasma display panel capable of improving the contrast with low power consumption while suppressing false contours. It is an object of the present invention to provide a driving method.

[0009]

According to the present invention, there is provided a driving method of a plasma display panel, wherein each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged crossing the row electrodes. A method of driving a plasma display panel in which a discharge cell corresponding to one pixel is formed, wherein a display period of one field is divided into N sub-fields, and a continuous one of the N sub-fields is used. The arranged M (2 ≦ M ≦ N) subfields are a subfield group, and all the discharge cells are either light emitting cells or non-light emitting cells only in the head subfield of the subfield group. A reset process for causing a discharge to be initialized to one state, and the discharge cell in any one of the subfields in the subfield group A first pixel data pulse for generating a discharge to be set in one of the non-light emitting cell and the light emitting cell is applied to the column electrode, and the same as the pixel data pulse in at least one of the subsequent subfields Applying a second pixel data pulse to the column electrode, and maintaining a discharge that causes only the light emitting cells to emit light during only a light emission period corresponding to the weight of the subfield in each of the subfields. The light emission process is executed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a schematic configuration of a plasma display device that drives a plasma display panel (hereinafter, referred to as a PDP) to emit light based on a driving method according to the present invention.

In FIG. 2, an A / D converter 1 samples an analog input video signal in accordance with a clock signal supplied from a drive control circuit 2 and converts this into pixel data of, for example, 8 bits per pixel. (Input pixel data) D, which is supplied to the data conversion circuit 30. The drive control circuit 2 synchronizes with a horizontal and vertical synchronizing signal in the input video signal, and outputs a clock signal to the A / D converter 1;
And a write / read signal for the memory 4 is generated. Further, the drive control circuit 2 generates various timing signals to drive and control each of the address driver 6, the first sustain driver 7, and the second sustain driver 8 in synchronization with the horizontal and vertical synchronization signals.

The data conversion circuit 30 converts the 8-bit pixel data D into 14-bit converted pixel data (display pixel data) HD, and supplies the converted data to the memory 4.
The conversion operation of the data conversion circuit 30 is as follows.
It will be described later. The memory 4 sequentially writes the converted pixel data HD according to a write signal supplied from the drive control circuit 2. When writing for one screen (n rows and m columns) is completed by such a writing operation, the memory 4 reads the converted pixel data HD _11-nm for one screen by dividing the converted pixel data HD _11-nm for each bit digit. Are sequentially supplied to the address driver 6 for each row.

The address driver 6 operates in accordance with the timing signal supplied from the drive control circuit 2 to operate the memory 4.
, And generates m pixel data pulses having voltages corresponding to the logic levels of the converted pixel data bits for one row, and applies these to the column electrodes D _{1 to} D _m of the PDP 10, respectively. PDP10 is provided with the column electrodes D ₁ to D _m as address electrodes, the row electrodes X ₁ to X _n and row electrodes Y ₁ to Y _n are arranged orthogonal to these column electrodes. In the PDP 10, a row electrode corresponding to one row is formed by a pair of the row electrode X and the row electrode Y. That is, the row electrode pair of the first row in the PDP 10 is the row electrode X
₁ and Y ₁ , and the row electrode pair in the n-th row is row electrodes X _n and Y _n . The row electrode pairs and the column electrodes are covered with a dielectric layer with respect to the discharge space, and a structure in which a discharge cell corresponding to one pixel is formed at the intersection of each row electrode pair and the column electrode.

Each of the first sustain driver 7 and the second sustain driver 8 generates various drive pulses as described below in accordance with a timing signal supplied from the drive control circuit 2, and supplies these to the row electrodes of the PDP 10. X ₁ ~
Applied to X _n and Y ₁ to Y _n. FIG. 3 is a diagram showing a light emission drive format based on a drive method according to the present invention.
FIG. 4 shows that the address driver 6, the first sustain driver 7, and the second sustain driver 8 each correspond to the column electrode D _{1 of the} PDP 10 according to the light emission drive format.
To D _m, is a diagram showing an application timing of various drive pulses applied to the row electrodes X ₁ to X _n and Y ₁ to Y _n.

In the example shown in FIGS. 3 and 4, the display period of one field is divided into 14 sub-fields SF1 to SF.
Driving of the PDP 10 is performed by dividing into F14. In each subfield, a pixel data writing process Wc for writing pixel data to each discharge cell of the PDP 10 to set a light emitting cell and a non-light emitting cell, and a sustaining light emitting process for keeping only the light emitting cells emit light And Ic.
Further, the simultaneous reset process Rc for initializing all the discharge cells of the PDP 10 is executed only in the first subfield SF1, and the erase process E is executed only in the last subfield SF14.

Here, in the above-mentioned simultaneous reset process Rc,
The first sustain driver 7 and second sustain driver 8 applies a but such reset pulses RP _x and RP _Y shown in Fig. 4 with respect PDP10 the row electrodes X ₁ to X _n and Y ₁ to Y _n, respectively at the same time . As a result, all the discharge cells in the PDP 10 are reset-discharged, and a predetermined wall charge is uniformly formed in each discharge cell. Thereby, PD
All the discharge cells in P10 are light emitting cells whose light emitting state is maintained in a sustain light emitting process described later.

In each pixel data writing process Wc, the address driver 6 operates the pixel data pulse group DP for each row.
_{1 1-n, DP2 1-} n, DP3 1-n, ····, as shown in FIG. 4 the DP14 _1-n, applied sequentially column electrodes D ₁ to D _m. That is, the address driver 6 operates in the subfield S
In F1, the first of each of the converted pixel data HD _11-nm
Applying pixel data pulse group DP1 _1-n corresponding to the first row to the n-th row, respectively, to sequentially column electrodes D ₁ to D _m to but as every one row as shown in FIG. 4 which is generated based on the bit Go.
Also, in the subfield SF2, the pixel data pulse group DP2 _1-n generated based on the second bit of each of the converted pixel data HD11 _-nm is set to 1 as shown in FIG.
Each rows is a sequential to the column electrodes D ₁ to D _m.
At this time, the address driver 6 generates a high-voltage pixel data pulse and applies it to the column electrode D only when the bit logic of the converted pixel data is, for example, a logical level “1”. The second sustain driver 8 controls each pixel data pulse group DP
At the application the same timing, which row electrodes Y ₁ ~ generates a scanning pulse SP such is shown in FIG. 4
Y _n are sequentially applied. At this time, discharge (selective erase discharge) occurs only in the discharge cell at the intersection of the "row" to which the scan pulse SP is applied and the "column" to which the high-voltage pixel data pulse is applied, and the discharge cell in the discharge cell Are selectively erased. Due to the selective erasing discharge, the discharge cells initialized to the state of the light emitting cells in the simultaneous reset process Rc change to non-light emitting cells. Note that no discharge occurs in the discharge cells formed in the "column" where the high-voltage pixel data pulse was not applied, and the discharge cells were initialized in the simultaneous reset process Rc, that is, the state of the light emitting cells. To maintain.

That is, by performing the pixel data writing process Wc, a light emitting cell in which a light emitting state is maintained in a sustain light emitting process to be described later and a non-light emitting cell which remains in a light-off state become:
This is set alternatively in accordance with the pixel data, and so-called pixel data is written into each discharge cell. Further, in each sustain emission step Ic, the first sustain driver 7 and the second sustain driver 8 drive the row electrodes X ₁ to X ₁ .
Applying pulses IP _X and IP _Y maintained alternately as shown in FIG. 4 with respect to X _n and Y ₁ to Y _n. During this time period the discharge cells in which the wall charges by the pixel data writing process Wc are remain, i.e. light emitting cells according sustain pulses IP _X and IP _Y are alternately applied,
The discharge light emission is repeated to maintain the light emission state. Note that the sustaining period of light emission performed in the sustaining light emission process Ic differs for each subfield as shown in FIG.

That is, when the light emission period in the sustain light emission step Ic in the subfield SF1 is "1", SF1: 1 SF2: 3 SF3: 5 SF4: 8 SF5: 10 SF6: 13 SF7: 16 SF8: 19 SF9 : 22 SF10: 25 SF11: 28 SF12: 32 SF13: 35 SF14: 39

That is, each of the subfields SF1 to SF
The ratio of the number of times of light emission of No. 14 is set to be non-linear (that is, the inverse gamma ratio, Y = X ^2.2 ), whereby the non-linear characteristic (gamma characteristic) of the input pixel data D is corrected. Further, as shown in FIG. 4, in the erasing step E in the last subfield, the address driver 6 generates an erasing pulse AP and sends it to the column electrodes D _{1 -m.}
To each of. The second sustain driver 8 generates an erasing pulse EP simultaneously with the application timing of the erasing pulse AP and applies it to each of the row electrodes Y _{1 to} Y _n .
By simultaneously applying these erase pulses AP and EP, PD
An erase discharge is generated in all the discharge cells at P10, and the wall charges remaining in all the discharge cells disappear. That is, by the erasing discharge, all the discharge cells in the PDP 10 become non-light emitting cells.

FIG. 5 is a diagram showing all the patterns of the light emission drive performed based on the light emission drive format as shown in FIGS. As shown in FIG. 5, a selective erase discharge is performed on each discharge cell only in the pixel data writing process Wc in one of the subfields SF1 to SF14 (indicated by black circles). .
That is, the execution of the simultaneous reset process Rc
The wall charges formed in all of the 10 discharge cells remain until the selective erase discharge is performed, and promote discharge light emission in the sustain light emission process Ic in each of the subfields SF existing therebetween (indicated by white circles). Shown). That is, each discharge cell becomes a light-emitting cell until the above-described selective erasure discharge is performed within one field period, and in the sustain light-emitting process Ic in each of the subfields existing between the discharge cells, FIG.
The light emission is continued at the light emission period ratio as shown in FIG.

At this time, as shown in FIG. 5, the number of transitions of each discharge cell from a light-emitting cell to a non-light-emitting cell is always set to one or less in one field period. That is, a light emission driving pattern in which a discharge cell set as a non-light emitting cell is returned to a light emitting cell once during one field period is prohibited. Therefore, as shown in FIGS. 3 and 4, the simultaneous reset operation involving strong light emission need not be performed only once in one field period even though it is not involved in image display. Can be suppressed.

In addition, since the selective erase discharge performed within one field period is at most one time as shown by the black circle in FIG. 5, the power consumption can be suppressed. Further, as shown in FIG. 5, there is no light emitting pattern in which the light emitting state and the light emitting state are not reversed in one field period, so that a false contour can be suppressed.

Here, according to the light emission drive pattern as shown in FIG. 5, the light emission luminance ratio is as follows: 0, 1, 4, 9, 17, 27, 40, 56, 75, 97, 122, 150 , 182, 217, 256｝, which is a 15-step halftone expression. However, the pixel data D supplied from the A / D converter 1 expresses 8 bits, that is, 256 gray levels.

Therefore, even in the above-described 15-step gradation driving, 256-step half-tone display is performed in a pseudo manner.
The data conversion is performed by the data conversion circuit 30 shown in FIG. FIG. 6 is a diagram showing the internal configuration of the data conversion circuit 30. In FIG. 6, an ABL (automatic brightness control) circuit 31 controls an average brightness of an image displayed on the screen of the PDP 10 to fall within a predetermined brightness range.
The brightness level of the pixel data D for each pixel sequentially supplied from the A / D converter 1 is adjusted, and the obtained brightness adjustment pixel data _DBL is converted to a first data conversion circuit 32.
To supply.

The adjustment of the luminance level is performed before the inverse gamma correction is performed by setting the ratio of the number of times of light emission of the subfield to non-linear as described above. Therefore, the ABL circuit 31
Is configured to perform inverse gamma correction on pixel data (input pixel data) D and automatically adjust the luminance level of the pixel data D according to the average luminance of the inverse gamma-converted pixel data obtained at this time. . This prevents the display quality from deteriorating due to the brightness adjustment.

FIG. 7 is a diagram showing the internal configuration of the ABL circuit 31. In FIG. 7, the level adjustment circuit 310
Outputs the luminance adjusted pixel data D _BL obtained by adjusting the level of the pixel data D in accordance with the average brightness determined by the average brightness detection circuit 311 to be described later. The data conversion circuit 312 converts the luminance adjustment pixel data _DBL into an inverse gamma characteristic (Y = X) having a non-linear characteristic as shown in FIG.
^2.2 ) Inverted gamma converted pixel data Dr
And supplies it to the average luminance level detection circuit 311. That is, the data conversion circuit 312 performs inverse gamma correction on the luminance adjustment pixel data _DBL to convert pixel data (inverse gamma converted pixel data Dr) corresponding to the original video signal from which gamma correction has been canceled. It will be restored. The average luminance detection circuit 311 specifies the light emission period in each subfield, for example, as shown in FIG.
4, a luminance mode capable of driving the PDP 10 to emit light at a luminance corresponding to the average luminance obtained as described above is selected, and a luminance mode signal LC indicating the selected luminance mode is supplied to the drive control circuit 2. At this time, the drive control circuit 2 performs the light emission sustaining period in the sustaining light emission process Ic of each of the subfields SF1 to SF14 shown in FIG.
The number of sustain pulses applied in each sustain emission step Ic is set according to the mode specified by the luminance mode signal LC as shown in FIG. That is, the light emission period in each subfield shown in FIG. 3 indicates the light emission period when the brightness mode 1 is set. If the brightness mode 2 is set, SF1: 2 SF2: 6 SF3: 10 SF4: 16 SF5: 20 SF6: 26 SF7: 32 SF8: 38 SF9: 44 SF10: 50 SF11: 56 SF12: 64 SF13: 70 SF14: 78 Emission in each subfield. Driving is performed.

In this light emission driving, the ratio of the number of times of light emission in each of the subfields SF1 to SF14 is set to be non-linear (that is, inverse gamma ratio, Y = X ^2.2 ). Is corrected. Also, the average luminance detection circuit 311
Calculates the average luminance from the inverse gamma converted pixel data Dr and supplies the average luminance to the level adjustment circuit 310.

The first data conversion circuit 32 in FIG.
Based on the conversion characteristic as shown in FIG. 10, the luminance adjustment pixel data _DBL of 256 gradations (8 bits) is _calculated as 14 × 16 /
8 bits (0 to 22) converted to 255 (224/255)
It is converted into the converted pixel data HD _p 4) to the multi-gradation processing circuit 33. Specifically, 8 bits (0 to 255)
Although the luminance adjusted pixel data D _BL shown in FIGS. 11 and 12 based on such characteristics are converted in accordance with such a conversion table. That is, the conversion characteristics are set according to the number of bits of the input pixel data, the number of compressed bits by multi-gradation, and the number of display gradations. As described above, the first data conversion circuit 32 is provided in the preceding stage of the multi-gradation processing circuit 33 to be described later, and the conversion is performed according to the number of display gradations and the number of compression bits by the multi-gradation. pixel data D _BL of upper bit group (corresponding to multi-gradation pixel data) and low-order bit group (truncated data: error data) cut to a bit boundary, to perform multi-gradation processing based on the signal Has become. As a result, it is possible to prevent the occurrence of luminance saturation due to the multi-gradation processing and the occurrence of a flat portion of the display characteristics (that is, the occurrence of gradation distortion) that occurs when the display gradation is not at the bit boundary.

Since the lower bit group is discarded, the number of gradations is reduced.
This is obtained in a pseudo manner by the operation of the multi-tone processing circuit 33 described below. FIG. 13 is a diagram showing the internal configuration of the multi-tone processing circuit 33. As shown in FIG. 13, the multi-gradation processing circuit 33 includes an error diffusion processing circuit 3
30 and a dither processing circuit 350.

[0031] First, the data separation circuit in the error diffusion processing circuit 330 331, the error data of lower two bits in the converted pixel data HD _P of 8 bits supplied from the first data conversion circuit 32, the upper 6 bits Is separated as display data. The adder 332, delay and the lower two bits of the converted pixel data HD in _P as such error data, a delay output from the delay circuit 334, an added value obtained by adding the multiplication outputs of the coefficient multipliers 335 The signal is supplied to a circuit 336. The delay circuit 336 delays the addition value supplied from the adder 332 by a delay time D having the same time as the clock cycle of the pixel data, and delays the addition value by a delay addition signal AD _1.
Are supplied to the coefficient multiplier 335 and the delay circuit 337, respectively.

The coefficient multiplier 335 outputs the delayed addition signal A
The multiplication result obtained by multiplying D ₁ by a predetermined coefficient value K ₁ (for example, “7/16”) is supplied to the adder 332. Delay circuit 3
37, further the delay addition signal AD ₁ - supplied to the delay circuit 338 which is delayed by (1 horizontal scanning period the delay time D × 4) comprising time as a delay addition signal AD _2.
Delay circuit 338, such delayed addition signal AD ₂ further delayed addition signal AD ₃ a delayed only the delay time D
Is supplied to the coefficient multiplier 339. Also, the delay circuit 33
8, further the delay time D of such delay addition signal AD ₂
A signal delayed by the time of × 2 is a delayed addition signal AD
₄ is supplied to the coefficient multiplier 340. Further, the delay circuit 338 converts the delay addition signal AD ₂ into the delay time D
A signal delayed by the time of × 3 is a delayed addition signal AD
_{The value 5} is supplied to the coefficient multiplier 341.

The coefficient multiplier 339 outputs the delayed addition signal A
The multiplication result obtained by multiplying D ₃ by a predetermined coefficient value K ₂ (for example, “3/16”) is supplied to the adder 342. Coefficient multiplier 34
0, a predetermined coefficient value K ₃ to the delay addition signal AD ₄ (e.g., "5/16") adders multiplication result obtained by multiplying the 34
Feed to 2. Coefficient multiplier 341, a predetermined coefficient value K ₄ to the delay addition signal AD ₅ (e.g., "1/16") to the adder 342 the multiplication result obtained by multiplying the.

The adder 342 includes the coefficient multiplier 339,
An addition signal obtained by adding the multiplication results supplied from each of 340 and 341 is supplied to the delay circuit 334.
The delay circuit 334 delays the added signal by the delay time D and supplies it to the adder 332.
The adder 332 outputs the error data (converted pixel data HD _P
(The lower 2 bits in the middle), the delay output from the delay circuit 334, and the multiplication output of the coefficient multiplier 335. At this time, if there is no carry, the logical level is "0" and there is carry. In this case, a carry-out signal C _O having a logical level “1” is generated and supplied to the adder 333.

The adder 333 outputs to the display data (upper 6 bits in the converted pixel data HD _P), a material obtained by adding the carry-out signal C _O of 6 bits as the error diffusion processing pixel data ED. The operation of the error diffusion processing circuit 330 having such a configuration will be described below.

For example, a PDP 1 as shown in FIG.
Error diffusion processed pixel data E corresponding to the pixel G (j, k) of 0
To obtain D, first, a pixel G (j, k-1) on the left side of the pixel G (j, k), a pixel G (j-1, k-1) on the upper left, and a pixel G (j-1, k) and each error data corresponding to the pixel G (j-1, k + 1) on the upper right, that is, error data corresponding to the pixel G (j, k-1): delay Addition signal A
D1 Error data corresponding to _one pixel G (j-1, k + 1): delayed addition signal AD Error data corresponding to _three pixels G (j-1, k): delayed addition signal A
D ₄ pixel G (j-1, k- 1) to the error data corresponding: a delay addition signal AD ₅ each weighted addition with a predetermined coefficient value K ₁ ~K ₄ as mentioned above. Then, the addition result, the lower two bits of the converted pixel data HD _P, i.e. pixel G (j, k) by adding the error data corresponding to the carry-out signal C _O of 1 bit obtained when the Top 6 of the converted pixel data HD in _P a
The bit amount, that is, the value added to the display data corresponding to the pixel G (j, k) is referred to as error diffusion processed pixel data ED.

The error diffusion processing circuit 330, by such a configuration, the display data upper 6 bits in the converted pixel data HD _P, captures the remaining lower two bits as error data, the peripheral pixels {G (j, k- 1), G (j-1, k + 1), G (j-1, k),
G (j−1, k−1) 誤差 The weighted sum of the error data for each is reflected in the display data.
By this operation, the luminance of the lower 2 bits in the original pixel {G (j, k)} is pseudo-expressed by the peripheral pixels,
Therefore, with the number of bits less than 8 bits, that is, 6 bits of display data, the same luminance gradation expression as that of the 8 bits of pixel data can be achieved.

If the error diffusion coefficient value is constantly added to each pixel, noise due to the error diffusion pattern may be visually recognized, thereby deteriorating the image quality. Therefore, the error diffusion coefficients K _{1 to} K ₄ to be assigned to each of the four pixels may be changed for each field as in the case of the dither coefficient described later. The dither processing circuit 350 performs dither processing on the error diffusion processing pixel data ED supplied from the error diffusion processing circuit 330, thereby obtaining the 6-bit error diffusion processing pixel data ED.
Also generates a multi-gradation processing pixel data D _S which was reduced to further 4 bits the number of bits while maintaining a comparable luminance gradation level. In the dither processing, one intermediate display level is expressed by a plurality of adjacent pixels.
For example, when gradation display corresponding to 8 bits is performed using upper 6 bits of pixel data of 8 bits of pixel data,
Four pixels adjacent to each other in the left, right, up, and down are set as one set, and four dither coefficients a to d each having a different coefficient value are assigned to each piece of pixel data corresponding to each pixel of the set and added. According to such dither processing, combinations of four different intermediate display levels occur in four pixels. Therefore, even if the number of bits of the pixel data is 6 bits, the luminance gradation level that can be expressed is four times, that is, halftone display equivalent to 8 bits is possible.

However, if the dither patterns of the dither coefficients a to d are constantly added to each pixel,
Noise due to the dither pattern may be visually recognized, and image quality may be impaired. Therefore, the dither processing circuit 350 changes the dither coefficients a to d to be assigned to each of the four pixels for each field.

FIG. 15 is a diagram showing the internal configuration of the dither processing circuit 350. In FIG. 15, a dither coefficient generation circuit 352 generates four dither coefficients a, b, c, and d for every four pixels adjacent to each other, and sequentially supplies these to an adder 351. For example, as shown in FIG. 16, the pixels G (j, k) and G (j, k + 1) corresponding to the j-th row,
Pixel G (j + 1, k) and pixel G (j + 1, k +) corresponding to the (j + 1) th row
1) four dither coefficients a corresponding to the four pixels
b, c and d are generated. At this time, the dither coefficient generation circuit 3
A step 52 changes the dither coefficients a to d to be assigned to each of these four pixels for each field as shown in FIG.

That is, in the first first field, pixel G (j, k): dither coefficient a pixel G (j, k + 1): dither coefficient b pixel G (j + 1, k): dither coefficient c Pixel G (j + 1, k + 1): dither coefficient d In the next second field, pixel G (j, k): dither coefficient b pixel G (j, k + 1): dither coefficient a pixel G ( j + 1, k): dither coefficient d pixel G (j + 1, k + 1): dither coefficient c In the next third field, pixel G (j, k): dither coefficient d pixel G (j, k) +1): dither coefficient c pixel G (j + 1, k): dither coefficient b pixel G (j + 1, k + 1): dither coefficient a Then, in the fourth field, pixel G (j, k) : Dither coefficient c Pixel G (j, k + 1): Dither coefficient d Pixel G (j + 1, k): Dither coefficient a Pixel G (j + 1, k + 1): Dither coefficient b The dither coefficients a to d are repeatedly circulated and generated, and supplied to the adder 351. The dither coefficient generation circuit 352 includes the first to fourth fields as described above.
Repeat the field operation. That is, when the dither coefficient generation operation in the fourth field is completed, the operation returns to the operation in the first field again, and the above-described operation is repeated.

The adder 351 is connected to the error diffusion processing circuit 3
The pixels G (j, k) and G (j, k +) supplied from
1), the pixel G (j + 1, k), and the error diffusion processing pixel data ED corresponding to each of the pixels G (j + 1, k + 1), and the dither coefficient assigned to each field as described above. a to d are added to each other, and the obtained dither added pixel data is supplied to the upper bit extraction circuit 353.

For example, in the first field shown in FIG. 16, the error diffusion processing pixel data ED + corresponding to the pixel G (j, k)
Error diffusion processing pixel data ED corresponding to dither coefficient a and pixel G (j, k + 1)
+ Dither coefficient b, error diffusion processed pixel data ED corresponding to pixel G (j + 1, k)
+ Dither coefficient c, error diffusion processed pixel data E corresponding to pixel G (j + 1, k + 1)
Each of the D + dither coefficient d is sequentially supplied to the upper bit extraction circuit 353 as dither added pixel data.

The upper bit extracting circuit 353 extracts until the upper 4 bits of such dither-added pixel data, and supplies the second data conversion circuit 34 shown in FIG. 6 as the multi-gradation pixel data D _S . Second data conversion circuit 34
Is such a multi-gradation pixel data D _S in accordance Although such a conversion table shown in FIG. 17, the sub-field SF1~
The image data is converted into converted pixel data (display pixel data) HD consisting of the first to 14th bits corresponding to each of the SFs 14. Note that multi-gradation pixel data D _S is the 224/225 input pixel data D of 8 bits (256 gradations) in accordance with a first data conversion (the conversion table of FIG. 11 and FIG. 12), furthermore, for example, error The two bits are each compressed by multi-gradation processing such as diffusion processing and dither processing, and converted into data of a total of 4 bits (15 gradations).

Here, the first in the converted pixel data HD
Of the 14th to 14th bits, the bit of the logic level "1" indicates that the selective erase discharge is to be performed in the pixel data writing process Wc in the subfield SF corresponding to the bit. Here, the conversion pixel data HD corresponding to each discharge cell of the PDP 10 is supplied to the address driver 6 via the memory 4. At this time, the form of the converted pixel data HD corresponding to one discharge cell is always one of 15 patterns as shown in FIG. The address driver 6 performs the first to the first conversion in the converted pixel data HD.
The fourteenth bit is assigned to each of subfields SF1 to SF14, and a high-voltage pixel data pulse is generated in pixel data writing process Wc in the corresponding subfield only when the bit logic is at logic level "1". Then, this is applied to the column electrode D of the PDP 10. As a result, the selective erasing discharge is generated.

As described above, the data conversion circuit 30
The 14-bit conversion pixel data H is
D, and the gradation display in 15 steps as shown in FIG. 17 is performed. However, by the operation of the multi-gradation processing circuit 33 as described above, the actual gradation expression in visual sense is obtained. It becomes 256 gradations. In the above embodiment,
As a method of writing pixel data, at the beginning of one field, wall charges are forcibly formed in each discharge cell in advance, and all discharge cells are set as light emitting cells, and the wall charges are selectively formed according to the pixel data. Has been described, the so-called selective erasure addressing method in which pixel data is written by erasing the pixel data is adopted.

However, the present invention can be similarly applied to a case where a so-called selective write address method in which wall charges are selectively formed according to pixel data as a method of writing pixel data. It is. FIG.
FIG. 4 is a diagram showing a light emission drive format when such a selective write address method is adopted.

FIG. 19 shows a column electrode D _{1 of the} PDP 10 based on the light emission drive format shown in FIG.
To D _m, it is a diagram showing an application timing of the applied various drive pulses to the row electrodes X ₁ to X _n and Y ₁ to Y _n. FIG. 20 is a diagram showing a conversion table used in the second data conversion circuit 34 when such a selective write address method is adopted, and all patterns of light emission driving performed within one field period.

As shown in FIG. 19, when the above-mentioned selective write address method is adopted, first, in the simultaneous reset step Rc in the first subfield SF14, the first
Sustain driver 7 and second sustain driver 8
Simultaneously applying a respective reset pulses RP _x and RP _Y to PDP10 the row electrodes X and Y. With this, PDP
All the discharge cells in 10 are reset-discharged to forcibly form wall charges in each discharge cell (R ₁ ). Immediately thereafter, the first sustain driver 7, by applying simultaneously the erase pulse EP to the PDP10 in the row electrode X ₁ to X _n, thereby erasing the wall charges formed in all the discharge cells (R ₂₎ . That is, according to the execution of the simultaneous reset process Rc shown in FIG. 19, all the discharge cells in the PDP 10 are initialized to the state of the non-light emitting cells.

In the pixel data writing step Wc, discharge (selective writing) is performed only at the intersection of the "row" to which the scan pulse SP is applied and the "column" to which the high-voltage pixel data pulse is applied. (Discharge) occurs, and wall charges are selectively formed in the discharge cells. Due to the selective writing discharge, the discharge cells initialized to the non-light emitting cells in the simultaneous resetting step Rc are changed to light emitting cells. The discharge is not generated in the discharge cells formed in the "column" where the high-voltage pixel data pulse is not applied, and the simultaneous reset process R
The state initialized at c, that is, the state of the non-light emitting cell is maintained.

That is, by executing the pixel data writing step Wc, a light emitting cell whose light emitting state is maintained in a sustain light emitting step to be described later and a non-light emitting cell which remains in the light-off state become:
This is set alternatively in accordance with the pixel data, and so-called pixel data is written into each discharge cell. Here, when performing the light emission drive by the selective write address method, as shown in FIG. 20, the selective write is performed only in the subfield SF corresponding to the bit of the logic level "1" in the converted pixel data HD. Discharge is performed (indicated by black circles). At this time, in the subfield SF existing between the first subfield SF14 and the execution of the selective writing discharge, the non-light emitting state is maintained, and the subfield SF where the selective writing discharge is performed is maintained.
The light emitting state is maintained in the subfield SF existing thereafter (indicated by white circles).

As described above, the above-mentioned simultaneous reset operation involving strong light emission despite not being involved in image display is performed only once in one field period as shown in FIGS. Since it is sufficient, reduction in contrast can be suppressed. Even when the selective write address method is applied as the pixel data write method, the selective write discharge performed within one field period is at most one time as shown by the black circle in FIG. The power consumption can be reduced. Furthermore, as shown in FIG. 20, there is no light emission drive pattern in which the light emitting state and the non-light emitting state are inverted in one field period, so that false contour can be suppressed. It is.

As described above, in the driving method shown in FIGS. 3 to 20, first, all the discharge cells are set to the light emitting cells only in the first subfield within one field period.
(When the selective erase address method is used) or non-light emitting cells
A discharge is generated which is initialized to the state (when the selective write address method is adopted). Next, only in the pixel data writing process in any one of the subfields, each discharge cell is set to a non-light emitting cell or a light emitting cell according to the pixel data. Further, in the light emission sustaining process in each subfield, only the light emitting cells emit light only during the light emission period corresponding to the weight of the subfield. According to such a driving method, in the case of the selective erasing address method, the light emission state is sequentially set from the first subfield of one field as the luminance to be displayed increases, while in the case of the selective erasing address method, the display is performed. As the luminance increases, the light emission state is set in order from the last subfield of one field.

In the above embodiment, the simultaneous reset operation performed within one field period is performed once so as to perform the halftone expression of 15 gradations.
By executing the simultaneous reset operation twice, the number of gray scales can be increased. FIG. 21 and FIG.
FIG. 4 is a diagram showing a light emission drive format made in view of such a point.

FIG. 21 shows a case where the selective erase address method as described above is employed as the pixel data writing method.
Reference numeral 2 denotes a light emission drive format applied when the selective write address method is employed. Also in the light emission drive format shown in FIGS. 21 and 22, one field period is divided into subfields SF1 to SF1.
It is divided into 14 sub-fields, i.e., 14 sub-fields. In each subfield, a pixel data writing process W for writing pixel data and setting light emitting cells and non-light emitting cells is performed.
c, and a sustaining light emission step Ic for maintaining the light emitting state only in the light emitting cells. At this time, each sustain emission process I
The light emission period (the number of times of light emission) in c is as follows: when the light emission period in the subfield SF1 is “1”, SF1: 1 SF2: 1 SF3: 1 SF4: 3 SF5: 3 SF6: 8 SF7: 13 SF8: 15 SF9: 20 SF10: 25 SF11: 31 SF12: 37 SF13: 48 SF14: 50

That is, each of the subfields SF1 to SF
The ratio of the number of times of light emission of No. 14 is set to be non-linear (that is, the inverse gamma ratio, Y = X ^2.2 ), whereby the non-linear characteristic (gamma characteristic) of the input pixel data D is corrected. Further, the simultaneous reset process Rc is executed in the head subfield and the middle subfield among these subfields.

In other words, in the light emission driving when the selective erase address method is employed as shown in FIG. 21, the simultaneous resetting process Rc is executed in the subfields SF1 and SF7, and the selective writing as shown in FIG. In the light emission driving when the embedded address method is adopted, the subfields SF14 and SF
6, the simultaneous reset process Rc is executed. or,
As shown in FIGS. 21 and 22, in the last subfield of one field period and the subfield immediately before executing the simultaneous reset process Rc, the wall charges remaining in all the discharge cells disappear. An erasing step E is executed.

FIGS. 23 and 24 show an example of a conversion table used in the first data conversion circuit 32 shown in FIG. 6 when performing the light emission drive based on the light emission drive format shown in FIGS. 21 and 22. FIG.
The first data conversion circuit 32 converts the input luminance adjustment pixel data DBL of 256 gradations (8 pits) to 22 × 16/255 (352/352) based on the conversion tables of FIGS.
And supplies the multi-gradation processing circuit 33 converts the converted pixel data HD _p of 9 bits to 255) (0-352).
The multi-gradation processing circuit 33 performs, for example, 4-bit compression processing in the same manner as described above, and outputs 5-bit (0 to 22) multi-gradation pixel data Ds.

[0059] At this time, the second data converting circuit 34 shown in FIG. 6, 14 bits and converts the multi-gradation pixel data D _S of such 5 bits in accordance Although such a conversion table shown in FIG. 25 or FIG. 26 , The converted pixel data (display pixel data) HD is obtained. At this time, FIG. 25 shows the case where the above-described selective erase address method is adopted as the pixel data writing method.
FIG. 7 is a diagram showing a conversion table of the second data conversion circuit 34 and all patterns of light emission driving used when the selective write address method is adopted.

By performing the driving as shown in FIGS. 21 to 26 in this manner, as shown in FIGS. 25 and 26, the emission luminance ratio becomes {0, 1, 2, 3}. , 6, 9, 17, 22, 30, 37, 45, 57, 65, 82, 90, 113, 121, 15
0, 158, 195, 206, 245, and 256 levels of halftone expression are possible.

As described above, in the driving method shown in FIGS. 21 to 26, the subfields in one field period are divided into two subfield groups consisting of a plurality of subfields arranged consecutively. ing. For example, when the selective erase address method is employed, FIG.
, A subfield group including subfields SF1 to SF6 and a subfield group including SF7 to SF14. At this time, the simultaneous resetting process Rc is performed only in the first subfield of each subfield group, and all the discharge cells are set to the light emitting cells (when the selective erase address method is employed) or the non-light emitting cells.
A discharge is generated which is initialized to the state (when the selective write address method is adopted). Here, in each subfield group, the discharge cells are set to non-light emitting cells or light emitting cells in accordance with the pixel data only in the writing process of the pixel data of any one of the subfields. Furthermore, in the light emission sustaining process in each subfield, only the light emitting cells emit light only during the light emission period corresponding to the weight of the subfield. Therefore, in each subfield group, the simultaneous reset operation and the selective erase operation (selective write operation) are performed once each. According to such a driving method,
In the case of the selective erasure address method, the light emission state is set in order from the first subfield in each subfield group as the luminance to be displayed increases. On the other hand, in the case of the selective erasing address method, as the luminance to be displayed increases, the light emission state is sequentially set from the last subfield in each subfield group.

As described above, FIGS. 17, 20, and 2
5, and in the light emission drive pattern shown in FIG. 26, in one of the pixel data writing steps Wc of the subfields SF1 to SF14, the scan pulse SP and the high-voltage pixel data pulse are applied simultaneously, A selective erase (write) discharge is generated. However, if the amount of charged particles remaining in the discharge cell is small, the selective erasing (writing) discharge does not normally occur even when the scan pulse SP and the high-voltage pixel data pulse are applied simultaneously, and the discharge cell In some cases, the wall charges inside cannot be erased (formed). At this time, even if the pixel data D after the A / D conversion is data indicating low luminance, light emission corresponding to the maximum luminance is performed, and there is a problem that image quality is significantly reduced.

For example, when the conversion pixel data HD is [0100000000000000] when the selective erasure addressing method is adopted as the pixel data writing method, as shown by a black circle in FIG. , The selective erasing discharge is performed, and at this time, the discharge cell changes to a non-light emitting cell. Thereby, SF1 in subfields SF1 to SF14 is
The sustain emission should be performed only in However, if the selective erasure in the subfield SF2 fails and the wall charges remain in the discharge cells, sustain emission is performed not only in the subfield SF1 but also in the subsequent subfields SF2 to SF14. As a result, the highest brightness is displayed.

Therefore, in the present invention, FIGS.
The erroneous light emission operation is prevented by employing the light emission drive pattern as shown in FIG. FIG. 27-
FIG. 33 is a diagram showing an example of a light emission drive pattern designed to prevent such an erroneous light emission operation and a conversion table used in the second data conversion circuit 34 when performing this light emission drive.

At this time, in FIG. 27 to FIG. 31, the light emission drive executed based on the light emission drive format as shown in FIG. 3 or FIG. 18 in which the simultaneous reset step Rc is provided only once during one field period. And the second data conversion circuit 34 in performing this light emission drive.
1 shows an example of a conversion table used in the example.
27 to 29 show the light emission drive format when the selective erase address method as shown in FIG. 3 is employed.
0 and FIG. 31 show the light emission drive patterns executed based on the light emission drive format when the selective write address method as shown in FIG. 18 is adopted, respectively.

In FIGS. 32 and 33, the simultaneous reset process Rc is provided twice in one field period.
Alternatively, FIG. 22 shows an example of all the patterns of the light emission drive performed based on the light emission drive format as shown in FIG. 22, and an example of a conversion table used in the second data conversion circuit 34 when performing the light emission drive. . Here, in the light emission drive pattern shown in FIG. 27, FIG. 30, FIG. 32, or FIG. 33 as described above, as shown by a black circle in the figure, the pixel data writing process At Wc, the selective erase (write) discharge is continuously performed.

According to this operation, even if the wall charges in the discharge cells cannot be normally erased (formed) by the first selective erasing (writing) discharge, the second selective erasing (writing) can be performed. In addition, since the wall charges are normally eliminated (formed) by the discharge, the erroneous sustain light emission as described above is prevented. Note that these two selective erase (write) discharges need not be performed in subfields continuous with each other. In short, after the first selective erase (write) discharge is completed, the second selective erase (write) discharge may be performed in any of the subfields.

FIG. 28 is a diagram showing an example of a light emission drive pattern and a conversion table of the second data conversion circuit 34 made in view of the above points. In the example shown in FIG. 28, the first selective erasing is performed as indicated by a black circle in the drawing.
After performing the (write) discharge, the second selective erase (write) discharge is performed after one subfield is left.

The number of selective erase (write) discharges performed within one field period is not limited to two. FIGS. 29 and 31 are diagrams showing an example of a light emission drive pattern and a conversion table of the second data conversion circuit 34 made in view of the above points. 29 and FIG.
“*” Shown in 1 indicates that the logic level may be either “1” or “0”, and a triangle indicates selective erasing (writing) only when such “*” is at logic level “1”. ) Indicates that a discharge is to be performed.

In short, the writing of pixel data may fail in the first selective erasing (writing) discharge. Therefore, the selective erasing (writing) is performed again in at least one of the subfields existing thereafter. By performing the discharge, the writing of the pixel data is ensured.

[0071]

As described in detail above, in the present invention,
First, the display period of one field is divided into N subfields, and only the first subfield in a subfield group consisting of M (2 ≦ M ≦ N) consecutively arranged subfields is divided into N subfields. A discharge is generated that initializes all the discharge cells to either the light emitting cells or the non-light emitting cells. Here, in any one of the subfields in the subfield group, writing of pixel data is performed by applying a first pixel data pulse for generating a discharge for setting each discharge cell to one of a non-light emitting cell and a light emitting cell. In each subfield, only the light emitting cells emit light during the light emitting period corresponding to the weight of the subfield. At this time, by applying again the same second pixel data pulse as the pixel data pulse in at least one of the subfields existing after the application of the first pixel data pulse, the writing of the pixel data is ensured. I have to.

With this method of driving a plasma display, it is possible to achieve both low power consumption and improved contrast while suppressing false contours.

[Brief description of the drawings]

FIG. 1 is a diagram showing a conventional light emission drive format for performing halftone display of 64 gradations.

FIG. 2 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to a driving method according to the present invention.

FIG. 3 is a diagram showing a light emission drive format when a selective erase address method is adopted.

FIG. 4 is a diagram illustrating an example of application timings of various drive pulses applied to the PDP 10.

FIG. 5 is a diagram showing an example of a light emission drive pattern performed based on the light emission drive format shown in FIG. 3;

FIG. 6 is a diagram showing an internal configuration of a data conversion circuit 30.

FIG. 7 is a diagram showing an internal configuration of an ABL circuit 31;

FIG. 8 is a diagram illustrating conversion characteristics in the data conversion circuit 312.

FIG. 9 is a diagram showing a correspondence relationship between a luminance mode and a light emission period performed in a sustain light emission process of each subfield.

FIG. 10 is a diagram showing conversion characteristics in a first data conversion circuit 32;

11 is a diagram illustrating an example of a conversion table in the first data conversion circuit 32. FIG.

FIG. 12 is a diagram showing an example of a conversion table in the first data conversion circuit 32.

FIG. 13 is a diagram showing an internal configuration of a multi-gradation processing circuit 33.

14 is a diagram for explaining an operation of the error diffusion processing circuit 330. FIG.

FIG. 15 is a diagram showing an internal configuration of a dither processing circuit 350.

FIG. 16 is a diagram for explaining the operation of the dither processing circuit 350;

FIG. 17 is a diagram showing an example of all patterns of light emission driving performed based on the light emission driving format shown in FIG. 3 and an example of a conversion table used in the second data conversion circuit 34 when performing this light emission driving. is there.

FIG. 18 is a diagram showing a light emission drive format when a selective write address method is adopted.

FIG. 19 shows a case where a selective write address method is employed,
FIG. 7 is a diagram showing application timings of various drive pulses applied to P10.

FIG. 20 is a diagram illustrating all patterns of light emission driving when the selective writing address method is adopted, and an example of a conversion table used in the second data conversion circuit 34 when performing the light emission driving.

FIG. 21 is a diagram showing another example of a light emission drive format when a selective erase address method is adopted.

FIG. 22 is a diagram showing another example of a light emission drive format when the selective write address method is adopted.

FIG. 23 is a diagram showing an example of a conversion table used in the first data conversion circuit 32 when performing light emission driving based on the light emission drive format shown in FIG. 21 or FIG.

24 is a diagram showing an example of a conversion table used in the first data conversion circuit 32 when performing light emission driving based on the light emission drive format shown in FIG. 21 or FIG.

25 is a diagram showing an example of all patterns of light emission driving performed based on the light emission drive format shown in FIG. 21 and an example of a conversion table used in the second data conversion circuit 34 when performing this light emission drive. .

26 is a diagram showing an example of all patterns of light emission drive performed based on the light emission drive format shown in FIG. 22 and an example of a conversion table used in the second data conversion circuit 34 when performing this light emission drive. .

FIG. 27 is a diagram showing a light emission drive pattern according to the drive method of the present invention.

FIG. 28 is a diagram showing another example of the light emission drive pattern according to the drive method of the present invention.

FIG. 29 is a diagram showing another example of the light emission drive pattern according to the drive method of the present invention.

FIG. 30 is a diagram showing another example of a light emission drive pattern according to the drive method of the present invention.

FIG. 31 is a diagram showing another example of a light emission drive pattern according to the drive method of the present invention.

FIG. 32 is a diagram showing another example of the light emission drive pattern according to the drive method of the present invention.

FIG. 33 is a diagram showing another example of the light emission drive pattern according to the drive method of the present invention.

[Explanation of Signs of Main Parts]

 2 Drive control circuit 6 Address driver 7 First sustain driver 8 Second sustain driver 10 PDP 30 Data conversion circuit 31 ABL circuit 31 32 First data conversion circuit 33 Multi-gradation processing circuit 34 Second data conversion circuit 330 Error diffusion processing Circuit 350 Dither processing circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 642 G09G 3/20 642E

Claims (10)

[Claims] 1. A plasma forming a discharge cell corresponding to one pixel at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged crossing the row electrodes. A method of driving a display panel, comprising: dividing a display period of one field into N subfields; and sequentially arranging M (2 ≦ M ≦ N) subfields of the N subfields. A sub-field group, a reset step for generating a discharge to initialize all of the discharge cells to only one of the light-emitting cells or non-light-emitting cells only in the first sub-field of the sub-field group, A first generating a discharge for setting the discharge cell to one of the non-light-emitting cell and the light-emitting cell in any one of the sub-fields in the sub-field group; Applying a pixel data pulse to the column electrode, and applying a second pixel data pulse identical to the pixel data pulse to the column electrode in at least one of the subfields present thereafter; A sustaining light emitting step of generating a discharge for causing only the light emitting cells to emit light during a light emitting period corresponding to the weight of the subfield in each of the subfields. 2. The plasma display according to claim 1, wherein the second pixel data pulse is applied to the column electrode in the subfield immediately after the application of the first pixel data pulse. Panel driving method. 3. An erasing step for generating a discharge for setting all the discharge cells to non-light emitting cells only in the last subfield of the subfield group. Driving method of a plasma display panel. 4. In the reset step, a discharge for initializing all the discharge cells to the state of the light emitting cells is generated. In the pixel data writing step, a discharge for setting the discharge cells to the non-light emitting cells is performed. 2. The plasma display panel according to claim 1, wherein the first pixel data pulse causing the first pixel data pulse and the second pixel data pulse identical to the first pixel data pulse are applied to the column electrode. Drive method. 5. A discharge for initializing all of the discharge cells to the non-light emitting cells in the reset step, and a discharge for setting the discharge cells to the light emitting cells in the pixel data writing step. 2. The plasma display panel according to claim 1, wherein the first pixel data pulse causing the first pixel data pulse and the second pixel data pulse identical to the first pixel data pulse are applied to the column electrode. Drive method. 6. A plasma forming a discharge cell corresponding to one pixel at each intersection of a plurality of row electrodes arranged for each scanning line and a plurality of column electrodes arranged crossing the row electrodes. A display panel driving method, wherein a display period of one field is divided into N sub-fields, and all of the discharge cells emit light only in a head sub-field of the N sub-fields. A reset process for generating a discharge for initializing a cell or a non-light-emitting cell to any one of the states; and the non-light-emitting cell or the discharge cell in any one of the N sub-fields. Applying a first pixel data pulse for causing a discharge to be set to one of the light emitting cells to the column electrode, and applying at least one of the subfields existing thereafter; A pixel data writing step of applying a second pixel data pulse identical to the pixel data pulse to the column electrode at 1; and only the light emitting cells in each of the N subfields correspond to the weighting of the subfield. Sustaining light emission process for generating a discharge for emitting light only during the light emitting period,
A method for driving a plasma display panel. 7. The plasma display according to claim 6, wherein the second pixel data pulse is applied to the column electrode in the subfield immediately after the application of the first pixel data pulse. Panel driving method. 8. The erasing step according to claim 6, further comprising the step of causing a discharge for setting all of said discharge cells to a non-light emitting cell only in the last subfield of said one field. A method for driving a plasma display panel. 9. In the reset step, a discharge for initializing all the discharge cells to the state of the light emitting cells is generated. In the pixel data writing step, a discharge for setting the discharge cells to the non-light emitting cells is performed. 7. The plasma display panel according to claim 6, wherein the first pixel data pulse causing the first pixel data pulse and the second pixel data pulse identical to the first pixel data pulse are applied to the column electrodes. Drive method. 10. The reset process generates a discharge that initializes all the discharge cells to the non-light emitting cells, and the discharge that sets the discharge cells to the light emitting cells in the pixel data writing process. 7. The plasma display panel according to claim 6, wherein the first pixel data pulse causing the first pixel data pulse and the second pixel data pulse identical to the first pixel data pulse are applied to the column electrodes. Drive method.