JP2000215071A - Virtual computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of a guest program process by providing a processor dedicated to a control program (host program) process and avoiding a conflict of resources between a guest program and the host program. SOLUTION: In a common memory, a host task queue 53 wherein tasks of a host are queued, a fixed guest task queue #1 (54) of guest tasks operating only on an instruction processor #1, a fixed guest task queue #2 (55) of guest tasks operating only on an instruction processor #2, and a floating guest task queue of guest tasks which can operate on any of the processor #1 or #2 are present; and a processor #3 mainly dispatches the tasks in the host task queue and the processor #1 mainly dispatches the tasks in the task queue #1 and floating guest task queue and dispatches the tasks in the host task queue only when no task is present in those queues. The processor #2 is also the same with the processor #1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual computer system, and more particularly to a computer system having a plurality of physical instruction processors of a physical computer, and having a virtual instruction processor that logically divides and uses the plurality of physical instruction processors. About.

[0002]

2. Description of the Related Art In a virtual computer, a virtual computer control program (hereinafter simply referred to as a control program) distributes hardware resources such as a processor and a memory on a physical computer.
By performing the simulation, a plurality of virtual computers are realized on one physical computer. A control program that manages a physical computer and implements a virtual computer system in this manner is called a host. A program running on the virtual machine is called a guest.

[0003] The user program runs on the guest, and in order to operate the guest efficiently, the processing time and overhead required for the control program processing are reduced, and hardware processing is performed to the guest program as much as possible. It is desirable to allocate resources. However, in the conventional method, the running of the host program and the running of the guest program are processed in a time-division manner on an arbitrary physical processor, and there is basically no distinction between the hardware resources of the host and the guest. Is shared between the host and guest. For this reason, during a certain period of time, a program processed on the physical processor may be occupied and used only by the host program, and from the guest program side, the response time of the program including the processing time may be the guest program. Response time. In this case, if the resource occupancy time of the host is short, this is not a problem.However, if the host is executing a task with a long execution time, or a host such as a maintenance command that is not directly related to the guest, such as performance measurement or trace collection. If an event that requires time for processing occurs, a problem arises because the actual processing time of the guest increases. As a document related to this type of technology, there is, for example, Japanese Patent Application No. 10-9055, “Method of Changing Architecture of Information Processing Apparatus”.

[0004]

As described above, in the conventional method in which the host and the guest share the operating processor resources, the real time required for the guest program processing increases as the time required for the host program to occupy the resources increases. The problem of an increase and a decrease in processing capacity as seen from the guest occurs is practically unavoidable. An object of the present invention is to increase the guest allocation rate of processor resources to improve processing efficiency.

[0005]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a virtual computer which comprises a physical computer having a plurality of physical instruction processors, and uses the plurality of physical instruction processors by dividing them logically. In a virtual machine system having a processor, at least one of the plurality of physical instruction processors is a physical instruction processor dedicated to processing a control program (host program) of the virtual machine system.

When the virtual computer system has a standby physical instruction processor, the standby physical instruction processor is a physical instruction processor dedicated to processing a control program (host program) of the virtual computer system. Like that.

Further, a task queue in which only the tasks executed by the control program are queued is provided in the storage device of the virtual machine system.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining the configuration of a computer system according to an embodiment of the present invention in relation to a physical computer and a virtual computer. FIG. 1 shows task assignment of a virtual computer system to a physical instruction processor in a physical computer. In FIG. 1, reference numeral 1 denotes a first instruction processor (physical processor), and reference numeral 2 denotes a second instruction processor (physical instruction processor). Although the first and second instruction processors (physical processors) are shown, the number of instruction processors (physical processors) may be one. Reference numeral 3 denotes a third processor, which is a control program processor (physical instruction processor). When a failure occurs in the instruction processor (physical processor) in addition to the instruction processor (physical processor), if there is a standby instruction processor (physical processor) that is invisible to the user to be switched and used, The standby instruction processor (physical processor) may be used as the control program processor (physical instruction processor) as the third processor. Each processor of the first instruction processor 1, the second instruction processor 2, and the third control program processor is, in FIG.
The numbers # 1, # 2, and # 3 are stored therein. 16 is a console and 4 is a common memory. The common memory 4 can be accessed from any of the first instruction processor 1, the second instruction processor 2, and the third control program processor 3. Console 16
Is a display input / output device serving as a user interface between the operator and the virtual computer 14.

The virtual machine 14 has a first instruction processor 1 (instruction processor #) which is a physical instruction processor.
1) Monitor task 11 and frame task 1 operating on
3 and a logical partition (LPAR # 1) task 5 are generated. Further, it operates on the first instruction processor 1 of the physical instruction processor, and operates in the logical partition (L
By generating a virtual instruction processor (LIP # 1.1) task 7 operating under the control of the PAR # 1) task 5, one virtual machine is configured and the system is operated. Also, if necessary, the first instruction processor 1
A virtual instruction processor (LIP # 1.2) task 8 operating under control of a logical partition (LPAR # 1) task 5 operating on (instruction processor # 1) is generated, and the first or second physical instruction processor is executed. 2 instruction processors (instruction processor # 1 or instruction processor #
2) work on

The virtual machine 14 has a second instruction processor 2 (instruction processor #) which is a physical instruction processor.
2) A monitor task 12 and a logical partition (LPAR # 2) task 6 operating on the above are generated. Also, the virtual instruction processor (LIP #) operates on the second instruction processor 2 of the physical instruction processor and operates under the control of the logical partition (LPAR # 2) task 6.
2.1) By generating the task 9, one virtual machine is configured and the system is operated. If necessary, the second instruction processor 2 (instruction processor #
2) Logical partition operating on (LPAR #)
2) A virtual instruction processor (LIP # 2.2) task 10 operating under the control of task 6 is generated, and the first or second instruction processor (instruction processor # 1 or instruction processor # 2) of the physical instruction processor is generated. Works on.

A control program processor (# 3)
A monitor task 17 operating on the processor, a dump task 18 operating on the control program processor with priority over other processors, and the like are generated. The monitor tasks are generated and operated one by one on each processor. The frame tasks in the instruction processor 2 and the control program processor 3 are not shown.

The common memory 4 operates on an arbitrary physical instruction processor and a control program processor other than a specific virtual instruction processor (LIP) task determined to operate on a specific processor. A first task queue 19 (task queue # 1) for queuing a task for processing the host program is provided. The physical instruction processor 1 (instruction processor #
1) There is provided a second task queue 20 (task queue # 2) for queuing a task that operates only on the top and mainly performs processing of a guest program. Further, a third task queue 21 (task queue # 3) that operates only on the physical instruction processor 2 (instruction processor # 2) and queues a task that mainly performs processing of a guest program is provided. The physical instruction processor 1 (instruction processor #
1) and physical instruction processor 2 (instruction processor #)
A fourth task queue 22 (task queue # 4) that operates on an arbitrary physical instruction processor of 2) and queues mainly a task for processing a guest program is provided. Thus, each task queue for queuing a task operating on the physical instruction processor is provided corresponding to each physical instruction processor and control program processor. A monitor task operating on each processor refers to these queues to perform task processing, so that each processor performs its own task processing and performs system operation.

FIG. 2 is a block diagram showing a system configuration of the virtual machine. In FIG. 2, reference numeral 31 denotes a monitor section, and the monitor section 21 has a task management function, an interrupt handler mechanism, a timer control function, and a macro control function. Reference numerals 36, 37, 38, and 39 denote virtual processor sections. These virtual instruction processor (hereinafter abbreviated as LIP) sections have an instruction emulator function and an interrupt simulator function.
Reference numerals 32 and 33 denote logical partition sections. The logical partition (hereinafter abbreviated as LPAR) section has a LIP control function for controlling a virtual instruction processor. LIP sections 36 and 37 (LIP # 1.1, # 1.
2) is controlled by the LPAR section 32 (LPAR # 1) and LIP sections 38 and 39 (LIP # 2.
1, # 2.2) is the LPAR section 33 (LPAR #
Controlled by 2). Operating system is L
One can operate for each PAR. Reference numeral 34 denotes a frame section, which is a console (16; FIG. 1).
And has an input / output function for inputting / outputting commands and data from an operator via the interface. Reference numeral 35 denotes a dump section, which has a function of collecting a trace. Since the processing function of each section is executed by task processing, data communication between the sections can communicate commands and data inside the virtual machine using the inter-task communication function. Here, the fact that the host program and the guest program are being executed by the processor is referred to as being dispatched.

A process of allocating the processing of the guest program to the instruction processor and the processing of the host program to the processor for the control program for the instruction processor and the control program processor in the above system will be described.
FIG. 3 is a task queue reference diagram when dispatching tasks of each instruction processor and control program processor. In an actual system, it is natural that more queues may be referred to depending on the processing capability of the processor. However, reference to queues of processors other than FIG. A host task queue (53) in which a host task is queued in the common memory, and a fixed guest task queue # 1 (54) in which a guest task operating only on the instruction processor # 1 (51) is queued. , Instruction processor # 2 (5
2) Fixed guest task queue # 2 (55) in which guest tasks operating only on the queue are queued, instruction processor # 1 (51), and instruction processor # 2 (5).
2) There is a floating guest task queue (56) in which guest tasks operable on any of the instruction processors are queued.

Control program processor # 3 (50)
Dispatches tasks in the host task queue mainly, and the instruction processor # 1 (51) dispatches the fixed guest task queue # 1 (54) and the floating guest task queue (5).
6) The tasks in the host task queue 53 are dispatched only when there are no tasks to be dispatched in those queues.
Similarly, the instruction processor # 2 (52) has a fixed guest task queue # 2 (55) and a floating guest task queue (5).
6) The tasks in the host task queue (53) are dispatched mainly when there are no tasks to be dispatched in those queues. By operating as described above, the processing of the host program (processing of the control program) and the processing of the guest program can be distributed to the control program processor and each instruction processor.

As an example of processing, an operation when a trace collection request is received from the console 16 while a guest program is being executed will be described. The description will be made with reference to FIG. It is assumed that the guest program runs on the physical instruction processor 1 (instruction processor # 1) and the physical instruction processor 2 (instruction processor # 2), and the control program processor 3 is currently in a wait state waiting for a task. First, when a trace collection request is input from the console 16 by a user, an interrupt occurs, and the interrupt is notified to one of the physical processors.
A monitor task running on that physical processor receives the interrupt and dispatches a frame task on that processor. Here, it is assumed that the physical instruction processor receiving the interrupt is the physical instruction processor 1 (instruction processor # 1) in FIG. Upon receiving the interrupt, the physical instruction processor 1 (instruction processor # 1) suspends the execution of the guest and dispatches the monitor task 11. The dispatched monitor task 11 dispatches the frame task 13, and the frame task 13 analyzes a command input to the console, and notifies the monitor task 11 that the command is a trace collection request. The monitor task 11 enqueues the dump task in the first task queue 19 (task queue # 1), dispatches the interrupted guest program again, and continues the processing of the guest program.

FIG. 4 is an operation flowchart of the control program processing processor. The monitor task 17 operating on the control program processing processor 3 preferentially searches the task queue 19 (task queue # 1) to perform task processing mainly on the control program. The monitor task 17 searches the task queue 19 (task queue # 1) for the dump task 18 enqueued in the previous monitor task 11 (102; FIG. 4), and the dump task is stored in the task queue 19 (task queue # 1). Enqueue is found at step 103 in FIG. If there is no task to be dispatched, the search of the task queue 19 is started again. In this case, the dump task 18 to be dispatched is set to the task queue 19 in step 103 in FIG.
(Task queue # 1), so that the dump task 18 which is a task for collecting a trace is dispatched, and the subsequent processing is performed on a processor dedicated to the control program, so that the processing for collecting the trace is interrupted in the execution of the guest program. This can be done without increasing the time overhead. When all processes of the dump task have been completed, the task queue 19 (task queue # 1) is again executed.
Start searching for.

[0018]

As described above, by providing the processor dedicated to processing the control program of the present invention, the control program is processed by the processor for processing the control program and the guest program is processed by the ordinary instruction processor between the control program and the guest program. The processing can be distinguished by performing the processing, and the waiting time generated due to the competition of the processor resources between the control program and the guest program can be reduced, and the allocation time of the processor resources to the guest program can be increased. Can be. In addition, since the control program processing processor performs execution of the dump task that collects traces that take time to process, it is not necessary to execute the time-consuming dump task with an ordinary instruction processor. No more waiting.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a computer system according to an embodiment of the present invention in relation to a physical computer and a virtual computer.

FIG. 2 is a block diagram of a functional configuration showing a system configuration of a virtual machine.

FIG. 3 is a diagram illustrating a relationship between each processor and a task queue when each processor refers to a queue for searching for a task to be dispatched;

FIG. 4 is a flowchart showing a flow of an operation process of a control program processing processor.

[Explanation of symbols]

1,50 First instruction processor (physical instruction processor) 2,51 Second instruction processor (physical instruction processor) 3,52 Control program processor (physical instruction processor) 4,57 Common memory 5,6 LPAR (logical partition) ) Tasks 7 to 10 LIP (Virtual Instruction Processor) Tasks 11, 12, 17 Monitor Tasks 13 Frame Tasks 16 Console 18 Dump Tasks 19 to 22, 53 to 56 Task Queues 14 Virtual Computers 15 Physical Computers

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hideaki Amano 1st Horiyamashita, Hadano-shi, Kanagawa F-term, General-purpose Computer Division, Hitachi, Ltd. 5B045 EE29 GG02 GG09 5B098 AA10 BA03 BB05 EE06 GA04 GA07 GB13 GC16 GD02 GD14 HH01 HH04

Claims (3)

[Claims] 1. A virtual computer system comprising: a physical computer having a plurality of physical instruction processors; and a virtual instruction processor which logically divides and uses the plurality of physical instruction processors. Wherein at least one physical instruction processor is a physical instruction processor dedicated to processing a control program (host program) of the virtual computer system. 2. The virtual computer system according to claim 1, wherein when the virtual computer system has a standby physical instruction processor, the standby physical instruction processor is controlled by a control program (host program) of the virtual computer system. A virtual computer system characterized in that it is a physical instruction processor dedicated to the processing of (1). 3. The virtual computer system according to claim 1, wherein the storage device of the virtual computer system includes a task queue in which only tasks executed by the control program are queued. Virtual computer system.