JP2000208632A - Design method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize a circuit area by assuming clock tree synthesis for optimization of clock signal timing skew at an arrangement/wiring process, for optimizing a logic circuit in a logical synthesization process. SOLUTION: In a logical synthesis, a clock driver 13 connected to a clock terminal of a flip flop 10 is limited. An output terminal 12 of the clock driver 13 is allowed to connect only to an input terminal 14 of the clock driver 13 and the clock terminal of the flip flop 10. The number of block blocks allowed to be connected and a circuit area for the output terminal of the clock driver 13 is defined to be identical with the fan out number of the clock driver 13 used in a clock tree synthesis performed in an arrangement/wiring process. Thus, such gate level circuit as a circuit area is equal to a gate level circuit is synthesized with an optimum circuit area at logical synthesis.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is based on the assumption that clock tree synthesis for optimizing the timing skew of a clock signal is performed in a placement and routing process, and that a semiconductor integrated circuit that can optimize a logic circuit in a logic synthesis process is provided. It relates to a circuit design method.

[0002]

2. Description of the Related Art Conventionally, a large number of flip-flops are arranged and wired together with other logic elements in a semiconductor integrated circuit to constitute a logic circuit. The flip-flop has a clock input terminal, and operates in synchronization with a clock signal, whereby the entire circuit functions. The logical relationship between the signals is that the clock signal in every flip-flop is
It is designed to operate at the same time within the required accuracy range.

A clock signal for synchronizing a large number of flip-flops is externally supplied from a clock terminal of an integrated circuit, and is branched and input to each flip-flop via a clock driver. At this time, the number of flip-flops that can be driven by one clock driver is generally much smaller than the number of flip-flops of the entire circuit. Therefore, in order to supply a clock signal to the flip-flops of the entire circuit, a clock signal network (hereinafter, referred to as a clock tree) formed by a large number of clock drivers is formed, and the clock signal is transmitted through the clock tree. It must be supplied to each flip-flop.

Conventionally, in a placement and routing step for applying a clock signal to all flip-flops at the same time via the clock tree, the clock tree is arranged in consideration of the layout of the flip-flops and the wiring length of the clock wiring connected thereto. A configuration technique (hereinafter referred to as clock tree synthesis) has been adopted.

[0005] However, conventional clock tree synthesis processes a gate level circuit generated by logic synthesis. Therefore, in clock tree synthesis in logic synthesis, it is difficult to consider a clock tree reconfigured in clock tree synthesis in the next placement and routing step. That is, in such conventional logic synthesis, it is not possible to predict the circuit scale including the clock tree finally determined by the clock tree synthesis, so that the circuit area cannot be optimized as a result. Was.

Here, as a first example of a specific prior art, Japanese Patent Application Laid-Open No. 6-251104 discloses a solution to the above problem.

In the first example of the prior art, it is proposed that clock tree synthesis be performed in a logic synthesis step by referring to the result of functional simulation during logic synthesis.

However, in order to guarantee the same time of the clock signal supplied to the flip-flop, the length of the wiring connected to the flip-flop is greatly affected. In this case, the wiring length cannot be calculated accurately, so that there is a problem that it is practically impossible to construct a highly accurate clock tree by the above-described method.

Furthermore, in the design of a semiconductor integrated circuit using the logic synthesis technique, the optimization of the timing skew of the clock signal connected to the sequential circuit cannot be considered at the time of logic synthesis, so that the area of the clock tree circuit is reduced. There was also a problem that the synthesis could not be performed correctly, and as a result, the chip area could not be optimized.

The reason is that the timing of the clock signal
It is necessary to optimize the skew with a placement wavy tool at the time of placement and wiring of a circuit. This is because the timing skew is greatly affected by the length of the wiring connecting the circuits,
This is because it is necessary to optimize based on actual placement and routing data. Although the circuit is arranged and wired for the gate level circuit, in the design of a semiconductor integrated circuit using logic synthesis, the gate level circuit is generated by logic synthesis. Therefore, the timing at the time of placement and routing during logic synthesis
This is because it is difficult to properly consider skew optimization.

Further, as a second example of the prior art for the purpose of optimizing the clock skew, Japanese Patent Application Laid-Open No. 2-13491 is disclosed.
There is one disclosed in Japanese Patent Application Laid-Open Publication No. 9-No.

In the second example of the prior art, an LSI
Input the external use of a clock distribution circuit composed of LSI clock phase definition data defining the clock phase used by the LSI and the flip-flop clock phase definition data used by each flip-flop in the LSI. The above object is achieved by distributing clocks equally to a plurality of regions in an LSI, generating clock distribution logic for distributing a clock signal to flip-flop groups in each region unit, and outputting the clock distribution logic. are doing.

A third example of the prior art for optimizing clock skew is disclosed in Japanese Patent Laid-Open No. 10-12455.
There is an apparatus disclosed in Japanese Patent Publication No.

In the third example of the prior art, a plurality of registers and a combinational circuit are interconnected, a clock pulse is supplied to a clock input terminal of each register via a plurality of clock buffers, and the value of each register is Is a method of generating a clock tree in a synchronous logic circuit that changes in synchronization with a clock pulse externally input via a clock buffer, according to a delay time of a combinational circuit existing between registers constituting the logic circuit. In order to achieve the above object, a clock tree generation method of classifying registers and selecting an output of a clock buffer for supplying a clock pulse to each register based on the classified registers and the cycle time of the clock pulse is adopted. I have.

As a fourth example of the prior art for the purpose of optimizing clock skew, Japanese Patent Laid-Open No.
There is one disclosed in Japanese Patent No. 9287.

A fourth example of this prior art is a method of designing, using a computer, a clock supply system in a semiconductor integrated circuit operated in synchronization with a clock signal, wherein a virtual clock for supplying a clock signal to a logically designed circuit is provided. A first process of generating a net from an output terminal of the virtual clock buffer to an input terminal of a clock signal supply destination, assuming a buffer; and replacing the virtual clock buffer in accordance with a specified delay value of the virtual clock buffer. A second process of generating a clock distribution circuit for specifying a clock supply path assuming at least a single clock buffer, and determining a budget value as a delay value in each net of the clock supply path defined by the clock distribution circuit; According to the logic design circuit and the clock distribution circuit. A third process of placing the circuit cells Te,
Fourth processing for minimizing the spread of the clock distribution circuit for each clock buffer at the same level when the circuit cell is arranged, and corresponding to the net corresponding to each net of the clock distribution circuit when the circuit cell is arranged. In order to adapt the delay value of the net to the budget value, a fifth process of changing the arrangement of circuit elements of the net is a layout design method for a clock supply system.

However, the second and third prior arts described above.
In each of the four examples, the circuit area is optimized at the gate level, that is, at the placement and routing step, and the circuit area cannot be optimized at the language level, that is, at the time of logic synthesis.

[0018]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and assumes that a clock tree is optimized in a subsequent placement and routing step at the time of logic synthesis. An object of the present invention is to provide a semiconductor integrated circuit design method that achieves optimization.

[0019]

In order to achieve this invention, the invention according to claim 1 assumes that a clock tree synthesis for optimizing a timing skew of a clock signal is performed in a placement and routing step. It is characterized in that the logic circuit is optimized during the synthesis process.

According to a second aspect of the present invention, in the first aspect of the present invention, in the logic synthesizing step, a clock driver connectable to a clock terminal of a flip-flop in the logic circuit is limited, and an output terminal of the clock driver is connected. It is characterized in that it can be connected only to a clock terminal of a flip-flop or an input terminal of another clock driver.

According to a third aspect of the present invention, in the second aspect, the connection in the logic synthesis step has the same area as the clock driver used in the clock tree synthesis in the placement and routing step, and has the same number of fan-outs. It is characterized in that it is defined to be connected to a flip-flop.

According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, the placement and routing step includes the steps of:
The clock driver in the logic circuit generated in the logic synthesis step is replaced with a logically equivalent single buffer.

According to a fifth aspect of the present invention, in the invention according to any one of the first to fourth aspects, the placement and routing step includes the steps of:
The clock driver in the logic circuit generated in the logic synthesis step is replaced with a plurality of logically equivalent buffers.

According to a sixth aspect of the present invention, in designing an application-specific integrated circuit using logic synthesis, a clock driver connectable to a clock terminal of a flip-flop is limited, and an output terminal of the block driver is connected to a clock of a flip-flop. A clock tree composed of a large number of clock drivers that supply clock signals to flip-flops of the entire circuit in the placement and routing process, defining a terminal or an input terminal of another clock driver as being connectable only, The number of fan-outs of the clock driver used in so-called clock tree synthesis, which reconfigures the clock signal to reach all flip-flops at the same time, taking into account the wiring length of the clock signal connected to the Of clock driver in Number Power terminals connectable block or define equivalently the number of fan-out, characterized in that logic synthesis.

According to a seventh aspect of the present invention, the clock tree circuit of the gate level circuit generated by the logic synthesis is extracted and replaced with a logically equivalent buffer. It is characterized by performing clock tree synthesis.

That is, according to the present invention, it is assumed that clock tree synthesis for optimizing the timing skew of a clock signal is performed in the placement and routing step, and the circuit area can be optimized during logic synthesis. The following design method has been devised.

First, in the logic synthesizing step, a buffer (hereinafter, referred to as a clock driver) connectable to a clock terminal of a flip-flop is limited, and an output terminal of the clock driver is connected to a clock terminal of a flip-flop or another terminal. Can be connected only to the input terminal of the clock driver. In addition, the number of output terminal connectable blocks (hereinafter referred to as the number of fan-outs) and the circuit area of the clock driver are made the same as the number of fan-outs of the clock driver used in the clock tree synthesis executed in the placement and routing process. Define. Logic synthesis is executed under the above conditions.

Second, the logic synthesizing step of extracting the connection of the clock driver in the gate level circuit generated by the above logic synthesis from the net list of the gate level circuit and replacing it with a logically equivalent single buffer is described. Set later. This single buffer is subjected to clock tree synthesis in the placement and routing process.

The following effects can be obtained by the means described above. By the first means, the circuit area of the clock driver forming the clock tree at the time of logic synthesis becomes equivalent to the circuit area after executing the clock tree synthesis in the placement and routing step.

After that, the second means makes it possible to use the conventional clock tree synthesis in the placement and routing step of the gate level circuit generated by the logic synthesis using the means 1. Therefore, by the above two means, the timing skew of the clock signal is optimized at the time of placement and routing, so that even when executing clock tree synthesis, it is possible to optimize the circuit area at the time of logic synthesis.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the method for designing a semiconductor integrated circuit according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a flow chart showing an operation example of a semiconductor integrated circuit designing method according to an embodiment of the present invention. After an integrated circuit to be designed is described by a function description circuit (step S1), a gate level circuit is generated by clock driver limited logic synthesis (step S2) (step S3). The clock driver limited logic synthesis in step S2 synthesizes the gate level circuit in step S3, which is equivalent in area to the clock tree reconfigured by the placement and wiring including the clock tree synthesis in step S8 to be executed later, by the operation described later. I do.

That is, in the clock driver limited logic synthesis step of step S2, optimization of the circuit area including the area of the clock tree circuit reconstructed by the clock tree synthesis of step S8 can be equivalently executed. Becomes

Here, the gate level circuit in step S3 includes a clock tree circuit. However, since this circuit configuration does not take the placement and routing information into consideration, the timing skew of the clock signal is not changed and the placement and routing process is performed as it is. Is not optimized. Therefore, it is necessary to execute clock tree synthesis in the placement and routing process. In order to execute clock tree synthesis in the placement and routing step, it is necessary to replace the single tree buffer to be subjected to clock tree synthesis with the placement and routing step based on the clock tree formed by logic synthesis. The step of performing this replacement is the clock tree buffer replacement step of step S4. Here, the buffer to be replaced in the placement and routing step is not limited to a single buffer, but may be a plurality of buffers as long as they are logically equivalent.

In the clock tree replacement step of step S4, the clock tree circuit included in the gate level circuit of step S3 is replaced with a single buffer to be the target of the clock tree by the operation described later in step S5.
Is generated (step S2). Hereinafter, an integrated circuit is designed using a normal design flow for the gate level circuit (step S2) in step S5. In the present embodiment, the placement and routing step including the circuit verification and the clock tree synthesis in step S6 corresponds to this.

FIG. 2 is an image diagram of the gate level circuit 1 generated by the clock driver limited logic synthesis in the embodiment described above.

The clock tree circuit constituted by the clock driver 13 defining the number of fan-outs and the circuit area equivalent to the clock driver 15 used in the clock tree synthesis executed in the placement and routing step is a clock tree in the placement and routing step. It is equivalent in area to a clock tree reconstructed by synthesis.

That is, in logic synthesis, the clock driver 13 connected to the clock terminal of the flip-flop 10
And the output terminal 12 of the clock driver 13 can be connected only to the input terminal 14 of the clock driver 13 and the clock terminal of the flip-flop 10, so that the gate formed by clock tree synthesis in the subsequent placement and routing process A gate level circuit equivalent in circuit area to a level circuit can be synthesized with an optimum circuit area during logic synthesis.

FIG. 3 is an image diagram of the gate level circuit 2 generated by replacing the clock buffer in the embodiment described above.

The clock tree circuit constituted by the limited clock driver 13 in the gate level circuit 1 of FIG. 2 is replaced with a clock driver 15 for clock tree synthesis. This makes it possible to execute clock tree synthesis in a subsequent placement and routing process.

[0041]

As is apparent from the above description, according to the present invention, in the design of an application specific integrated circuit (ASIC), when a gate level circuit is generated by using logic synthesis, a subsequent placement and routing step is performed. In the case where the timing skew of the clock signal is optimized using the clock tree synthesis in the above, the circuit area including the clock tree circuit can be optimized in the logic synthesis step.

The reason is that, in the logic synthesis, by limiting the clock driver, it is possible to optimize a clock tree circuit reconfigured by clock tree synthesis in placement and routing and a clock tree circuit having an equivalent circuit area. This is because

[Brief description of the drawings]

FIG. 1 is a flowchart showing an operation example of a semiconductor integrated circuit designing method according to an embodiment of the present invention.

FIG. 2 is an image diagram of a gate level circuit 1 generated by clock driver limited logic synthesis according to the embodiment of the present invention.

FIG. 3 is an image diagram of a gate level circuit 2 generated by replacing a clock buffer according to the embodiment of the present invention.

[Explanation of symbols]

 9 Input terminal 10 Flip-flop 11 Combination circuit 12 Output terminal 13 Limited clock driver 14 Clock input terminal 15 Clock driver for clock tree synthesis

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA04 5B079 CC14 DD08 DD12 DD13 5F038 CA04 CD06 CD09 CD20 DF01 EZ20 5F064 AA03 BB19 BB26 DD03 DD25 DD32 EE03 EE16 EE47 EE54 EE60 HH10

Claims (7)

[Claims] 1. A method of designing a semiconductor integrated circuit, wherein a logic circuit is optimized in a logic synthesis step, assuming that clock tree synthesis for optimizing a timing skew of a clock signal is performed in a placement and routing step. 2. The logic synthesizing step, wherein a clock driver connectable to a clock terminal of a flip-flop in the logic circuit is limited, and an output terminal of the clock driver is connected to a clock terminal of the flip-flop or another clock driver. 2. The method according to claim 1, wherein only the input terminal is connectable. 3. The connection in the logic synthesis step is defined so as to have the same area as the clock driver used in the clock tree synthesis in the placement and routing step and to be connected to the flip-flop with the same number of fan-outs. 3. The method for designing a semiconductor integrated circuit according to claim 2, wherein: 4. The placement and routing step according to claim 1, wherein the clock driver in the logic circuit generated in the logic synthesis step is replaced with a logically equivalent single buffer. 3. The method for designing a semiconductor integrated circuit according to item 1. 5. The placement and routing step according to claim 1, wherein the clock driver in the logic circuit generated in the logic synthesis step is replaced with a plurality of logically equivalent buffers. 13. The method for designing a semiconductor integrated circuit according to the above item. 6. In a design of an application specific integrated circuit using logic synthesis, a clock driver connectable to a clock terminal of a flip-flop is limited, and an output terminal of the clock driver is set to a clock terminal of a flip-flop or another clock. A clock tree that is defined as connectable only to the input terminal of the driver and that is composed of a large number of clock drivers that supply clock signals to flip-flops of the entire circuit in the placement and routing process, The number of fan-outs of a clock driver used in so-called clock tree synthesis for reconfiguring a clock signal to reach all flip-flops at the same time in consideration of the wiring length, and the output of the clock driver during the logic synthesis Terminal connectable block A method for designing a semiconductor integrated circuit, wherein the number of locks, that is, the number of fanouts is equivalently defined and logically synthesized. 7. The clock tree circuit of a gate level circuit generated by the logic synthesis is extracted and replaced with a logically equivalent buffer, and clock tree synthesis is performed in the placement and routing step. The semiconductor integrated circuit design method according to the above.