JP2000207233A - Multi-thread processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make available a hardware scheduling function and a software scheduling function both. SOLUTION: Thread execution units 10-0 to 10-3 have machine-word instruction, which enable a thread in process to generate a new thread and a thread in process to end. Furthermore, the processor is equipped with a function of directly assigning the new thread by hardware, a function of instructing whether or not the assignment by the hardware is performed by the hardware, a function of holding the register context of a thread generated, when the assignment by the hardware is not performed, and a function of restoring the held register context on the thread execution units 10-0 to 10-3, when the thread in process ends; and the thread execution units 10-0 to 10-3 process the new thread generated by the thread in process by themselves as need after the thread ends in processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-thread microprocessor for executing a plurality of instructions in an information processing apparatus at the same time, and more particularly to a multi-thread processor characterized by an execution scheduling technique for a plurality of threads.

[0002]

2. Description of the Related Art As a technique for executing a single program at high speed, there is a technique for dividing a program into a plurality of threads (instruction streams) and performing parallel processing at the thread level.
Also, in the technical field, by realizing basic processes such as thread generation, thread allocation and execution to processor execution resources, and termination and deletion of a thread at a machine language instruction level, even a thread with a finer granularity can achieve high speed. A scheme aimed at execution has been proposed.

[0003] As this kind of prior art, for example, a document “Multiscalar Processor”
(GS Sohi, SE Breach and
T. N. Vijaykumar, The 22nd I
international Symposium on
Computer Architecture, IE
EEComputer Society Press,
1995, p. 414-425) and the document "On-Chip Multiprocess."
or Oriented Control Parallel Architecture MUSCAT "
(Torii, Kondo, Motomura, Konagaya, Nishi, Parallel Processing Symposium JSPP97 Transactions, Information Processing Society of Japan, pp.229-
236, May 1997).

According to the techniques disclosed in these documents, a basic block in a program written in a programming language such as the C language or a macro basic block in which some basic blocks are collectively viewed are parallelized. It is possible to increase the processing speed, and the processing speed can be increased even with a very small program granularity (on the order of μsec).

The major features of fine-grained thread execution methods such as Multiscalar and MUSCAT are hardware scheduling for high-speed thread generation and allocation to execution resources, and registers for enabling high-speed data transfer between threads. There is content inheritance. As a conventional technique relating to hardware scheduling of a thread, there is a thread execution method disclosed in, for example, Japanese Patent Application Laid-Open No. 10-27108. As a technique relating to the inheritance of register contents, there is a patent application (Japanese Patent Application No. 10-117666) filed by the present applicant. These techniques enable a high-speed execution by dividing a program based on a sequential order execution model into fine-grained programs and executing them in parallel. In addition, the technique is also directed to automatically dividing a thread of a program by a compiler.

In addition, in the technology related to thread parallel execution, there is a parallel programming model which explicitly describes parallelism as a programming model, in addition to the technology for supporting multi-thread in the processor hardware as described above. . There have been many attempts to use an SMP type multiprocessor to actually perform parallel execution. For example, a document “Implementation of a weighing process mechanism with excellent portability on BSD UNIX” (Abe, Matsuura, Taniguchi, Transactions of Information Processing Society of Japan, Vol. 36,
No. 2, pp. 296-303, Feb. 199
5. As described in (1), research using a user-level library scheduler has been actively conducted to realize a lighter and faster software thread as far as possible in software technology.

[0007] When comparing hardware-based scheduling and software-based scheduling for parallel execution of a plurality of threads in these conventional technologies, one advantage and disadvantage are the other advantage and disadvantage.

[0008] That is, the advantage of the hardware approach is that it can be accelerated by parallel processing even if the parallel processing granularity is very small. On the other hand, disadvantages are that the number of threads that can be scheduled is strongly limited because the hardware directly manages and stores, and scheduling by hardware often does not always achieve the performance characteristics desired by software. Lack of flexibility.

On the other hand, the software approach has an advantage that the number of manageable threads can be made much larger than that of the hardware approach, and a GUI (Graphics User Interface) can be used.
rface) High applicability to an event-driven programming style often used in program and communication transaction processing, and a scheduling method can be individually tuned and flexibly adjusted to characteristics required individually for each target application. Is high. Another disadvantage is that if the parallel processing granularity is small, the overhead becomes large, and it is difficult to increase the speed.

That is, since the hardware approach and the software approach have the property of complementing each other, it is desirable that both functions can be operated in a mixed manner and that any of the approaches can be freely used in combination.

Next, a problem concerning the execution of a mixed program of hardware scheduling and software scheduling will be described in more detail. FIG. 20 to FIG. 22 are conceptual diagrams illustrating the problem of parallelization granularity and scheduling using six parallel-processable jobs (T0 to T5 threads) on the order of msec as an example.

[0012] FIG. 20 shows that the original msec-order work is generated and executed in the order of thread T0 → thread T1 →.
This shows the scheduling when hardware scheduling is performed in ar or MUSCAT. Here, in order to enable high-speed thread generation and allocation to execution resources, a thread execution unit (PE # 0
In the period from to PE # 3), a new thread can be generated and executed only in the direction indicated by the direction ring. Therefore, when the thread T3 executing the PE # 3 attempts to generate a new thread T4, the T4 starts after the PE # 0 completes the execution of the T0. For this reason, PE # 1 and PE # 2, which end earlier than T0 and are in an idle state, such as T1 and T2, are not effectively utilized, resulting in wasted time. Whether this problem can be solved is actually closely related to thread granularity. In other words, if the idle time of PE # 1 or PE # 2 is on the order of μsec, it is difficult to utilize this idle time, but the idle time is ms.
If the order is equal to or more than the ec order, the software scheduling can perform scheduling better.

FIG. 21 shows a case where scheduling is performed using a user-level library scheduler by software scheduling. If the software scheduler is used, the PE in the idle state can transfer control to the library scheduler and search for the next thread to be executed. As a result, the PE # 1 and PE # 2 can start executing T4 and T5 immediately after the end of T1 and T2, respectively. Therefore, it is possible to shorten the entire end time as compared with FIG. However, in the state of FIG. 21, the PEs # 0, # 1, and # 3 wait in an idle state until the processing of the PE # 2, which has ultimately performed the execution of T5, ends. There is an inefficient aspect.

Therefore, based on the problem presented with reference to FIGS. 20 and 21, an execution example in which hardware scheduling and software scheduling are mixed is shown in FIG.
It is shown in FIG. In FIG. 22, each of the tasks T0 to T5 is originally parallelized using the user-level scheduler in the unit thereof, and is defined as the first-level parallelism. And, as the parallelization of the second hierarchy, a program is assumed in which the inside of T0 to T5 is parallelized so as to be processed by the hardware scheduler. That is, as shown in FIG. 22, the last T5 under treatment is the other PE # 0, # 1, # 3.
When the system becomes idle, parallel processing is performed at a hardware scheduling level in a small-granular form, thereby further increasing the speed.

However, in order to perform the processing shown in FIG. 22, the inside of T0 to T5 is made parallelizable at the hardware level, and another PE is provided to the program.
Is empty, the other PE is used, and the other PE is used.
If is currently being used by software scheduling, it is necessary to control a new thread that is to be started at the hardware level so that it can be serialized and processed on its own PE on the time axis.

[0016]

As described above, conventional thread execution methods in a multi-thread processor include hardware scheduling and software scheduling. Since both approaches have contradictory advantages and disadvantages, it is desirable to mix both functions and operate them freely.

However, in order to perform such an operation,
It has been necessary to make the inside of a plurality of threads parallel at the hardware level, and to implement control in each thread execution unit to select a processing method of a program according to the use status of another thread execution unit.

An object of the present invention is to solve the above-mentioned conventional problems, and realize that, in parallel execution of a plurality of threads, a hardware scheduling function and a software scheduling function are mixed and operated freely. To provide a multi-thread processor.

[0019]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention comprises a plurality of program counters, and a plurality of threads for simultaneously fetching, interpreting, and executing instructions of a plurality of threads according to the plurality of program counters. In a multi-thread processor having an execution unit,
A machine instruction for enabling the thread executing unit to execute a new thread at most once and a machine instruction for enabling the thread being executed to terminate in any thread execution unit Further, a thread allocation means for directly performing, in hardware, a process of allocating a new thread generated based on the machine language instruction to a thread execution unit other than the thread execution unit executing the machine language instruction, In a case where a thread being processed in any of the thread execution units executes a machine instruction for generating a new thread, the thread execution for executing the machine instruction on a new thread generated based on the machine instruction. The process assigned to the thread execution unit of the unit A thread assignment instructing means for instructing whether or not the means is to be performed by software; and the machine language instruction when the thread assignment instructing means instructs the thread assigning means not to execute the thread assignment. Register context holding means for storing and holding a register context required for the start of execution of a new thread generated based on a thread execution unit for executing the machine language instruction. And a thread execution end instruction execution detecting means for detecting that the thread has been executed, and a machine language instruction for terminating a thread being processed in any of the thread execution units. To start execution of the thread to be created A register context restoring means for restoring a required register context on the thread execution unit, wherein a thread being processed in any of the thread execution units generates a new thread if necessary. The thread execution unit processes a new thread generated when executing a machine language instruction for performing the following after the thread being processed on the thread execution unit ends.

According to another aspect of the present invention, there is provided a thread execution unit comprising a plurality of program counters, wherein the plurality of thread execution units simultaneously fetch, interpret, and execute instructions of a plurality of threads according to the plurality of program counters. In the multi-threaded processor provided with the above, the thread execution unit terminates the thread being processed in a machine instruction that enables the thread being processed to generate a new thread at most once and any thread execution unit. A shared physical register file comprising a plurality of physical registers shared by the plurality of thread execution units, and one of the logics in the thread execution unit provided in the plurality of thread execution units. Registers and specific in the shared physical register file A conversion table defining a mapping relationship with one of the plurality of physical registers; and a conversion table information copying means for copying information of the conversion tables of the plurality of thread execution units to adjacent thread execution units. Grouping a plurality of physical registers for which a mapping relationship is defined with one of the logical registers, and adding information indicating a position in the group to information of the conversion table to define the mapping relationship Thus, when a thread being processed in any of the thread execution units executes a machine language instruction for generating a new thread, a register content inheritance device that performs inheritance of the register content is generated based on the machine language instruction. Assigns a new thread to a thread execution unit of the thread execution unit that executes the machine instruction. Thread assignment means for instructing, by software, whether or not the thread assignment means performs the thread assignment process, and the thread assignment instruction means instructing the thread assignment means not to execute the thread assignment. A register context holding unit for storing and holding a register context required to start execution of a new thread generated based on the machine language instruction; and a thread being processed in the thread execution unit executing the machine language instruction A thread execution end instruction execution detecting means for detecting execution of a thread execution end instruction, and a register context holding means for executing a machine language instruction for terminating a thread being processed in any of the thread execution units. Freshly held by Register context restoration means for restoring, on the thread execution unit, a register context required for the start of execution of a thread to be formed. Wherein the thread execution unit processes a new thread generated when the thread of the thread executes a machine language instruction for generating a new thread, after the thread being processed on the thread execution unit ends. I do.

In another aspect, in any one of the above-mentioned inventions, the register context holding means is a memory area on a main memory of the thread execution unit, and is generated by software processing using an instruction trap. Storing the register context of a new thread.

In another aspect of the present invention, in any one of the above-mentioned inventions, the register context holding means instructs the thread assignment instructing means to not execute the thread assignment to the thread assigning means. In this case, when an attempt is made to process a machine instruction for generating a new thread, an instruction that traps an instruction address X determined in advance by hardware and executes the machine instruction for generating a new thread is executed. A register context required for starting execution of a new thread to be newly generated by a program in which an address is stored and held in a trap source instruction address register uniquely provided in the thread execution unit, and the instruction address X is an entry point. Is stored in the main memory, and the trap source instruction address is saved. The instruction of the machine language instruction for generating the new thread based on the instruction address stored and held in the register is calculated, the start instruction address of the new thread is calculated, and the calculation result is saved on the main memory. On the basis of the instruction address held in the trap source instruction address register uniquely provided in the thread execution unit, program control is restored to an instruction address subsequent to the instruction that executed the machine instruction for generating the new thread, and the thread execution is executed. When the end instruction execution detecting means has instructed the thread assignment instructing means to not execute the thread assignment to the thread assigning means,
When a thread being processed in the thread execution unit executes a thread execution end instruction, the thread traps at an instruction address Y determined in advance by hardware, and the register context recovery means uses the instruction address Y as an entry point. Thus, the register context of the new thread to be newly created and saved on the main memory is returned to the register, and the start instruction address of the new thread saved on the main memory is taken out and stored in the address. It is characterized by restoring program control.

In still another aspect, in any one of the above-mentioned inventions, the register context holding means is a set of storage devices provided for each thread execution unit for register context saving, and Storing the register context of the new thread created by the hardware sequence,
The register context restoring means directly restores the register context held in the register context saving storage device to the thread execution unit by a hardware sequence.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a multi-thread processor according to an embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration for realizing switching between hardware scheduling and software scheduling. The multi-thread processor according to the present embodiment has the configuration shown in FIG.
As shown in FIG. 2, the processor is a four-thread parallel execution type processor, and has a thread management unit 30 and four sets of thread execution units (PE # 0 to PE # 3) 10-0 to 10-3.
, A physical shared register file 20, and an execution unit status 50.

Thread execution units 10-0 to 10-3
Are the instruction caches (# 0 to # 3) 11-0, respectively.
11-3, and instruction decoders (# 0 to # 3) 12-0 to
12-3 and a register mapping table (# 0 to # 3) 13
−0 to 13-3 and arithmetic unit (# 0 to # 3) 14−
0 to 14-3 and selectors 15-0 to 15-3. Also, the register mapping tables 13-0 to 13-3
Are connected to adjacent register mapping tables so as to form a ring by a mapping information transfer bus 40, respectively.

The execution unit status 50 indicates each thread execution unit (PE # 0 to PE # 3) 10-0 to 10
-3 and the instruction units 12-0 to 12-3 and the physical shared register file 20 to calculate the operation units 14-0 to 14-1.
Selectors 15-0 to 15-3 for selecting a bus for connecting data and commands to 4-3 or a bus for returning execution results to the physical shared register 20 from the operation units 14-0 to 14-3
5-3.

FIG. 1 shows only the characteristic configuration of the present embodiment, and the description of other general configurations is omitted. For example, it goes without saying that a processor requires a load store unit, a data cache memory, an external interface, and the like in addition to the above configuration. In the following description, the thread execution units 10-0 to 10-3 and the thread execution units 10-
Instruction cache 11-0, which is a component of 0-10-3
To 11-3, instruction decoders 12-0 to 12-3, register mapping tables 13-0 to 13-3, arithmetic unit 14
In the case of −0 to 14-3 and the selectors 15-0 to 15-3, when it is not particularly necessary to distinguish individual components,
The suffixes of the reference numerals are omitted as appropriate, and, for example, the thread execution unit 10, the instruction cache 11, and the instruction decoder 12 are described.

The multi-thread processor according to the present embodiment has a machine language instruction that enables a thread being processed in an arbitrary thread execution unit to generate a new thread, and a thread being processed in an arbitrary thread execution unit is terminated. The thread being processed in any thread execution unit generates a new thread at most once, and in the processing of the machine language instruction for generating a new thread, the It is assumed that there is provided a register content inheritance means realized by hardware that directly controls a new thread generated based on the thread execution unit other than the thread execution unit.
The thread management unit 30, the thread execution units 10-0 to 10-3, and the physical shared register file 20 implement a register content inheritance unit. Therefore,
First, means for inheriting the contents of the register will be described.

FIG. 12 shows the thread execution unit 1 of FIG.
It is a figure which shows the pipeline stages of 0-0 to 10-3. Referring to FIG. 12, the thread execution unit 10-
In the pipeline stages 0 to 10-3, the instruction fetch stage 1201, the instruction decode stage 12
02, register conversion stage 1203, execution stage 1
The execution is completed through five stages of 204 and a register write back stage 1205.

FIG. 13 is a diagram showing a detailed configuration of the physical shared register file 20 of FIG. Referring to FIG. 13, the physical register file 20 stores the logical register number 2
The number of physical registers 201 is twice as large as the number of thread execution units 10-0 to 10-3 for every 02. Therefore, in this embodiment, 8 bits are assigned to one logical register.
Physical registers 201 are associated with each other. Each physical register 201 has two bits A and B of the group selection bit 203.
Into two groups 204 and 205, each having physical extension bits 206 corresponding to the number of thread execution units 10-0 to 10-3.

FIG. 14 is a diagram showing a format of the physical register 201 of FIG. Referring to FIG. 14, in the case of an instruction set having 32 logical register sets, the physical register 201 includes a physical extension bit 206, a group selection bit 203, and a logical register number 202. In this case, when the number of logical register sets changes, the number of bits indicating the logical register number 202 changes, and when the number of thread execution units 10-0 to 10-3 changes, the value of the physical extension bit 206 changes.

FIG. 15 shows the register mapping table 1 of FIG.
FIG. 3 is a diagram showing a detailed configuration of No. 3; Referring to FIG.
The register mapping table 13 has a logical register number 202
Each is divided into groups A and B selected by the group selection bit 1501, and each includes a physical extension bit 1503, a change bit 1504, a write-back bit 1505, an inheritance group selection bit 1502, and a group selection change instruction And an incomplete bit 1506. The group selection bit 1501 indicates a group of the physical shared register file 20 referred to by the thread execution units 10-0 to 10-3.
1 is referred to. The change bit 1504 is
It indicates whether or not the instruction for updating the physical register 201 selected by the group selection bit 1501 has been decoded one or more times by the thread execution units 10-0 to 10-3. The write-back bit 1505 indicates whether or not one or more instructions that have updated the physical register 201 have actually been completed. The inheritance group selection bit 1502 is
Registers are stored in the corresponding thread execution units 10-0 to 10-
3 is a copy of the contents of the group selection bit 1501 at the time when the thread selection units are inherited from the thread execution units 10-0 to 10-3.

FIG. 16 shows the register mapping table 1 of FIG.
FIG. 3 is a diagram showing a detailed configuration of one entry of No. 3; Referring to FIG. 16, the register mapping table 13 includes adders 1601a and 1601b, multiplexers 1602a to 1602d, and write operation logic 1603 in addition to the bits shown in FIG.

The group selection bit 1501 indicates the fork in the one-fork one-time model, that is, after the thread has been generated, the relevant thread execution unit 10-0 to 10-0
This is set when the register value is changed for the first time by the instruction of 10-3. The determination as to whether or not the first rewrite after the fork is performed by taking an exclusive logical loop of the values of the group selection bit 1501 and the inheritance group selection bit 1502. Since the inheritance group selection bit 1502 holds a copy of the group selection bit 1501 at the time of thread creation, this determination can be made.

Also, change bits 1504a, 1504b
Is reset when the thread starts. afterwards,
The instruction for changing the register value is sent to the instruction decoder 12-0.
Group selection bit 1 when received from
Change bits 1504a, 1 on the side selected at 501
504b is set.

Write-back bits 1505a, 1505b
Is reset when the thread is started, and is set when the actual calculation result calculated by the arithmetic unit 14 is written back to the physical shared register file 20. As a result, the physical register number is extended to the logical register according to the following reference policy.

First, at the time of calling reference, the multiplexer 1
602a and 1602b are change bits 1504a and 15
04b is reset, the physical extension bit 1
Adders 1601a and 1601a are added to the values of 503a and 1503b.
The value added by 01b is output. Physical extension bit 1
By adding 1 to the values of 503a and 1503b,
In the physical shared register file 20 used by the non-selection side, the occurrence of register conflict is prevented. Prevention of register conflicts is used when changes are made in the own unit on the non-selected side.Therefore, make sure that the preceding unit and the own unit or the own unit and the subsequent unit do not use the same register. Can be realized.

The multiplexer 1602c selects, based on the group selection bit 1501, either the value of the group A or the value of the group B and outputs it as the physical extension bit 206 for reference. On the other hand, as for the physical extension bit 206 for write reference, it is necessary to always output a value obtained by adding 1 to the physical extension bits 1503a and 1503b regardless of whether the group A or the group B is selected.

Therefore, the input to the multiplexer 1602d is obtained from the physical extension bits 1503a and 1503b of either the A group or the B group.
01a and 1601b are used. The selection of the A group or the B group basically depends on the value of the group selection bit 1501.
When switching 1, the group of the switching destination is selected first. This control is performed by the write operation logic 160.
3 is performed. Also, the physical extension bit 1503
a and 1503b are returned to 0 when the digits prepared by the addition overflow. Further, at the time of thread generation, the group selection bit 1501 and the multiplexer 1602
a, physical extension bit 1503 output from 1602b
a and 1503b are copied via the register mapping table 13 at the thread creation destination.

Hereinafter, a normal register reference operation after thread activation, an operation at thread creation, and a register reference operation after thread creation will be described in chronological order. The following description is mainly of the operation performed by register conversion stage 1203 in FIG.

FIG. 17 shows a group selection bit 1501 and physical extension bits 1503a and 1503 during normal operation.
b, transition of the values of the change bits 1504a and 1504b,
FIG. 4 is a diagram illustrating a mechanism that can realize register inheritance. Note that the write-back bits 1505a, 1505
The operation of 5b will be described later.

In the thread execution unit (# 0) 10-0, when the new thread is started (A), the group selection bit 1501 is "A", the physical extension bits 1503a and 1503b are 0, Bit 1
504a and 1504b are 0. In this case, the logical register is the physical register 201 located at 0 of “A”.
Is read and referenced.

When a write reference occurs, that is, at the time of register change (b), the change bit 1504 of "A"
a is set to 1. The change is performed on the physical register 201 located at 1 of “A”, and the subsequent read reference is also performed on the same register. Thereafter, even if a write reference to the same register occurs, the group selection bit 1501 and the change bits 1504a and 1504b are not changed.

Next, at the point of time when a new thread is created (C), the group selection bit 1501 is "A", so "A" is set, and the change bit 1504a is set on the selection side. Since the bit 1504b is the non-selection side, a value obtained by adding 1 to the value of the physical extension bits 1503a and 1503b is transmitted to the register mapping table 13-1 of the thread execution unit (# 1) 10-1.

When the thread execution unit (# 0) 10-0 performs register write reference for the first time after thread creation, that is, (d), the group selection bit 1
501 is changed from “A” to “B” and the change bit 150 is changed.
4b is set. The change is performed on the physical register 201 located at 1 of “B”, and the subsequent read reference is also performed on the same register. Thereafter, even if a write reference to the same register occurs, the group selection bit 1501 and the change bits 1504a and 1504b are not changed. Thereby, the thread execution unit (# 1) 1
Registers that may be referenced by 0-1 are “A” 0
Is held at the position.

In the thread execution unit (# 1) 10-1, (e)
A new thread is created at the time. Therefore, the value of the physical extension bit 1503a of “A” on the group selection side is transmitted as it is. Therefore, the contents of the register of the thread executing in the thread execution unit (# 0) 10-0 are directly stored in the thread execution unit (# 0).
2) Inherited by the thread executed in 10-2. At the time of (f), when the register is changed,
Since it is after forking, the group selection bit 1501 is changed from "A" to "B".

FIG. 18 shows a group selection bit 1501 and a physical extension bit 15 when speculative thread generation is involved.
03a, 1503b, change bits 1504a, 1504
FIG. 11 is a diagram for explaining a transition of a value of b and a mechanism that can realize register inheritance by the transition of the value of b. Among the operations shown in FIG. 18, (A) to (D) correspond to (A) to (D) in FIG.
Operation is the same as

At time (e) in FIG. 17, the thread execution unit (# 0) 10-0 cancels the generation of the thread generated at time (c). Further, a thread is generated again at the time of (f). Group selection bit 150
Since 1 is "B", "B" is set, and the change bit 1504a "A" is set on the selection side.
Is the non-selection side, so the physical extension bits 1503a, 1503a
The value obtained by adding 1 to the value of 3b is the thread execution unit (#
1) Transmit to the register table 13-1 of 10-1. As a result, the value changed at the time (d)
It is inherited by the thread executed by the thread execution unit (# 1) 10-1. If the register is changed again at (g), the group selection bit 1501 is returned to "A" again.

FIG. 19 is a diagram showing the timing of copying the mapping information in the operation of the pipeline shown in FIG. Referring to FIG. 19, the copy of the register mapping information is performed by executing the thread generation instruction in the register conversion stage (FIG. 19).
In cycle 5), the thread execution unit (#
0) Register inheritance information is transmitted from 10-0, and is written to the register mapping table 13-1 of the thread execution unit (# 1) 10-1 in cycle 6. In the cycle 7, the normal instruction E accesses the inherited register with reference to the register mapping table 13-1. The thread execution unit 10 at the thread creation destination
If −0 to 10−3 are executing another thread and cannot receive a new thread creation request, the inheritance group selection bit 15
A value of 02 may be transmitted instead of the group selection bit 1501.

Next, write-back bits 1505a, 1505
The operation of 5b will be described. Writeback bit 1505
“a” and “1505b” are caused by an instruction that writes and refers to a register for some reason (for example, prediction failure of a conditional branch instruction).
Change bits 1504a, 1
Used to restore 504b to the correct value.

Write-back bits 1505a, 1505b
Is the group selection bit 1501 when the thread is started.
Has been reset by The reset write-back bits 1505a and 1505b are
4 is set when the actual calculation result calculated by 4 is written back to the physical shared register file 20. That is, the fact that the change bits 1504a and 1504b are set and the write-back bits 1505a and 1505b are not set indicates that the change bit 15
It means that the instruction which set 04a, 1504b is not completed. Therefore, if an instruction cancellation event occurs at this stage, the write-back bit 1505a,
Change the contents of 1505b bits 1504a, 1504b
To restore the register mapping table 13 to the correct value when the instruction is canceled.

Further, the group selection change instruction incomplete bit 1506 is reset when the thread is started, is set when the instruction to change the group selection bit 1501 reaches the register conversion stage 1203, and reaches the register write back stage 1205. Reset when done. That is, while the group selection change instruction incomplete bit 1506 is set, the instruction to change the group selection bit 1501 is not completed.
If an instruction is canceled in this state, the group selection bit 1501 is inverted corresponding to the set group selection change instruction incomplete bit 1506. Thereafter, the group selection change command incomplete bit 1506 is reset.

According to the method described above, the inheritance of registers can be realized without copying the actual contents of the registers and using only the physical shared register file 20 as a shared resource. At the time of inheritance, only 1 is added to each physical extension bit 206, and these mechanisms can be realized by having two sets of register groups corresponding to the number of thread execution units 10-0 to 10-3. It is.

Next, a description will be given of an embodiment of the present invention for realizing switching between hardware scheduling and software scheduling in a processor device using the above-described register content inheriting device.

In the present embodiment, as shown in FIG. 1, a thread management unit 3 for realizing means for inheriting register contents is provided.
0, a configuration comprising the thread execution units 10-0 to 10-3 and the physical shared register file 20, additional logic is added to the instruction decoders 12-0 to 12-3, and an execution unit status 50 is further provided. The execution unit status 50 indicates that when a thread being processed in an arbitrary thread execution unit attempts to process a machine instruction for generating a new thread, a new thread to be generated based on the request of the instruction is The present invention enables software to instruct whether hardware should directly perform processing to be assigned to a thread execution unit other than the thread execution unit.

FIG. 2 is a circuit diagram showing the internal structure of execution unit status 50 in FIG. Referring to FIG. 2, the execution unit status 50 includes thread execution unit statuses # 0 to # 3 (21-0 to 21-3).
And NOR logic gates (22-0 to 22-3), selectors (23-0 to 23-3) for selecting a status write destination from each thread execution unit, and status reading from each thread execution unit Selectors (24-0 to 24-3) for selecting entries.

FIG. 3 shows the instruction decoder 12- in FIG.
FIG. 3 is a circuit diagram showing an internal structure of 0-12-3. Referring to FIG. 3, instruction decoders 12-0 to 12-3 include an instruction decoder circuit 25 having a function corresponding to an instruction decoder function in a processor device using the above-described register content inheritance means, an AND gate 26, and an inverter. 2
7, a set / reset flip-flop 28.

The association of the functions added to the instruction decoder circuit 25 with the entire functions will be described later, and the circuit operation will be described here.

When the instruction decode circuit 25 finds a new thread generation instruction in a machine language to be hardware-scheduled in the instruction sequence being executed,
Based on the instruction from the D gate 26, it is determined whether or not to trap to the instruction address X, and the operation is performed. When the output of the AND gate takes the value "0", a trap operation to the instruction address X occurs, and when the output value of the AND gate 26 is "1", the trap to the instruction address X does not occur and hardware scheduling is performed directly. Perform a new thread creation operation. If the instruction decode circuit 25 determines that the instruction address X should be trapped, the instruction decode circuit 25
Performs a set operation on the set / reset flip-flop 28 and sets the value of the flip-flop 28 to “1”.

When the instruction decoding circuit 25 finds a thread end instruction in a machine language to be hardware-scheduled in an instruction sequence being executed,
Based on the instruction of the ND gate 26, the operation is performed by determining whether or not to trap to the instruction address Y. When the output of the AND gate takes the value "0", a trap operation to the instruction address Y occurs, and the output value of the AND gate 26 becomes "1".
In the case of, the thread generation end operation is directly performed by hardware scheduling without causing a trap to the instruction address Y. If the instruction decode circuit 25 determines that the instruction address X should be trapped, the instruction decode circuit 25
Performs a reset operation on the set / reset flip-flop 28 and sets the value of the flip-flop 28 to “0”.

The output of the set / reset flip-flop 28 is connected to the AND gate 26 via the inverter 27. When these circuits once perform the operation of trapping a new thread generation instruction based on a certain machine language instruction at the address X, the instruction decoder circuit 25 again finds a thread end instruction that is paired with the machine language instruction. ,
Instruct to always trap to address Y. In addition,
The set / reset flip-flop 28 is set to a value “0” when the processor is initialized.

The additional circuit added to the instruction decoder circuit 25 shown in FIG.
In the combination with the above, it is detected that the thread being processed in the predetermined thread execution units 10-0 to 10-3 has executed the thread execution end instruction.

Next, the structure of a program for realizing mixed execution of software scheduling and hardware scheduling shown in FIG. 22 will be described with reference to the flowcharts of FIGS.

FIG. 4 is a flowchart showing an operation relating to the mixed execution of software scheduling and hardware scheduling in the initialization of a user program which is started up from the OS or the like and starts operating.

Referring to the program shown in FIG. 4 as a part related to the execution, first, it is assumed that threads T1 to T5 managed by the software scheduler are generated, and the thread T0 is the P which initializes the program.
It is assumed that E starts executing itself as it is after the initialization is completed (steps 401 and 402). Thread T1
Generation of T5 is performed by calling a thread generation routine in a dynamically or statically linked user-level thread library when creating an execution load module of the user program. The change of the “thread execution status” described in step 401 is a process related to controlling the availability of hardware scheduling from the software side, and the status of the thread execution units # 0 to # 3 in FIG. This is a process of updating the status of one of the thread execution units that is to be activated under software scheduling from among 21-0 to 21-3).

In FIG. 2, thread execution unit #i
When the status value is “0”, it means “the thread execution unit #i is unusable by hardware scheduling”, and when the thread execution unit #i status is the value “1”, it means “thread execution unit #i”. #I
Indicates a state that can be used in software scheduling. Therefore, step 4 in FIG.
The “set the“ thread execution status ”of the PE to the user-level execution” performed in step 01 indicates that the thread execution unit status of FIG.
Is set.

In this updating process, in FIG. 1, data and commands are sent to the execution unit status 50 from PE # j which is performing the thread generation process, and the target value of the thread execution unit status of #i in FIG. It is to update. This is because the selectors 23-0 to 23-0
This is possible by controlling any one of 23-3, and its implementation is apparent to a technician having very general hardware design knowledge, and thus the description is omitted.

FIGS. 5 to 7 are flowcharts showing the software structure of the user-level thread library.

This user-level thread library must not be called from a parallel execution environment under hardware scheduling. In a parallel processing execution environment under hardware scheduling, it is always called after only one thread execution unit is in the execution state. In a program constituting the threads T0 to T5, it is possible to adopt a program configuration in which, when a user-level thread library is called, only one thread execution unit is executed before calling. Also, means for ensuring that only one thread execution unit becomes an execution state in hardware under the instruction of software is disclosed in, for example, Japanese Patent Publication No. 10-27108, "Thread Execution Method". Here, the detailed description is omitted.

FIG. 5 shows a thread generation routine. After registering thread information to be generated when called (step 502), the routine shown in FIG. 5 checks whether there is a waiting thread execution unit, and if there is a waiting thread execution unit, One of them is selected and activated to execute the dispatcher (step 503). Whether or not the thread execution unit is on standby can be managed by software by providing a flag area in a memory area used by the library when starting or terminating the thread execution unit in the library scheduler. is there.

In the "thread generation processing", if a plurality of thread execution units perform processing at the same time, destruction of data that can be accessed only exclusively occurs. Therefore, the thread generation routine shown in FIG. 5 secures and releases the lock of the scheduler in steps 501 and 504, thereby guaranteeing that it operates exclusively for calls from each thread execution unit. Need to be kept.

FIG. 6 shows a thread termination routine. The routine shown in FIG. 6 also needs to be executed exclusively between thread execution units. Therefore, when called, after securing the scheduler lock (step 6
01), as the thread end processing, the information of the end thread is deleted from the thread information managed by the library (step 602). Further, the thread termination routine shown in FIG. 6 does not need to return execution control to the user thread managed by the software that has completed the processing, and therefore has a structure in which control is passed to the dispatcher in order to obtain a new thread to be executed as it is. Has become.

FIG. 7 shows the processing of the dispatcher.
Also in the process shown in FIG. 7, it is necessary to execute exclusively between thread execution units. Therefore, when called, the scheduler lock is first secured (step 7).
01). Then, by referring to the thread management information, it is checked whether there is any executable user-level thread that has not been processed yet (step 702). If there is a thread to be executed, the thread information is extracted (step 702). 703) The process shifts to the thread from which control has been extracted to be executed by the own thread execution unit.

On the other hand, when there is no thread to be executed, it is necessary to reach a waiting state. Specifically, the thread execution unit that is about to enter the standby state determines whether there is more than one other thread execution unit in operation (step 705). If the number is more than one, the scheduler is unlocked (step 706), and the "thread execution status" of the own thread execution unit is set so that hardware scheduling can be performed. (Step 70
7).

If the remaining thread execution unit becomes one due to its own thread execution unit being in the standby state, the “thread execution status” of the last remaining thread execution unit is set by hardware scheduling. A process for setting to be possible is additionally performed (step 708).

The operations in steps 705 to 708 mean that if only one thread execution unit is in the operating state, the two thread execution units that are already in the standby state are under hardware scheduling. The purpose of the present invention is to convey that a total of three thread execution units may be used, including one thread execution unit and one thread execution unit that is about to enter a waiting state.

The result of the processing in steps 705 to 708 is
By executing steps 708 and 707, all the flags of the thread execution unit status in FIG. 2 become “0” and are transmitted to the hardware. How the hardware interprets and operates the result of the above processing will be described later in terms of the overall operation.

Next, referring to FIGS. 1, 2 and 3, and the flowcharts of FIGS. 8 and 9, when the software gives an instruction that the hardware should not directly allocate a new thread, Means for storing and holding a register context required to start execution of a new thread to be created based on the thread creation request;
A description will be given of a means for enabling the held register context necessary for starting execution of a thread to be newly generated to be restored on the thread execution unit.

First, in the processing described in FIGS. 8 and 9, execution of a thread generation instruction based on hardware scheduling is started in each thread execution unit while each thread execution unit is operating under software scheduling. It is a flowchart explaining the operation | movement which respond | corresponds to a case. The determination as to whether or not the processing described in FIGS. 8 and 9 is activated is performed as follows.

First, the outputs of the NOR gates 22-0 to 22-3 change depending on whether the value of the thread execution unit #i status in FIG. 2 is "0" or "1". The outputs of the NOR gates 22-0 to 22-3 are, when viewed from the predetermined thread execution unit #i, the thread execution units #j of the other thread execution units.
(J is other than i) If the status is a value "0", that is, if a thread execution unit other than itself is in a state in which hardware scheduling is possible, a value "1" is taken, otherwise. In this case, the value is "0".

The outputs of the NOR gates 22-0 to 22-3 are connected to an instruction decode circuit 25 of each thread execution unit via an AND gate 26 as shown in FIG. Since the set / reset flip-flop 28 has the initial value “0”, this value is AND-inverted.
Gate 26 transmits the outputs of NOR gates 22-0 to 22-3 in a running state.

Therefore, if the output of the connected NOR gates 22-0 to 22-3 of FIG. 2 is "0", the instruction decode circuit 25 of each thread execution unit When a thread generation instruction of a machine language instruction that directly performs hardware scheduling is found, it is interpreted that serialization must be performed, and trapped at an instruction address X determined in advance by hardware.

On the other hand, NOR gates 22-0 to 22 input to instruction decode circuit 25 of each thread execution unit
If the output of -3 is "1", this is shown in the prior art when a thread generation instruction of a machine language instruction that directly performs hardware scheduling is found in the instruction sequence to be executed by itself. A new thread is generated and executed by the adjacent descending thread execution unit as described above.

Also, when each thread execution unit finds a thread end instruction of a machine language instruction that directly performs hardware scheduling in an instruction sequence to be executed by itself, the NOR gates 22-0 to 22-0 in FIG. 22
-3 behaves similarly, but for the thread termination instruction, the circuit of FIG. 3 also plays an additional role.

That is, if the outputs of the connected NOR gates 22-0 to 22-3 of FIG. 2 are "0", the instruction decode circuit 25 of each thread execution unit
When a thread end instruction of a machine language instruction for directly performing hardware scheduling is found in an instruction sequence to be executed, the instruction is trapped at an instruction address Y determined in advance by hardware. On the other hand, NOR input to the instruction decoder 12 of each thread execution unit
If the output of the gates 22-0 to 22-3 is "1", when a thread end instruction of a machine instruction for directly performing hardware scheduling is found in the instruction sequence to be executed, As described in the art, the basic operation is to end the thread execution directly and to attain the waiting state.

However, when the thread generation instruction processed before finding the thread end instruction is serialized by the operation of the additional circuit in FIG. NOR gate 22-0
The outputs of .about.22-3 are masked by the AND gate 26 in FIG.

With respect to the mechanism of trapping at the address X or the address Y when the processor attempts to execute the thread generation of the machine language instruction or the execution of the end instruction, conventionally, an instruction which is complicated to be realized by the wired logic is replaced by a software. Alternatively, since it is known as a technique of emulating by trapping as firmware, a detailed description thereof is omitted here.

Next, with reference to FIGS. 8 and 9, the processing after trapping at the address X or the address Y will be described. FIG. 8 is a flowchart showing a process of serializing and executing thread generation started from address X.

In the processor of the present embodiment, the process of a predetermined thread execution unit generating a new thread under hardware scheduling is performed by changing the register context at the time when the fork instruction, which is an instruction for generating a new thread, appears. Inherit and create a child thread. Further, a newly created thread can generate a new thread at most once by the end thereof. When an incorrect thread is generated, the calculation model is such that the thread that has been generated incorrectly is forcibly terminated and then the thread is regenerated. Therefore, in this calculation model, when an attempt is made to execute a thread generation instruction, the register context at that time and the instruction start address of the generated thread are saved, and the processing of the thread being executed is continuously executed. After execution reaches the thread end instruction, the context of the new thread to be created that has been saved is restored to the register, and execution control is passed to the instruction start address of the new thread to be created. It is possible to serialize and execute a plurality of threads using only one thread execution unit without using the thread execution unit. It is sufficient that the save area of the context necessary for serialized execution can hold at most one thread information for each thread execution unit. Therefore, in step 802 of FIG. 8, the thread information (register context and thread start instruction address) of the hardware activation to be generated is stored in the individual memory area of each thread execution unit, and thereafter, the control is performed to the trap source address. To continue execution of the original thread.

As described above, when the software instructs that the hardware should not directly allocate a new thread, the software is required to start execution of a new thread to be generated based on the thread generation request. A means for storing and holding a register context is realized.

In the process of serializing and executing the thread generation started from the address X shown in FIG. 8, when the thread to be generated saved as a serialization process target is to be executed later, a thread end instruction is executed. A set operation for the set / reset flip-flop 28 in FIG.

Next, the processing in the case where each thread execution unit detects a thread end instruction and traps an instruction at address Y while serialization is being executed will be described with reference to FIG. As shown in FIG. 9, there are two cases of the end processing.

The first case is when the thread to be terminated is performing a new thread generation process.
In this case, the context of the new thread to be created is restored to the register, and control is transferred to the start address of the new thread (steps 902 and 903).

The second case is where the thread to be terminated has not performed a new thread generation process. In this case, the thread execution unit enters a standby state (steps 902 and 904).

As a result, a means for restoring the held register context required for starting execution of the newly created thread to be created on the thread execution unit is realized.

When a thread end instruction is detected and an instruction is trapped at the address Y while serialization is being executed, the set / reset flip-flop 28 shown in FIG. 3 is reset as additional processing.

Next, the overall operation of this embodiment will be described with reference to FIG. FIG. 10 is a diagram showing the mixed execution of software scheduling and hardware scheduling shown in FIG. 22 with finer resolution on the time axis.

In the description of the execution state of each thread execution unit, a description in which “value 1” or “value 0” is added to a line with an arrow pointing downward on the right side corresponds to the thread execution of FIG. Unit status 23-
0 to 23-3.

The flow of the program processing is as follows. First, the program initialization processing shown in FIG.
It is started by starting at E # 0. When the thread execution unit PE # 0 starts the program initialization process and performs the process of step 401, the thread execution status of the thread execution unit PE # 0 becomes the value 1 (a state usable in software scheduling). Thereby, the thread execution units PE # 1 to # 3
, The thread generated by the hardware scheduling is in a mode of serializing and executing.

The thread execution unit PE # 0, which is continuously performing the program initialization process, executes the process of step 402, executes the thread generation process of FIG. 5 five times, and executes the threads T1 to T5 to be subjected to software scheduling. Is generated, and at the time of generation of T1 to T3, the dispatcher is activated by setting the thread execution unit status of each of the thread execution units PE # 1 to # 3 to a state usable by software scheduling.

Thread execution units PE # 1 to PE # 3
Is the thread T1 to be processed via the dispatcher
~ T3, and each starts execution. After performing the processing of step 402, the thread execution unit PE # 0 starts executing the thread T0.

Here, in a state where the threads T0 to T3 are being executed in parallel, each thread to be software-scheduled proceeds while generating and deleting a thread by using a machine language instruction to be hardware-scheduled. . However, since the thread execution unit status of all thread execution units is proceeding in a state in which software scheduling is possible, when a thread generation instruction and a thread end instruction are executed by machine language instructions, these instructions are trapped, and FIG. 8 and serialized by the means described with reference to FIG. Thread T0
At the end of the processing from T3 to T3, each thread execution unit calls the thread end processing in FIG. 6 as the execution end of the thread to be software scheduled.

On the time axis, the thread T1 to be software-scheduled ends first, and then the thread T2
End, the thread execution unit PE # 1 and the thread execution unit PE # 2, which have executed them, respectively proceed to the thread end processing of FIG. 6 and the subsequent dispatcher of FIG. Execution of the threads T4 and T5 that have not been processed is started.

Next, the thread execution unit PE # 0 executing the thread T0 to be software-scheduled on the time axis reaches the execution end state, performs the thread end processing of FIG. 6, and returns to the dispatcher of FIG. Control transfers.

At this point, since there is no thread that is not assigned to a thread execution unit among the threads to be software-scheduled, the thread execution unit PE # 0 executes step 7
In step 07, the thread execution unit status of the own thread execution unit is changed to a state usable by hardware scheduling, and the thread execution unit falls into a standby state.

Next, the thread execution unit PE # 1, which was also executing the thread T4, also terminates the processing and similarly changes the thread execution unit status of its own thread execution unit to a state usable by hardware scheduling. And fall into a standby state.

Further, the thread execution unit PE # 3 executing the thread T3 ends the processing, and shifts the control to the dispatcher of FIG. Here, step 70
In the process of 5, when the own thread execution unit PE # 3 reaches the standby state, it is determined that only one PE is executing the remaining process, and the process of step 708 is performed. When the processing of step 708 is completed, the thread execution unit PE # 0 and the thread execution unit PE in the thread execution unit status of FIG.
# 1 and the thread execution unit PE # 2 indicate a state usable in executing hardware scheduling. At this point, the outputs of the NOR circuits 22-0 to 22-3 become "0", "0", "0", and "1" in this order. In the instruction decoders 12-0 to 12-3 of each thread execution unit in FIG. 1 to which the output is connected, only the thread execution unit PE # 3 can determine that the thread for which hardware scheduling is to be performed can be directly executed. Become.

On the other hand, the thread execution unit PE # 3
Since the process of step 707 is performed after the process of step 708 is performed, no thread for which hardware scheduling is to be performed is generated at this time.
However, when the process of step 707 is executed, the thread execution unit statuses 21-0 to 21-3 in FIG.
Everything indicates a state usable in hardware scheduling execution. When this state is reached, N
The outputs of the OR circuits 22-0 to 22-3 are, in order,
"1", "1", "1", "1", and all the PEs reach a state in which a thread for hardware scheduling can be executed.

The thread execution unit PE # 2 executing the thread T5 to be software-scheduled
At this point, if an attempt is made to execute a thread-scheduled machine instruction to be subjected to hardware scheduling after this point, the execution does not fall into the trap and serialize execution shown in FIG. Thus, high-speed execution is performed under hardware scheduling.

In FIG. 6, the symbol of the thread T5 is “T
The reason why a and b are added to the last character, such as “5a” and “T5b”, is that T5a is a period during which thread execution by hardware scheduling is serialized and processed, and a plurality of threads are directly executed by hardware scheduling. The period during which parallel processing is performed using the execution unit resources is described separately from T5b.

FIG. 11 is a block diagram showing a configuration for realizing switching between hardware scheduling and software scheduling in a multi-thread processor according to another embodiment of the present invention.

This embodiment The multi-thread processor of this embodiment has four processors as in the first embodiment shown in FIG.
It is a thread parallel execution type processor, and has a thread management unit 30 and four sets of thread execution units (PE # 0
-PE # 3) 10-0 to 10-3, a physical shared register file 20, and an execution unit status 50.

Thread execution units 110-0 to 110
-3 are instruction caches (# 0 to # 3) 11-0 to 11-3 and instruction decoders (# 0 to # 3), similarly to the thread execution units 10-0 to 10-3 in the first embodiment. # 3) 12-0 to 12-3, register mapping tables (# 0 to # 3) 13-0 to 13-3, operation units (# 0 to # 3) 14-0 to 14-3, selector 1
5-0 to 15-3, and the evacuation memory (# 0 to # 0)
# 3) 111-0 to 111-3 are provided. In addition, similarly to the first embodiment, the register mapping tables 13-0 to 13-0
3-3 are connected to adjacent register mapping tables so as to form a ring by a mapping information transfer bus 40, respectively.

The backup storages 111-0 to 111-3 store new threads to be created based on the thread creation request when an instruction is given in software that hardware should not directly allocate new threads. This is a means for storing and holding a register context required for the start of execution of a program, and is used to save information of a thread to be subjected to hardware scheduling.

With the provision of the backup storages 111-0 to 111-3, the present embodiment enables the machine language instruction to be subjected to hardware scheduling in a state where the thread to be hardware scheduled is serialized and executed. When executing the thread generation instruction and the thread end instruction according to the above, the software processing using the instruction trap as shown in FIG. 2 is not performed, and the standby storage 111-included in each thread execution unit is directly performed by a hardware sequence. It is possible to save and restore thread information using 0 to 111-3.

The other components and operations are the same as those of the first embodiment described with reference to FIGS. 1 to 107, and a description thereof will not be repeated.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0118]

As described above, according to the multi-thread processor of the present invention, parallel program execution with fine granularity based on hardware scheduling and flexible parallel execution scheduling using a software library scheduler are achieved. Since the programs can be mixedly executed, there is an effect that the processing time of the entire program can be reduced by efficiently executing the program.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration for realizing switching between hardware scheduling and software scheduling in a multi-thread processor according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal structure of an execution unit status in the embodiment.

FIG. 3 is a circuit diagram illustrating an internal structure of an instruction decoder of a thread execution unit according to the embodiment.

FIG. 4 is a flowchart showing an operation related to a mixed execution of software scheduling and hardware scheduling in the initialization of a user program started up and started to operate from an OS or the like.

FIG. 5 is a flowchart illustrating a software structure of a user-level thread library, and illustrates a thread generation routine.

FIG. 6 is a flowchart illustrating a software structure of a user-level thread library, illustrating a thread termination routine.

FIG. 7 is a flowchart illustrating a software structure of a user-level thread library, and is a diagram illustrating a process of a dispatcher.

FIG. 8 is a flowchart showing a thread generation operation when execution of a thread generation instruction based on hardware scheduling is started in the thread execution unit while the thread execution unit is operating under software scheduling.

FIG. 9 is a flowchart illustrating a thread termination operation when execution of a thread generation instruction based on hardware scheduling is started in the thread execution unit while the thread execution unit is operating under software scheduling.

FIG. 10 is a diagram showing mixed execution of software scheduling and hardware scheduling, with finer resolution on the time axis.

FIG. 11 is a block diagram showing a configuration for realizing switching between hardware scheduling and software scheduling in a multi-thread processor according to another embodiment of the present invention.

FIG. 12 is a diagram illustrating a pipeline stage of a thread execution unit in the embodiment of the present invention.

FIG. 13 is a diagram showing a detailed configuration of a physical shared register file in the embodiment of the present invention.

FIG. 14 is a diagram showing a format of a physical register in the embodiment of the present invention.

FIG. 15 is a diagram showing a detailed configuration of a register mapping table in the embodiment of the present invention.

FIG. 16 is a diagram showing a detailed configuration of one entry of a register mapping table according to the embodiment of the present invention.

FIG. 17 is a diagram illustrating a transition of values of a group selection bit and a physical extension bit change bit during a normal operation and a mechanism that can realize register inheritance by the embodiment according to the present invention.

FIG. 18 is a diagram for explaining a transition of values of a group selection bit, a physical extension bit, and a change bit when speculative thread generation is performed in the embodiment of the present invention, and a mechanism for realizing register inheritance thereby. It is.

FIG. 19 is a diagram showing a timing of copying mapping information in the operation of the pipeline shown in FIG. 12;

FIG. 20 is a diagram illustrating a thread execution method by hardware scheduling.

FIG. 21 is a diagram illustrating a thread execution method by software scheduling.

FIG. 22 is a diagram illustrating a thread execution method in which hardware scheduling and software scheduling are mixed.

[Explanation of symbols]

 10-0 to 10-3 Thread execution unit 11-0 to 11-3 Instruction cache 12-0 to 12-3 Instruction decoder 13-0 to 13-3 Register mapping table 14-0 to 14-3 Operation unit 15-0 ~ 15-3 Selector 20 Physical shared register file 30 Thread management unit 40 Mapping information transfer bus 50 Execution unit status

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Junji Sakai 5-7-1 Shiba, Minato-ku, Tokyo Within NEC Corporation (72) Taku Osawa 5-7-1 Shiba, Minato-ku, Tokyo Japan Inside Electric Company (72) Inventor Satoshi Matsushita 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation F-term (reference) 5B013 DD01 DD04 5B033 AA13 DD01 5B098 AA02 AA10 GA05 GC01

Claims (8)

[Claims] 1. A multi-thread processor comprising: a plurality of program counters; and a plurality of thread execution units for simultaneously fetching, interpreting, and executing instructions of a plurality of threads according to the plurality of program counters. Comprises a machine instruction that allows the thread being processed to create a new thread at most once and a machine instruction that allows the thread being processed to terminate in any thread execution unit, Thread allocation means for directly performing, by hardware, a process of allocating a new thread generated based on the machine language instruction to a thread execution unit other than the thread execution unit executing the machine language instruction, and any of the threads The thread being processed in the execution unit is new. When executing a machine instruction for generating a new thread, assigning a new thread generated based on the machine instruction to a thread execution unit of the thread execution unit executing the machine instruction. A thread assignment instructing means for instructing whether or not the means is to be performed by software; and the machine language instruction when the thread assignment instructing means instructs the thread assigning means not to execute the thread assignment. Register context holding means for storing and holding a register context required for the start of execution of a new thread generated based on: a thread being processed in the thread execution unit for executing the machine instruction terminates the thread That the machine language instruction was executed A thread execution end instruction execution detecting unit that issues a machine language instruction for terminating a thread being processed in any of the thread execution units, and a thread to be newly generated that is held by the register context holding unit. Register context restoring means for restoring, on the thread execution unit, a register context required for the start of execution, and if necessary, a thread being processed in any of the thread execution units is newly provided. A multi-thread processor, wherein the thread execution unit processes a new thread generated when executing a machine instruction for generating a new thread after the thread being processed on the thread execution unit ends. . 2. The register context holding unit according to claim 1,
The multi-thread processor according to claim 1, wherein the multi-thread processor is a memory area on a main memory of the thread execution unit and stores the register context of a new thread generated by software processing using an instruction trap. 3. A machine language instruction for generating a new thread when the register context holding unit instructs the thread allocation unit not to execute the thread allocation, when the thread allocation instruction unit instructs the thread allocation unit not to execute the thread allocation. When the thread execution unit attempts to process the instruction, the thread execution unit traps the instruction at the instruction address X determined in advance by the hardware, and the thread execution unit uniquely includes an instruction address at which the machine language instruction for generating the new thread is executed. A register context required to start execution of a new thread to be newly created is saved in the main memory by a program having the instruction address X as an entry point and stored in an address register. Based on the instruction address stored in the register Calculating a start instruction address of the new thread, saving the calculation result in a main memory, and indicating a trap source instruction uniquely provided in the thread execution unit. Based on the instruction address held in the address register,
The program control is restored to an instruction address subsequent to the instruction that has executed the machine instruction for generating the new thread, the thread execution end instruction execution detecting means includes: When the thread executing in the thread execution unit executes a thread execution end instruction, the instruction is trapped at an instruction address Y predetermined by hardware, and the register is executed. The context restoring means restores the register context of a new thread to be newly created, which has been saved on the main memory, to a register by a program having the instruction address Y as an entry point, and saves the register context on the main memory. The start instruction address of the new thread Multithreaded processor according to claim 2, characterized in that to restore the program control to the address. 4. The register context holding means,
A set of storage devices provided specifically for each thread execution unit for register context save,
The register context restoring means directly stores the register context of the new thread generated by a hardware sequence, and stores the register context held in the storage device for register context save directly by a hardware sequence. The multi-thread processor according to claim 1, wherein the multi-thread processor is restored on a thread execution unit. 5. A multi-thread processor comprising: a plurality of program counters; and a plurality of thread execution units for simultaneously fetching, interpreting, and executing instructions of a plurality of threads according to the plurality of program counters. Comprises a machine instruction for enabling the thread being processed to create a new thread at most once and a machine instruction for enabling the thread being processed to terminate in any thread execution unit, A shared physical register file that is shared by a plurality of thread execution units and includes a plurality of physical registers; one logical register provided in the plurality of thread execution units and one of the plurality of physical registers in the thread execution unit; Mapping between one of the physical registers And a conversion table information copying means for copying information of the conversion table of the plurality of thread execution units to an adjacent thread execution unit, wherein a mapping relationship is defined between one of the logical registers. Register inheritance device for inheriting register contents by grouping each of the plurality of physical registers described above and adding information indicating a position in the group to information of the conversion table to define the mapping relationship When a thread being processed in any of the thread execution units executes a machine instruction for generating a new thread, the new thread generated based on the machine instruction executes the machine instruction. The thread assignment unit assigns a process to assign a thread execution unit to a thread execution unit. Thread assignment instructing means for instructing whether or not to execute the thread assignment by software, based on the machine language instruction when the thread assignment instructing means instructs the thread assigning means not to execute the thread assignment. Register context holding means for storing and holding a register context required to start execution of a new thread to be generated; and a thread being processed in the thread execution unit executing the machine language instruction has executed a thread execution end instruction. A thread execution end instruction execution detecting means for detecting that a thread is being executed, and a machine language instruction for terminating a thread being processed in any of the thread execution units should be newly generated and held by the register context holding means. Necessary to start thread execution And a register context restoring means for restoring a register context to be executed on the thread execution unit, wherein a thread being processed in any of the thread execution units generates a new thread if necessary. A multi-thread processor wherein a new thread generated when a word instruction is executed is processed by the thread execution unit after the thread being processed on the thread execution unit ends. 6. The register context holding means,
The multi-thread processor according to claim 5, wherein the multi-thread processor is a memory area on a main memory of the thread execution unit, and stores the register context of a new thread generated by software processing using an instruction trap. 7. A machine language instruction for generating a new thread when the register context holding means has instructed the thread allocation means not to execute the thread allocation when the thread allocation instructing means has performed the instruction. When the thread execution unit attempts to process the instruction, the thread execution unit traps the instruction at the instruction address X determined in advance by the hardware, and the thread execution unit uniquely includes an instruction address at which the machine language instruction for generating the new thread is executed. A register context required to start execution of a new thread to be newly created is saved in the main memory by a program having the instruction address X as an entry point and stored in an address register. Based on the instruction address stored in the register Calculating a start instruction address of the new thread, saving the calculation result in a main memory, and indicating a trap source instruction uniquely provided in the thread execution unit. Based on the instruction address held in the address register,
The program control is restored to an instruction address subsequent to the instruction that has executed the machine instruction for generating the new thread, the thread execution end instruction execution detecting means includes: When the thread executing in the thread execution unit executes a thread execution end instruction, the instruction is trapped at an instruction address Y predetermined by hardware, and the register is executed. The context restoring means restores the register context of a new thread to be newly created, which has been saved on the main memory, to a register by a program having the instruction address Y as an entry point, and saves the register context on the main memory. The start instruction address of the new thread Multithreaded processor according to claim 6, characterized in that to restore the program control to the address. 8. The register context holding means,
A set of storage devices provided specifically for each thread execution unit for register context save,
The register context restoring means directly stores the register context of the new thread generated by a hardware sequence, and stores the register context held in the storage device for register context save directly by a hardware sequence. The multi-thread processor according to claim 5, wherein the multi-thread processor is restored on a thread execution unit.