JP2000188828A - Capacitor discharge circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor discharge circuit which does not generate losses, when a prescribed voltage is applied to a load, and can quickly turn an output voltage of a DC power source to 0 V when a power source switch is cut off. SOLUTION: When supply of input is stopped to a DC power source 1, wherein a smoothing capacitor C1 is installed in a path of DC output 111, charges stored in the capacitor C1 are discharged. This capacitor discharge circuit is equipped with a voltage-detecting circuit 2 for detecting whether the voltage of the DC output 111 becomes lower than a preset voltage, and a discharging circuit 3 for discharging for charges of the capacitor C1, when the voltage detecting circuit 2 detects decrease of the voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor discharge circuit for discharging electric charges stored in a smoothing capacitor provided in a DC power supply, and more particularly, to a method for detecting a decrease in the output voltage of the DC power supply. The present invention relates to a capacitor discharging circuit for discharging a charge of a smoothing capacitor.

[0002]

2. Description of the Related Art A rectifying and smoothing circuit is indispensable for a DC power supply that obtains a DC output stabilized at a predetermined voltage. For this reason, even when the power switch is turned off, since the charge is stored in the smoothing capacitor, a situation may occur in which the voltage of the DC output does not drop to 0V. In order to solve such inconvenience, as shown in FIG. 5, a conventional technique of connecting a discharging resistor 62 in parallel to a smoothing capacitor 61 and discharging the charge of the smoothing capacitor 61 until the voltage becomes 0 V is known. Proposed (this is the first
Of the prior art).

FIG. 6 shows a conventional technique proposed as Japanese Patent Laid-Open No. 4-38122. That is, in this technique, when the power switch is turned on and a DC voltage is supplied between the terminals a and b, charges are gradually stored in the capacitor 31 and the voltage of the inverting input of the comparator 33 increases. When the voltage of the inverting input becomes higher than the voltage divided by the resistor 27 and the resistor 28, the comparator 3
The output of No. 3 is at the L level (the output is on), the relay coil 41 is driven, and the contact rl is closed. Therefore,
The DC voltage is supplied to the load when a predetermined time has elapsed after the DC voltage is supplied between the terminals a and b.

On the other hand, when the power switch is turned off, the following operation is performed. That is, when the voltage of the DC voltage supplied between the terminals a and b decreases, the divided voltage applied to the non-inverting input of the comparator 39 becomes lower than the reference voltage applied to the inverting input. Therefore, the output of the comparator 39 becomes L level (the output is turned on), and the electric charge of the capacitor 31 is discharged. As a result, the level of the inverting input of the comparator 33 becomes lower than the level of the non-inverting input, so that the output of the comparator 33 becomes H level (the output is off). Accordingly, the driving of the relay coil 41 is stopped, and the connection of the contact rl is opened. Also, the capacitor 43
Is discharged, and the capacitor 43 is reset.

That is, the comparator 39 operates as a discharge circuit for discharging the electric charge of the capacitor 31. Therefore, after the power switch is turned off and the voltage value of the DC voltage supplied between the terminals a and b decreases to a voltage value that sets the output of the comparator 39 to the L level, a predetermined delay operation can be performed. It has become.

The operation of the terminal d is as follows. That is, the reference voltage e is applied to the inverting input of the comparator 37 via a time constant circuit including the resistor 44 and the capacitor 43, and the resistors 24 to 26 are applied to the non-inverting input.
A divided voltage of a voltage dividing circuit composed of For this reason, the terminal d becomes an output terminal indicating a decrease in the voltage of the DC output supplied between the terminals a and b (this is referred to as a second conventional technique).

[0007]

However, when the above technique is used, the following problems have occurred. That is, in the first related art, when the power switch is turned on, a current always flows through the discharge resistor 62. For this reason,
When the value of the current flowing through the discharge resistor 62 is increased, the loss increases. On the other hand, in order to reduce the loss, the discharge resistor 6
When the value of the current flowing through the capacitor 2 is reduced,
The time for discharging one charge becomes longer. That is,
It has been difficult to discharge the charge of the smoothing capacitor 61 in a short time without increasing the loss.

The comparator 39 of the second prior art merely discharges the charge of the capacitor 31 for setting the delay time when the power switch is turned off. Therefore, even when the power switch is turned off,
The charge of the smoothing capacitor (not shown) in the DC power supply connected between the terminals a and b is not discharged. For this reason, it has been difficult to reduce the DC voltage supplied to the load to 0 V when the power switch is turned off.

The reference voltage e is different from the voltage supplied between the terminals a and b. Therefore, the reference voltage e
Requires a DC power supply to generate the circuit, which leads to a complicated circuit. Further, even if a malfunction occurs in the DC power supply that generates the reference voltage e, the predetermined operation cannot be performed. That is, since a DC power supply for generating the reference voltage e must be used, the reliability of the device is reduced correspondingly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for controlling the power supply of a DC power supply when the output voltage of the DC power supply decreases with the disconnection of a power supply switch. By discharging the charge of the smoothing capacitor, no loss occurs when the predetermined voltage is supplied to the load, and when the power switch is turned off,
An object of the present invention is to provide a capacitor discharge circuit capable of rapidly reducing the output voltage of a DC power supply to 0V.

It is another object of the present invention to provide a capacitor discharge circuit which can eliminate the need for a voltage source different from a DC voltage supplied to a load.

A third object of the present invention is to provide a capacitor discharge circuit capable of easily setting a discharge current value while suppressing a maximum value of a current for discharging a capacitor. It is in.

[0013]

According to a first aspect of the present invention, there is provided a capacitor discharging circuit in which the supply of an input to a DC power supply having a smoothing capacitor provided in a DC output path is stopped. Sometimes, the voltage detection circuit is applied to a capacitor discharge circuit that discharges the electric charge stored in the smoothing capacitor, and detects whether the voltage of the DC output has dropped below a preset voltage, and the voltage detection circuit. Has a charge discharging circuit that discharges the charge of the smoothing capacitor when detecting a drop in voltage.

That is, when the DC power supply supplies a predetermined voltage to the load, the voltage detection circuit does not detect a voltage drop. Therefore, no current flows through the charge discharging circuit. on the other hand,
When the power switch is turned off, the voltage detecting circuit detects a drop in voltage, so that the charge discharging circuit discharges the charge of the smoothing capacitor.

According to a second aspect of the present invention, in addition to the above configuration, when the one terminal of the DC output is at a power supply level and the other terminal of the DC output is at a ground level, The discharge circuit has a first switch circuit having one terminal connected to the power supply level, one terminal connected to the other terminal of the first switch circuit, and the other terminal connected to the ground level. A voltage holding capacitor, a second switch circuit having one terminal connected to one terminal of the voltage holding capacitor,
A discharge current circuit, wherein a control input is connected to the other terminal of the second switch circuit, and when a voltage is applied to the control input, a discharge current circuit closing a connection between the pair of terminals is provided. When the voltage detection circuit does not detect a drop in voltage, the connection of the first switch circuit is closed and the connection of the second switch circuit is connected. When the voltage detection circuit detects a voltage drop, the connection of the first switch circuit is opened and the connection of the second switch circuit is closed.

That is, when the voltage detection circuit does not detect a voltage drop, the connection of the first switch circuit is closed and the connection of the second switch circuit is opened. Therefore, although the charge is stored in the voltage holding capacitor, no voltage is applied to the control input. Therefore, no current flows through the discharge current circuit. On the other hand, when the voltage detection circuit detects a voltage drop, the first switch circuit is opened and the second switch circuit is closed. Therefore, a voltage corresponding to the charge stored in the voltage holding capacitor is applied to the control input, so that a current flows through the discharge current circuit. At this time, the voltage holding capacitor is disconnected from the DC output.
That is, the voltage holding capacitor becomes a current source independent of the DC output. Therefore, even when the DC output is near 0 V, a sufficient voltage can be supplied to the control input. For this reason, even when the DC output is near 0 V, the discharge current circuit can flow a current, and the voltage of the DC output can be reduced to 0 V.

According to a third aspect of the present invention, in addition to the above configuration, the discharge current circuit further includes a delay resistor having one terminal connected to the other terminal of the second switch circuit. One terminal is connected to the other terminal of the delay resistor, the other terminal is connected to the ground level, a delay capacitor is connected to the other terminal of the delay resistor, and the drain is connected to the power supply level. , And a FET whose source is connected to the ground level.

That is, when the voltage drop is detected and the voltage is output from the second switch circuit, the gate voltage of the FET changes gradually from 0V. Therefore, the value of the current flowing through the FET takes a maximum value while the voltage of the DC output decreases. For this reason, the maximum value of the current flowing through the FET becomes a suppressed value. The relationship between the current flowing through the FET and the gate voltage is known as the characteristics of the FET. Therefore, it is possible to set the value of the current flowing through the FET to a desired value based on the capacitance of the smoothing capacitor, the value of the delay resistor, and the capacitance of the delay capacitor.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below.
This will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an electrical connection of an embodiment of a capacitor discharge circuit according to the present invention. The circuit includes a voltage detection circuit 2 and a charge discharge circuit 3 when roughly classified.

In FIG. 1, a DC power supply 1 is a switching power supply that uses a commercial power supply led through a power switch 6 as an operation power supply, and supplies a stabilized DC output 111 to a load 5. For this reason, a smoothing capacitor C1 having a large capacitance value is provided inside.

The voltage detection circuit 2 is a block for detecting whether or not the voltage of the DC output (power level described in the claims) 111 sent from the DC power supply 1 has dropped below a preset voltage. If it is detected that the voltage of the DC output 111 has not dropped below a predetermined voltage, the outputs 101 and 102 are set to the H level (between the outputs 101 and 102 and the ground level). Open connection). When it is detected that the voltage of the DC output 111 has dropped below a predetermined voltage, the outputs 101, 1
02 is set to L level (outputs 101 and 102 are connected to the ground level).

The charge discharging circuit 3 is a block for discharging the charge stored in the smoothing capacitor C1 when the voltage detecting circuit 2 detects a voltage drop. That is, when the outputs 101 and 102 of the voltage detection circuit 2 are at the H level, the connection between the DC output 111 and the ground level is opened. When the outputs 101 and 102 become L level, the connection between the DC output 111 and the ground level is closed to discharge the charge of the smoothing capacitor C1.

More specifically, the voltage detection circuit 2
It includes two resistors R4, R6, R7, R9, a Zener diode D5, three diodes D10 to D12, and a comparator 8.

More specifically, one terminal of the resistor R4 is connected to the DC output 111, and the other terminal of the resistor R4 is connected to the cathode of the Zener diode D5. The anode of the Zener diode D5 is grounded. The cathode of the Zener diode D5 is connected to the inverting input of the comparator 8.

Therefore, when the voltage of the DC output 111 is in a voltage range lower than the Zener voltage of the Zener diode D5, the voltage of the inverting input is equal to the voltage of the DC output 111. When the voltage of the DC output 111 is higher than the Zener voltage, the voltage of the inverting input becomes equal to the Zener voltage of the Zener diode D5.

One terminal of the resistor R6 is a DC output 1
11, the other terminal of the resistor R6 is connected to one terminal of the resistor R7, and the other terminal of the resistor R7 is grounded. Therefore, the resistors R6 and R7 are
It operates as a voltage dividing circuit for dividing the DC output 111, and sends the divided voltage to the non-inverting input of the comparator 8.

The path composed of the diode D10 and the resistor R9 is a signal path for obtaining a hysteresis by giving a positive feedback to the comparator 8.
The diodes D11 and D12 are connected to the outputs 101 and 10 respectively.
2 is an element for preventing the signal paths connected to each other from affecting each other.

Here, specific numerical values will be described.
The Zener voltage is 5 V, and the standard value of the voltage of the DC output 111 is 12 V. Further, the voltage division ratio of the resistors R6 and R7 is set to 1/2.

With the above values, when the voltage of the DC output 111 is lower than 10 V, the voltage of the inverting input becomes higher than the voltage of the non-inverting input. Therefore, the output of the comparator 8 becomes L level (the output of the comparator 8 is turned on). When the voltage of the DC output 111 becomes higher than 10 V, the voltage of the non-inverting input becomes higher than the voltage of the inverting input. Therefore, the output of the comparator 8 becomes H level (the output of the comparator 8 is turned off).

The standard value of the voltage of the DC output 111, the Zener voltage of the Zener diode D5, and the voltage dividing ratio of the voltage dividing circuit are not limited to the above-described embodiment, but may be other combinations. However, the predetermined voltage serving as a reference for detecting the voltage drop is preferably in the range of 80% to 90% of the standard value of the voltage of the DC output 111.

Next, the charge discharging circuit 3 will be described.
The charge discharging circuit 3 includes seven resistors R12 to R16, R1.
8, R20, two capacitors C17 and C21, a diode D19, and four transistors Q14 to Q16, Q2
2 is provided. The block 4 including the two resistors R18 and R20, the capacitor C21, the diode D19, and the transistor (FET) Q22 is a discharge current circuit described in the claims.

More specifically, one terminal of the resistor R13 is connected to the DC output 111, and the other terminal of the resistor R13 is connected to the output 101. The base of the transistor Q16 is connected to the output 101, and the emitter of the transistor Q16 is grounded. For this reason,
The transistor Q16 inverts the level of the output 101.

The transistor Q14 whose emitter is connected to the DC output 111 forms a first switch circuit. Therefore, the base of the transistor Q14 is connected to the collector of the transistor Q16 via the resistor R14 that limits the base current. A resistor R12 for raising the base potential to the emitter potential is connected between the emitter and the base of the transistor Q14. A voltage holding capacitor C17 is connected between the collector of the transistor Q14 and the ground level.

The transistor Q15 whose emitter is connected to the collector of the transistor Q14 is connected to the second transistor.
Switch circuit. For this reason, the base of the transistor Q15 is connected to the output 102 via the resistor R16 that limits the base current. A resistor R15 for raising the base potential to the emitter potential is connected between the emitter and the base of the transistor Q15.

One terminal of the delay resistor R18 serves as a control input 142 of the discharge current circuit 4, and is a collector of the transistor Q15 (the other terminal of the second switch circuit).
It is connected to the. A delay capacitor C21 is connected between the other terminal of the delay resistor R18 and the ground level.

The other terminal of the delay resistor R18 is connected to the gate of the FET (Q22). And FE
The drain of T (Q22) is one of the pair of terminals (141) described in the claims, and is connected to the DC output (power supply level in the claims) 111. Also, FET
The source of (Q22) is the other (143) of the pair of terminals described in the claims, and is connected to the ground level.

The gate of the FET (Q22) is connected to the collector of the transistor Q16 via a diode D19 for preventing a current from flowing. Further, a resistor R20 for discharging charges is connected in parallel to the delay capacitor C21.

The charge discharging circuit 3 has the above-described configuration. Therefore, when the voltage detection circuit 2 does not detect a drop in the voltage of the DC output 111, that is, when the outputs 101 and 102
Becomes H level, the transistor Q14 (first
Switch circuit) is turned on, and the transistor Q15
(The second switch circuit) is turned off.

Accordingly, since the DC output 111 is connected to the voltage holding capacitor C17, the voltage holding capacitor C17
The voltage between the terminals 17 (the voltage at the connection point 103) is equal to the voltage of the DC output 111. Further, the path between the voltage holding capacitor C17 and the delay capacitor C21 is disconnected.

Therefore, the voltage between the terminals of the delay capacitor C21 becomes 0 V (even if the charge is accumulated in the delay capacitor C21, the voltage is discharged by the resistor R20). Therefore, since the FET (Q22) is turned off, F
No current flows through ET (Q22).

On the other hand, when the voltage detection circuit 2 detects a decrease in the voltage of the DC output 111, that is, when the outputs 101 and 1
02 goes low, the transistor Q14
(The first switch circuit) is turned off, and the transistor Q
15 (second switch circuit) is turned on. Therefore, the voltage holding capacitor C17 is disconnected from the DC output 111. Therefore, even when the voltage of the DC output 111 decreases, the voltage between the terminals of the voltage holding capacitor C17 (the voltage at the connection point 103) is maintained at a voltage substantially equal to the DC output 111.

For this reason, even when the voltage of the DC output 111 decreases, the voltage of the control
As long as 15 is kept on, the DC output 11
1 (12 V) (the voltage holding capacitor C17 is separated from the DC output 111, so even when the voltage of the DC output 111 decreases, the voltage at the connection point 103 is almost zero. Does not drop).

From the voltage holding capacitor C17,
A current flows to the delay capacitor C21 via the delay resistor R18. For this reason, the gate voltage of the FET (Q22) (voltage at the connection point 147) increases at a speed determined by the values of the delay resistor R18 and the delay capacitor C21 (the limit value of the increase at this time is the control input). 142 is divided by the delay resistor R18 and the resistor R20).

Accordingly, the area between the drain and the source of the FET (Q22) changes from the off state to a direction in which the value of the on resistance gradually decreases. Therefore, the smoothing capacitor C1
Is discharged through the FET (Q22). Further, the value of the current flowing through the FET (Q22) shows a change that gradually increases from zero.

Then, as the discharge of the charge of the smoothing capacitor C1 progresses, the current flowing through the FET (Q22) turns to decrease. Then, when the voltage of the DC output 111 becomes close to 0 V, the transistor Q15 is turned off.

However, since charge is accumulated in the delay capacitor C21, the FET (Q22) is maintained in the ON state. Therefore, the FET (Q22) keeps flowing current until the voltage between the terminals of the smoothing capacitor C1 becomes 0V. After that, the delay capacitor C2
The charge accumulated in 1 is discharged by the resistor R20,
The FET (Q22) is turned off.

As described above, the voltage holding capacitor C1
7 continues to apply a substantially constant voltage to the control input 142 without being affected by the decrease in the voltage of the DC output 111 even when the voltage of the DC output 111 decreases. In other words, the voltage holding capacitor C17 is provided separately from the DC output 111 in a range where the ON state of the transistor Q15 is maintained, and serves as a voltage source that hardly changes even when the voltage of the DC output 111 decreases. Operate.

FIG. 2 is a timing chart showing the level change of the main point when the power switch 6 is turned off and the main switch is turned off after a lapse of time. The operation of the embodiment will be described with reference to FIG.

Before the power is turned on, the voltage holding capacitor C
No charge is accumulated in the capacitor 17 and the delay capacitor C21. Therefore, the voltages at the connection points 103 and 147 are both 0V. When the power switch 6 is turned on in this state, the voltage of the DC output 111 starts to increase. Then, at time T2, the voltage of the DC output 111 becomes the standard value of 12V.

On the other hand, a time T1 indicates a time when the voltage of the DC output 111 reaches a set voltage serving as a criterion for determining a voltage drop. Therefore, before the time T1, the outputs 101 and 102 of the voltage detection circuit 2 are at the L level.
Therefore, the transistors Q14 and Q16 are turned off, and the transistor Q15 is turned on. The voltage at the connection point 103 and the voltage at the connection point 147 are both 0V. Therefore, the FET (Q22) is in the off state, and the FET (Q2
No current Id flows in 2).

At time T1, the output 10
1, 102 change from the L level to the H level. Therefore, the transistors Q14 and Q16 are turned on, and the transistor Q15 is turned off. Therefore, the voltage holding capacitor C
17, the voltage at the connection point 103 is
11 shows a change corresponding to the voltage of No. 11.

However, the voltage of the control input 142 does not change from 0 V because the transistor Q15 is off.
Accordingly, the voltage at the connection point 147 is also 0 V, so that the FET
(Q22) is maintained in the off state, and no current Id flows. After time T2, the load 5 performs a predetermined operation.

Time T3 indicates the time at which the power switch 6 is turned off. Therefore, after the time T3, the voltage of the DC output 111 starts to decrease, and at the time T4,
The voltage of the DC output 111 decreases to a set voltage serving as a reference for determination. Therefore, after the time T4, the outputs 101, 1
02 is at the L level, the transistors Q14 and Q16 are off, and the transistor Q15 is on.

As a result, the voltage of the control input 142 connected to the collector of the transistor Q15 becomes equal to the voltage of the node 103. Therefore, the voltage holding capacitor C17
Thereafter, a current flows through the delay capacitor C21 via the delay resistor R18. Therefore, the voltage of the connection point 147 gradually increases.

Therefore, between the drain and the source of the FET (Q22), the resistance changes gradually from the off state to the resistance value. Therefore, the electric charge accumulated in the smoothing capacitor C1 is discharged through the FET (Q22).
At this time, the value of the current flowing through the FET (Q22) shows a change that gradually increases from zero.

Then, as the discharge of the electric charge of the smoothing capacitor C1 progresses, the current Id flowing through the FET (Q22) starts to decrease. And the DC output 111
When the voltage of the comparator becomes approximately 0 V, the comparator 8 becomes inoperable, and the transistor Q15 is turned off.

However, since charge is accumulated in the delay capacitor C21, the FET (Q22) is maintained in the ON state. Therefore, the FET (Q22) keeps flowing current until the voltage between the terminals of the smoothing capacitor C1 becomes 0V. Thereafter, the electric charge accumulated in the delay capacitor C21 is discharged by the resistor R20, and the FET (Q
22) is turned off.

The electric charge stored in the voltage holding capacitor C17 flows from the collector of the transistor Q14 to the base, and then passes through the DC output 111 via the resistor R12.
Is discharged to the side. Therefore, after the time T5, the connection point 10
The voltage of No. 3 decreases and eventually becomes 0V.

When attention is paid to the voltage of the DC output 111 after time T4, the voltage at time T4 is the highest. But,
The gate voltage of the FET (Q22) at time T4 is 0
V, and then gradually rises. Therefore, FE
The value of the current flowing to T (Q22) takes a maximum value while the voltage of the DC output 111 decreases. Therefore, the maximum value of the current flowing through the FET (Q22) is a suppressed value as compared with the case where the delay capacitor C21 is omitted.

The current flowing through the FET (Q22)
The relationship with the gate voltage is known as the characteristics of the FET (Q22). Therefore, it becomes easy to set the maximum value of the current flowing through the FET (Q22) to a desired value based on the capacitance of the smoothing capacitor C1, the value of the delay resistor R18, and the capacitance of the delay capacitor C21. I have.

FIG. 3 is a timing chart showing a level change of a main point when the power switch 6 is turned off for a short time. If necessary, refer to FIG.
The operation of the 19 routes will be described.

When power switch 6 is turned off at time T7 and time T8 has elapsed, outputs 101 and 102 are output.
Changes from the H level to the L level. Therefore, the transistors Q14 and Q16 are turned off, and the transistor Q15 is turned on. Therefore, the voltage of the gate (connection point 147) of the FET (Q22) starts to increase.

If the power switch 6 is turned on again at time T9 when the outputs 101 and 102 are at the L level, the outputs 101 and 1 are output at time T9.
Since 02 is at the L level, the transistors Q14 and Q16 are turned off and the transistor Q15 is turned on. Therefore, FE
The voltage at the gate of T (Q22) (node 147) shows a continuous rise.

Therefore, the current Id is applied to the FET (Q22).
Flows, but the voltage of the DC output 111 rises. Therefore, at time T10, the DC output 111
Rises to a set voltage that is a criterion for a decrease. Therefore, at time T10, the output 101,
102 changes from the L level to the H level. Therefore,
Transistors Q14 and Q16 are on, transistor Q1
5 turns off.

As a result, the electric charge stored in the delay capacitor C21 is discharged by the transistor Q16 via the diode D19. Therefore, at time T10, the voltage of the gate (connection point 147) of the FET (Q22) becomes 0V. Therefore, the FET (Q22) is turned off, and the drain current Id becomes 0. Therefore, the voltage of the DC output 111 rises at a high speed, and reaches the standard value of 12 V at the time T11.

That is, through the diode D19, F
By providing a path for setting the gate voltage of the ET (Q22) to 0 V, the FET (Q22) can be turned off even when the power switch 6 is cut off for an extremely short time. It is possible. For this reason,
No matter how the power switch 6 is operated, it is possible to perform a trouble-free operation.

It should be noted that the present invention is not limited to the above embodiment, and the transistor Q1 constituting the first switch circuit
4. Transistor Q1 forming second switch circuit
5, and the transistor Q16, as shown in FIG. 4, can be configured using FETs Q31 to Q33.

The discharge current circuit 4 is the same as the circuit shown in FIG. Elements having the same configuration as the circuit shown in FIG. 1 and elements having the same operation are given the same reference numerals as those shown in FIG.

The comparator 8 which is a component of the voltage detection circuit 2 has been described in the case where an element whose output is an open transistor is used. However, when the output is at the H level, an OP amplifier capable of extracting a current from the output is used. Can be used.

[0071]

According to the first aspect of the present invention, when the supply of an input to a DC power supply provided with a smoothing capacitor in the path of the DC output is stopped, the capacitor discharge circuit is stored in the smoothing capacitor. When applied to a capacitor discharge circuit that discharges a charge, the voltage of the DC output is a voltage detection circuit that detects whether the voltage has dropped below a preset voltage, and when the voltage detection circuit detects a drop in voltage, And a charge discharging circuit for discharging the charge of the smoothing capacitor. Therefore, when the DC power supply supplies a predetermined voltage to the load, the voltage detection circuit detects the voltage drop, and no current flows in the charge discharge circuit. On the other hand, when the power switch is turned off, the voltage detection circuit detects a drop in the voltage, so that the charge discharging circuit discharges the charge of the smoothing capacitor. Therefore, when the predetermined voltage is supplied to the load, no loss occurs,
When the power switch is turned off, the output voltage of the DC power supply can be quickly reduced to 0V.

Further, in the capacitor discharge circuit according to the present invention, when one terminal of the DC output is at a power supply level and the other terminal of the DC output is at a ground level, A first switch circuit having one terminal connected to the power supply level, a voltage holding capacitor having one terminal connected to the other terminal of the first switch circuit, and the other terminal connected to the ground level; A second switch circuit having one terminal connected to one terminal of the voltage holding capacitor, a control input connected to the other terminal of the second switch circuit, and a voltage applied to the control input. A discharge current circuit that closes the connection between the pair of terminals, wherein one of the pair of terminals is connected to a power supply level and the other of the pair of terminals is connected to a ground level. When the voltage detection circuit does not detect the voltage drop, the connection of the first switch circuit is closed and the connection of the second switch circuit is opened, and when the voltage detection circuit detects the voltage drop, the first switch circuit is closed. The connection of the switch circuit is opened and the connection of the second switch circuit is closed. Therefore, when the voltage detection circuit detects a drop in voltage, the voltage holding capacitor is disconnected from the DC output. That is, the voltage holding capacitor becomes a current source independent of the DC output. Therefore, even when the DC output is near 0 V, a sufficient voltage can be applied to the control input. Therefore, even when the DC output is close to 0 V, the discharge current circuit can flow the current, and can reduce the DC output voltage to 0 V. For this reason, it is possible to eliminate the need for a voltage source different from the DC voltage supplied to the load.

According to a third aspect of the present invention, in the capacitor discharge circuit, the discharge current circuit includes a delay resistor having one terminal connected to the other terminal of the second switch circuit;
A delay capacitor having one terminal connected to the other terminal of the delay resistor and the other terminal connected to the ground level;
An FET has a gate connected to the other terminal of the delay resistor, a drain connected to the power supply level, and a source connected to the ground level. For this reason, when the voltage drop is detected and the voltage is output from the second switch circuit, the gate voltage of the FET changes gradually from 0V. Accordingly, the value of the current flowing through the FET takes a maximum value while the voltage of the DC output decreases, and the maximum value of the current flowing through the FET becomes a suppressed value. The relationship between the current flowing through the FET and the gate voltage is known as the characteristics of the FET. Therefore, the maximum value of the current flowing through the FET can be set to a desired value based on the capacity of the smoothing capacitor, the value of the delay resistor, and the capacity of the delay capacitor. Therefore, it is possible to easily set the discharge current value while suppressing the maximum value of the current for discharging the capacitor. Further, even when the voltage of the DC output becomes close to 0 V and the second switch circuit is turned off, the FET is maintained in a state in which a current flows by the voltage generated by the electric charge accumulated in the delay capacitor, so that it is more reliable. In addition, there is an effect that the voltage of the DC output can be reduced to 0V.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an electrical connection of an embodiment of a capacitor discharge circuit according to the present invention.

FIG. 2 is a timing chart showing a level change of a main point of the embodiment.

FIG. 3 is a timing chart showing a level change of a main point of the embodiment.

FIG. 4 is a circuit diagram showing a different configuration of the charge discharging circuit.

FIG. 5 is a circuit diagram showing a conventional technique.

FIG. 6 is a circuit diagram showing a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 DC power supply 2 Voltage detection circuit 3 Charge discharge circuit 4 Discharge current circuit 111 DC output (power supply level) 141 One of a pair of terminals 142 Control input 143 The other of a pair of terminals C1 Smoothing capacitor C17 Voltage holding capacitor C21 Delay capacitor Q14 Transistor Q15 forming first switch circuit Transistor Q22 forming second switch circuit Q22 FET R18 Delay resistor

Continued on the front page F term (reference) 5G065 DA04 EA01 HA06 HA16 LA01 MA07 MA09 NA01 NA05 NA07 5H006 CA02 CC08 DA04 DC05 GA04 5H410 BB04 DD02 EA11 EB01 EB40 FF03 FF22 KK05

Claims (3)

[Claims] When an input supply to a DC power supply having a smoothing capacitor provided in a DC output path is stopped,
In a capacitor discharging circuit for discharging electric charges accumulated in the smoothing capacitor, a voltage detection circuit that detects whether the voltage of the DC output has dropped below a preset voltage, and the voltage detection circuit reduces the voltage. And a charge discharging circuit for discharging the electric charge of the smoothing capacitor when detecting is detected. 2. When the one terminal of the DC output is set to a power supply level and the other terminal of the DC output is set to a ground level, the charge discharging circuit includes a first terminal having one terminal connected to a power supply level. A voltage holding capacitor having one terminal connected to the other terminal of the first switch circuit and the other terminal connected to the ground level; and one terminal connected to one of the voltage holding capacitors. A second switch circuit connected to the second terminal; a control input connected to the other terminal of the second switch circuit; and when a voltage is applied to the control input, the discharge between the pair of terminals is closed. A current circuit, wherein one of the pair of terminals is connected to a power supply level, the other of the pair of terminals is connected to a ground level, and the voltage detection circuit does not detect a voltage drop. Kiniwa,
The connection of the first switch circuit is closed and the connection of the second switch circuit is opened. When the voltage detection circuit detects a drop in voltage, the connection of the first switch circuit is opened and the connection of the second switch circuit is opened. 2. The capacitor discharging circuit according to claim 1, wherein the circuit is closed. 3. The discharge current circuit according to claim 1, wherein one terminal is connected to the other terminal of the second switch circuit, and one terminal is connected to the other terminal of the delay resistor. A delay capacitor having a terminal connected to the ground level; and an FET having a gate connected to the other terminal of the delay resistor, a drain connected to the power supply level, and a source connected to the ground level. 3. The capacitor discharging circuit according to claim 2, wherein