JP2000188760A - Method and device for converting video code - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale by performing an inter-frame-to-intra-frame conversion with a DCT area as it is and using an input video signal as it is when conversion is not needed. SOLUTION: An intra-frame signal 102 outputted by an inter-frame and intra-frame conversion circuit 101 is a DCT coefficient string when each block of an image is subjected to DCT transformation. A BUF 105 is used to meet an input video code 2 to time delay in the circuit 101. The video code 2 stored in the BUF 105 is read to be a video code 103. A synthetic circuit 104 performs variable length coding of a selected signal in accordance with an externally inputted intra-frame/inter-frame selection signal 106 when it is the intra-frame signal 102 and further adds information such as a header. The signal 102 becomes a video code for intra-frame coding by that and is outputted as a video code 7. When the selected signal is the video code 103, the video code 103 is outputted as the video code 7 as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for compressing and coding an image, and more particularly to a video code conversion method and apparatus for converting an inter-frame coded image into an intra-frame coded image.

[0002]

2. Description of the Related Art A moving image has an enormous amount of information, and it is necessary to compress the amount of information by high-efficiency coding in order to transmit the digital image and store it. The International Standard for High Efficiency Coding is the International Telecommunication Union Telecommunication Standardization Sector (I
TU-T), the International Organization for Standardization (ISO) and the International Electrotechnical Commission (IEC). 261 and H.E. H.263 and general MPEG1 according to ISO / IEC, and MPEG2 whose application range is widened.

All of these international standard systems use an inter-frame coding technique based on motion-compensated inter-frame predictive coding, and include an intra-frame coding technique for coding a frame alone, that is, within a frame screen. Are used together.

FIG. 22 shows a frame configuration of an encoded moving image. First, the first frame is coded by intra-frame coding to become an I picture. Intra-frame encoding is
In any of the international standards mentioned above, a discrete cosine transform (hereinafter referred to as “DCT (Discrete
sine transform) ”). DCT is applied to each block of 8 × 8 pixels of an image. The 64 pixels of the block are transformed by DCT into 64 frequency components (DCT coefficients). The DCT coefficients are subsequently encoded by a variable length code.

[0005] From the second frame onward, many frames (all frames depending on the system) are coded by inter-frame coding for performing predictive coding using the immediately preceding coded image as a reference image. Becomes Specifically, a prediction image of 16 × 16 pixels is extracted from the reference image in macroblock units of 16 × 16 pixels of the image,
The difference between the macroblock to be coded and the predicted image, that is, 16 × generated by taking the difference for each corresponding pixel
The difference image of 16 pixels is encoded. The encoding of the difference image is performed by applying DCT to each divided 8 × 8 pixel, as in the intra-frame encoding. In addition, even if the inter-frame coding is performed, the intra-frame coding may be adaptively performed on a part of the frame. However, the term “inter-frame coding” includes the intra-frame coding.
I will say.

[0006] The above-described extraction of a predicted image is performed by extracting
This is done by searching for an optimal (usually the smallest prediction error) part around the same screen position as the macroblock to be coded. In order to represent the position of the predicted image on the reference image, a motion vector (vertical and horizontal two-dimensional) from the screen position of the macroblock to be encoded is used. In this way, the encoded difference image and the motion vector are generated by the motion compensation inter-frame coding, and the video code is generated from these.

Decoding starts from an I picture, and a reference image is generated by accumulating a difference image each time a frame advances, and the position is corrected by a motion vector from the reference image of the previous frame. This is performed by taking out the predicted image thus obtained and adding the difference image of the current frame to the predicted image to obtain a reproduced image.

There are two types of motion vector precision: integer pixel precision and half-pixel precision (half-pel) for the purpose of improving prediction precision. In the case of integer pixel precision, each pixel indicated by the motion vector becomes a prediction image. In the case of half pel, detailed description is omitted, but half pixels indicated by the motion vector are averaged between two pixels or four pixels. And

The above is a method of encoding a luminance signal.
Similar processing is performed on the color signals (color difference signals) of the components. However, since the resolution (the number of pixels) of the color difference signal is の of the luminance signal in both the vertical and horizontal directions, motion compensation is performed in units of 8 × 8 pixels in conjunction with the luminance signal.

Further, depending on the standard system, there is a B-picture in which prediction (forward prediction / reverse prediction / bidirectional prediction switching) is performed from frames preceding and succeeding in time.
Since the processing can be performed as an extension of the processing of the picture, the description is omitted.

As described above, the P picture generated by the motion compensation interframe coding is generated by accumulating the difference images. Therefore, the P picture cannot be decoded and reproduced without the immediately preceding reference image. For example, when trying to decode the sixth frame (P picture) in FIG. 22, it cannot be decoded without accumulating from the first frame, that is, going back to the first frame. In the case of MPEG1 and MPEG2 described above, the normal value is 0.1.
An I picture is inserted at a period of about 5 seconds (15 frame periods). 261, H .; In real-time communication using H.263, all P-pictures (or B-pictures) are usually used after the first frame is encoded as an I-picture.
Is often encoded as

Therefore, when the video code of the frame configuration shown in FIG. 22 is, for example, a digital broadcast, and the video is recorded from the fifth frame, for example, in the middle of the video, if the video is recorded as it is, the first video before it is recorded. Since the video of the fourth frame is not recorded, the I picture of the first frame is lost, and the recorded video cannot be reproduced.
Therefore, it is necessary to convert the fifth frame at the start of recording into an I-picture before recording. That is, I1, P2, P
The video code configured as 3, P4, P5, P6 is represented by I
It is necessary to change the configuration to 1, P2, P3, P4, I5, P6.

When such conversion is required, a still image (frame) having a large scene change is taken out and arranged in one screen as a reduced image, or a frame is thinned out to perform fast forward reproduction. There are many cases such as performing.

As an example of a conventional apparatus for converting a P picture in the middle of a video code into an I picture, there is a code conversion apparatus 1 shown in FIG. The input video code 2 (code-level signal) is decoded by the decoding circuit 3 and becomes a reproduced video 4 once. At the same time, the decoding circuit 3
The motion vector 5 used in the decoding process is output. The reproduced video 4 is a pixel-level signal that can be displayed as it is.

In the process of encoding the reproduced video 4 again, the middle is encoded as an I picture, and the others are encoded as P pictures, thereby performing conversion. Encoding as an I picture is performed under the control of a selection signal 106 from the outside. In the above example, the selection signal 106 is a signal indicating the start of recording, a scene change signal, or the like. Encoding of the reproduced video 4 is performed by the re-encoding circuit 6, and the converted video code 7 (code-level signal) is output.

The details of the decoding circuit 3 are shown in FIG. This circuit is a commonly used standard decoding circuit.
The input video code 2 is converted into a variable length decoding circuit (VLD).
Decoded at 20. The DCT coefficient 21 of the decoded coded difference image is input to an inverse quantization circuit (iQ) 22. The motion vector 5 decoded at the same time is supplied to a motion compensation circuit (MC) 28 and sent out of the decoding circuit. The DCT coefficient 21 is inversely quantized by an inverse quantization circuit 22 to become a differential DCT coefficient 23. The coefficient 23 is subsequently input to an inverse DCT transform (iDCT) circuit 24 to become a differential image 25.

The frame memory (FM) 26 stores a reference image decoded immediately before. The motion compensation circuit 28 reads an image signal 27 from the frame memory 26 in accordance with the value of the motion vector 5 and performs prediction. The signal 29 is output. When the motion vector has integer precision, the image signal 27 of 8 × 8 pixels is read from the predicted image 29 of 8 × 8 pixels, and when the motion vector is half-pel, the predicted image 29 of 8 × 8 pixels is read.
In contrast, the number required for calculating the half pel, that is, 9 × 8,
The image signal 27 of either 8 × 9 or 9 × 9 pixels is read.

The difference image 25 and the predicted image 29 are added for each pixel by an adding circuit 30 to form a reproduced image 4 at a pixel level. The reproduced image 4 is written into the frame memory 26 and becomes a reference image of the next frame.

Next, details of the re-encoding circuit 6 are shown in FIG. This circuit is also a commonly used standard encoding circuit except that the selection signal 106 is input to the control circuit 71. The difference between the input reproduced image 4 and the predicted image 41 is obtained by a difference circuit 40, and a difference image 42 is generated.

When a P picture is output in the inter-frame prediction mode, the switch 70 is closed, and the predicted image 41 from the reference image is supplied to the difference circuit 40. The predicted image 41 is stored in the frame memory 5 in which the reference image is stored.
The motion compensation circuit 56 corrects the position of the signal read from No. 4. The circuit 56 corrects the position using the motion vector 5.

On the other hand, when the I picture is output in the intra-frame prediction mode, the switch 70 is turned off, and the prediction image 41 is not sent to the difference circuit 40 and is not sent to the addition circuit. Therefore, the output signals of the difference circuit 40 and the addition circuit 52 are not a difference but an image.

The switch 70 is controlled by a control circuit 71. The selection signal 106 is input to the control circuit. When the selection signal 106 instructs intra-frame encoding, the switch 70 is turned off, and the video signal becomes an I picture. When performing inter-frame encoding, the control circuit 71
Selects connection / disconnection as appropriate depending on the state of the image.

Difference image 42 at the time of inter-frame encoding
Are converted into DCT coefficients 44 by the DCT circuit 43.
The DCT coefficient 44 is obtained by quantizing the DT
The DCT coefficients 46 become the CT coefficients 46, and then the DCT coefficients 46 are encoded by the variable length encoding circuit 47 together with information such as the motion vector 5 and the encoding mode, and the video code 7 is output.

Generally, an image signal has a property that its frequency component is biased toward a low frequency component. Therefore, the quantized D
The higher order part of the CT coefficient has a very high probability of being zero. By utilizing this property, the amount of information can be significantly reduced. The DCT coefficient 46 quantized by the quantization circuit 45 is inversely quantized by the inverse quantization circuit 48, and subsequently becomes the reproduced difference image 51 via the inverse DCT transformation circuit 50. The reproduced difference image 51 is added to the previous predicted image 41 by the adding circuit 52 to form a reproduced image 53. The reproduced image 53 is stored in the frame memory 54 as a reference image at the time of encoding the next frame.

At the time of intra-frame encoding, the difference circuit 40
The output of the inverse DCT transform circuit 50 is an image, and the amount of information is reduced in the frame plane. Through such processing, the encoding mode in the video code can be changed. Specifically, the P picture in the code can be changed to an I picture.

[0026]

The above-mentioned P picture is represented by I
The video code conversion device for converting a picture has the following problems. The first problem is that re-encoding is performed after the amount of information is increased by decoding to the pixel level, so that the processing amount is increased and the circuit scale is increased. Second, there is a problem in a video system including a transmitting device that transmits a converted video code and a plurality of receiving devices that receive the video code from the video device. In such a system, the receiving devices are individually independent. Since a video code conversion is requested (a selection signal is transmitted), a video code conversion device must be provided for each receiving device, and an increase in the circuit scale of the system is inevitable.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a novel video code conversion method and apparatus having a small circuit scale.

[0028]

In the above-mentioned conventional transforming process, the signal of the code level in the DCT area to be encoded is once converted to a pixel level signal by inverse DCT transform, and the pixel level signal is again subjected to DCT transform. To a code level signal in the DCT region. On the other hand, the algorithm and the configuration of the processing for performing the intra-frame intra-frame conversion in the DCT region are the same as those of the 12th Digital Signal Processing Symposium No. C7-4 No. 597 sponsored by the Institute of Electronics, Information and Communication Engineers.
This is found in the resolution conversion method in the DCT domain described on pages 602 to 602 (November 1997).

The inventor of the present invention uses this processing technique to perform inter-frame intra-frame conversion without changing the pixel level to the DCT region, and to use the input video code as it is when conversion is not necessary. As a result, it has been found that a video transcoder can be configured.
With this configuration, the circuit scale can be significantly reduced as compared with the conventional method in which all video codes are once reproduced at the pixel level and then re-encoded. That is, a video code conversion apparatus of the present invention includes a conversion circuit that performs intra-frame conversion between motion compensation frames in a DCT domain on a video code, a buffer that temporarily holds the video code to delay the video code by a predetermined time, It is characterized by comprising a conversion circuit and a synthesis circuit for selecting and switching the output signal of the buffer.

The output signals of the conversion circuit and the buffer are
Since a plurality of receivers are always present at the same time, when a plurality of receivers are arranged, the plurality of receivers can share the inter-frame intra-frame conversion circuit, and each receiver can include only a combining circuit. Thereby, the effect of reducing the circuit scale can be further enhanced.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a video code conversion method and apparatus according to the present invention will be described in more detail with reference to embodiments of the present invention according to several embodiments shown in the drawings.

[0032]

<Embodiment 1> In FIG. 1, reference numeral 101 denotes a circuit for performing an inter-frame intra-frame conversion on an input video code 2, and reference numeral 105 designates a video code 2 by temporarily storing the video code 2. A buffer 104 for delaying the time is a signal 102 in the frame which is an output signal of the intra-frame conversion circuit 101 and a video code which is an output signal of the buffer 105.
A synthesizing circuit 100 for selecting any one of 103 and outputting the video code 7, and 100 is a video code conversion device including the circuits 101, 104 and 105.

The intra-frame signal 102 output from the inter-frame intra-frame conversion circuit 101 is, specifically, an 8 × 8
Is a DCT coefficient sequence when each block is divided by DCT. Since a time delay occurs in the conversion process of the conversion circuit 101, the buffer 105 is used to adjust the input video code 2 to the delay. The video code 2 stored in the buffer 105 is read and becomes the video code 103. The synthesizing circuit 104 selects either the intra-frame signal 102 or the video code 103 according to the intra-frame / inter-frame selection signal 106 input from the outside, and if the selected signal is the intra-frame signal 102, Is variable-length encoded, and information such as a header is added. As a result, the intra-frame signal 102 becomes a video code for intra-frame encoding, and is output as the video code 7. When the selected signal is the video code 103, the video code 103 is output as it is as the video code 7.

FIG. 2 shows a detailed configuration of the inter-frame intra-frame conversion circuit 101. The input video code 2 is decoded by the variable length decoding circuit 20, and becomes a DCT coefficient 21.
The DCT coefficient 21 is a difference DC
The T coefficient becomes 23.

DCT area motion compensation circuit (DCT-MC)
Reference numeral 201 denotes a DCT area prediction image described below, that is, a predicted DCT coefficient 202, and the operation of the motion compensation circuit 28 shown in FIG. 24 is performed in the DCT area. Motion vector 5
Is supplied to the motion compensation circuit 201. The detailed configuration of the motion compensation circuit 201 will be described later. In accordance with the value of the motion vector 5, the compensating circuit 201 reads a DCT coefficient of the reference image (a DCT coefficient sequence when the reference image is intra-frame coded) from the frame memory 205, A DCT coefficient 206 is read, and a transform described below is performed on the DCT coefficient 206 to output a predicted DCT coefficient (a signal obtained by performing a DCT on a predicted image of 8 × 8 pixels) 202.

The difference DCT coefficient 23 and the predicted DCT coefficient 202
Are added by the addition circuit 203 for each frequency component, and become a reproduction DCT coefficient. Since the reproduced DCT coefficient is a DCT coefficient after motion compensation, the DCT coefficient
The converted signal, that is, the above-described intra-frame signal 102.

Before describing the detailed configuration of the DCT area motion compensation circuit 201, an algorithm of the processing will be described. The conversion algorithm used in the above-mentioned document was used.

To make the algorithm easier to understand,
First, processing contents in the pixel area will be described with reference to FIGS. 3 and 4, and then a method in a case where they are applied to the DCT coefficient area will be described. To generate a predicted image corresponding to an 8 × 8 pixel block in the current frame, signals of four blocks to be encoded (see the left side of FIG. 3) in which reference image blocks overlap are used. The overlapping position changes depending on the magnitude of the motion vector. That is, how they overlap is determined by the motion vector. Therefore, if the block of the reference image is shifted using the motion vector so as to completely overlap the block to be coded, the compensation has been performed.

The number of blocks to be used is reduced to 2 or 1 when the horizontal or vertical component of the vector is an integral multiple of 8, but in the following description, a more general case, that is, each component The description will be made assuming that it is not an integral multiple of 8.

In this case, in the pixel area, the portions of the four blocks B1 to B4 which are provided with oblique vertical and horizontal lines are used. Bref1 to Bref4 shown on the right side of FIG.
After parallel movement as shown in FIG. 3 and supplementing 0 to unnecessary pixel portions, Bref1 to Bref4 are added,
Completely overlapping blocks (in the pixel area) of the predicted image (Bref described below) are determined, and a predicted image is generated.

As shown in FIG. 4, the conversion from B to Bref is realized by multiplying a matrix corresponding to the size of the part to be converted (w × h pixels in the example of FIG. 4) twice. The size corresponds to the motion vector. In the example of FIG. 4, Bref1 is generated by multiplying the matrix V (h) in the lower part of the figure from the left of B1, and further multiplying the matrix H (w) from the right. Similarly, Bref2
To Bref4 are described as in equation (1).

[0042]

(Equation 1)

By performing matrix addition (hereinafter simply referred to as "addition" or "sum") on the Bref1 to Bref4 generated in this way, the pixels divided into four blocks can be combined into one block Bref. A predicted image is generated from Bref.

The processing in the pixel area has been described above.
In the area, this is realized by applying DCT to both sides of the final equation (1). Specifically, as shown in equation (2),
It is the sum of the coefficients obtained by transforming Bref1 to Bref4 by DCT.
The fact that the sum DCT (Bref) is obtained by processing in the DCT region will be described below.

[0045]

(Equation 2)

First, for example, with respect to Bref1 of the uppermost expression in Expression (1), DCT (Bref
Equation (3) shows that 1) is eventually obtained by applying DCT to each of V (h), B1, and H (w) and then multiplying each.

Next, for Bref2 to Bref4, similarly, it is shown that by applying DCT to each of the matrix and the block and then multiplying each, the DCT transform can be obtained.

[0048]

(Equation 3)

On the other hand, DCT (V (h)), DCT (H (w))
Are fixed matrices determined when h and w are determined,
Since the values of h and w each range from 1 to 7, the DCT
It is sufficient to prepare a total of 14 types of matrices for each of (V (h)) and DCT (H (w)).

From the above, by storing DCT coefficients (B1) to DCT (B4), which are DCT coefficients of B1 to B4, DCT (V (h)), DCT (H (w)) and the like are respectively stored. DCT (Bref1) to DCT (Bref4) are obtained by multiplication,
It can be seen that DCT (Bref) is obtained by adding these. DCT (B1) to DCT (B4) are DC
Signal in the T domain, and therefore in the DCT domain, ie, DC
It can be seen that the predicted DCT coefficients can be generated without performing the inverse transform of T.

The above description is for the case where the precision of the motion vector is integer precision. Although a detailed description is omitted, when a half pel is used for a prediction image, a prediction DCT is similarly performed using a signal of 9 × 9 pixels to generate a prediction image of 8 × 8 pixels.
A coefficient is generated.

The DCT area motion compensation circuit 20 shown in FIG.
1 is a circuit for realizing the above algorithm, the details of which are shown in FIG. D of the input frame memory 205 output
The CT coefficients 206, that is, DCT (B1) to DCT (B4) are temporarily stored in the memory 120. On the other hand, the DCT_H table 133
And a DCT_V table 137, a matrix of DCT coefficients corresponding to the motion vector, for example, DCT (H
(w)), DCT (V (h)), and the like. Also,
The control circuit 140 controls the operations of the memories 120, 124, 130 and the tables 133, 137 according to the motion vector 5.

Each element of the two matrices is read out in the order described below under the control of the control circuit 140 when the motion vector 5 is input. First, the DCT coefficient 206 read from the memory 120 and the table 133
Is multiplied by the product-sum calculator 122, the result is accumulated in the value of the memory 124, and the accumulated result is returned to the input and added to the product operation. By this series of operations, for example, DCT (B1) · DCT of Expression (3)
The operation corresponding to (H (w)) is completed.

Similarly, by the product-sum operation unit 126 and the memory 130,
An operation corresponding to the operation with DCT (V (h)) in Expression (3) is performed, and DCT (Bref1) is stored in the memory 130. At the time of the next operation relating to B2, the stored DCT (Bre
f1), the calculation result is accumulated, and DCT (Bref1) + DCT (Br
ef2), and then accumulate the operation results on B3 and B4. In this way, the addition of equation (2) can be performed simultaneously.

FIG. 6 is a diagram showing the order of data input to the product-sum calculators 122 and 126. In the upper part of the figure, an example is shown in which matrix A and matrix B are integrated to obtain a matrix C. Here, for example, AH1
Indicates that 8 data in the first row of the left matrix A are processed in order from the left, and BV1 indicates that 8 data in the first column of the right matrix B are processed in order from the top. I have. The lower part of FIG. 6 shows the read timing of each data. First, the first row (AH
1) and the data of the first column (BV1) of the matrix B are read out in order, and the data of AH1 and the corresponding data of BV1 are sequentially accumulated and accumulated to obtain C11, which is stored in the memory 124. Hereinafter, BV1 repeatedly uses the same data, and matrix A sequentially reads out data from AH2, AH3,.
The data of C81 is obtained. BV2, BV
By performing on 3, 3,...
Is obtained.

Although the calculation shown in FIG. 6 is performed using all the elements of the matrix A, as mentioned above, the effective component (non-zero coefficient) of the DCT coefficient of the image signal is the DCT coefficient.
Assuming that the T coefficient 206 is the matrix A in FIG. 6, the upper left of the matrix A in FIG. 6, that is, the low-frequency component tends to be concentrated, and the lower right of the matrix A has a high probability of being all zero. For example, when AH7 and AH8 are all 0, the operation result of AH7 and AH8 in FIG.
Therefore, the processing can be omitted. Thereby, the total operation time can be reduced. Similarly, AV7,
AH1 when AV8 (the right two columns of matrix A) is 0
Since the operation results for the last two elements of .about.8 are always 0, the processing time can be reduced by performing the operations of AH1.about.8 for only the first six elements.

Next, FIG. 7 shows details of the synthesizing circuit 104 of FIG. The input intra-frame signal 102 is subjected to intra-frame variable-length encoding in a variable-length encoding circuit 111. That is, it is converted into an intra-frame encoded video code 112. The variable length code circuit 111 has only a code for intra-frame coding. The video code 112 is input to the selection circuit 115 together with the video code 103 that is the input video code 2 delayed by a predetermined time. The selection circuit 115 includes an intra-frame encoded video code 112 and a video code 1
03, ie, the video code 103 by inter-frame coding is switched in frame units and output as the video code 7.

In this way, of the frames (P pictures) obtained by the inter-frame coding, the frame selected by the selection signal 106 is converted into an intra-frame coded I picture, and a part of the frame is converted into an I picture. The sequence (sequence) of the changed frames is synthesized.

It should be noted that the information of the video code 103 needs to be reflected on the video code 112 in order for the video code 7 composed of such a sequence of frames to be correctly decoded. This process is performed by the control circuit 113. The control circuit 113 extracts necessary information from the video code 103 and notifies the variable-length coding circuit 111 via the control signal 114.

Examples of such information include frame time information (such as a time stamp for managing decoding time and reproduction time), image size, and image configuration (aspect ratio,
There are items common to the entire sequence, such as interlace / progressive, color signal characteristics (conversion method, sampling position, etc.). Among them, the image size and the time information of the frame are essential information. The image size information is stored in the converter 10
Since it is indispensable in the process of 0, it can be separately notified to the variable length coding circuit 111, but the time information of the frame needs to be notified by the control circuit 113. If the intra-coded frame is accessed from the middle of the sequence, or if it is necessary to perform an operation to discard the frame before this frame and make a new first frame, items common to the entire sequence Must be added to the head of each frame of the video code 112 by intra-frame coding.

When the above-described inter-frame intra-frame conversion is performed, the code amount of the converted frame differs. In general, the prediction efficiency is lower in intra-frame coding, and thus the code amount tends to increase by the above-described conversion processing. On the other hand, a reproduced image can be obtained by applying an inverse DCT transform to the intra-frame signal 102, that is, the reproduced DCT signal, and the obtained image (intra-frame reproduced image) is directly decoded without performing the intra-frame conversion. (Image reproduced between frames). Therefore, even though the reproduced images are substantially the same, the amount of codes increases due to the conversion of intra-frame coding, and it is desired to reduce the amount of codes.

As a method of reducing the code amount after the intra-frame encoding, the intra-frame signal 102 (reproduced DCT signal) output from the inter-frame intra-frame conversion circuit 101 is quantized, and the high-frequency component of the signal is reduced to 0. There is a method to replace it. However, the image quality may change due to the reduction of the code amount. Also, when an image according to this method is used as the first prediction signal, the images of subsequent frames are all different from the original inter-frame reproduced image. As described above, the change in image quality is inherited by the succeeding inter-frame encoded image, but the change is constant for each successive frame and is not accumulated, so that the image quality does not significantly deteriorate. This change in image quality depends on the degree of quantization roughness.

When the next intra-frame coding conversion is selected, a change in image quality of the preceding coding conversion does not affect the selection. Therefore, it is also possible to perform coding conversion so that a change in image quality does not appear when the next intra-frame coding is selected. Thus, the inter-frame intra-frame conversion circuit 10
The present invention also includes the case where the intra-frame signal 102 output from 1 is quantized after encoding conversion, or the high-frequency component is replaced with 0.

<Embodiment 2> FIG. 8 shows an embodiment of a video code converter having a code storage function. In the figure, 303
Is a storage device for storing the intra-frame signal 102 output from the inter-frame intra-frame conversion circuit 101, and 305 is a buffer 105
The storage device 301 for storing the video code 103 output from the storage device 301 is a video code conversion unit that outputs the video code 7 with a time delay by the storage devices 303 and 305, and the video signal conversion unit 300 is a video code conversion unit 301 and a storage device 303. , 305 having a storage function. It is written in the storage device 303,
The read intra-frame signal 102 is referred to as an intra-frame code 302 again, and the video code 103 written to and read from the storage device 305 is referred to as an inter-frame code 304 again.

FIG. 9 is a detailed diagram of the video code conversion unit 301. In the figure, reference numeral 310 denotes an in-frame signal 302 input to a storage device 302 as an intra-frame code 302 and an intra-frame code 302 read from the storage device 303 to a combining circuit 104
A switch 312 for supplying the video code 103 to the storage device 305 as the inter-frame code 304 and the inter-frame code 304 read from the storage device 305 to the combining circuit
This is a changeover switch to be supplied to 104. The conversion unit 301
Except for switches 310 and 312, the configuration is the same as that of the video encoding / conversion apparatus 100 shown in FIG.

At the time of code storage, the switches 310 and 312 are connected to the left side, and the intra-frame signal 102, that is, the intra-frame code 302, is supplied to the storage device 303, and the video code 103, that is, the inter-frame code 304, is written into the storage device 305. It is. At the time of reading at an appropriate time after the accumulation, the switches 310 and 312 are connected to the right side, respectively, and the accumulated in-frame signal 10
2 and the video code 103 are supplied to the synthesis circuit 104. The synthesizing circuit 104 performs variable-length coding on the read intra-frame signal 102, selects one of the video code and the inter-frame code 304, and synthesizes the video code 7.

FIG. 10 shows an example of the operation of the video code converter 300.
Shown in The number represents the frame number, and the subscript i is I
Indicates that the frame has been converted to a picture. The input video code 2 is the intra-frame code 30 in the upper part of FIG.
2. Accumulated as indicated by the inter-frame code 304. That is,
All frames of the inter-frame code are stored in the storage device 305, and frames 1, 6, and 11 of the intra-frame code are stored in the storage device 303. In the lower part of FIG. 10, five examples of seven video output codes are shown as examples of reading and synthesizing the signals thus accumulated.

Video code 7 example 1: Output inter-frame code as it is, video code 7 example 2: Output a sequence starting in the middle of the sequence (6th), Video code 7 example 3: Output a sequence starting in the middle of the sequence (11th) Output, video code 7 example 4: Output a sequence including a frame that is intra-frame coded in the middle of the sequence (in this case, random access of the sequence is easy), video code 7 example 5: Consist of only intra-frame code Output sequence.

It is apparent that the following modifications are also included in the present invention. Specific media applicable to the storage devices 303 and 305 include VTRs, hard disks, optical disks, DVD-RAMs, CD-Rs, semiconductor memories such as DRAMs and flash memories, and magnetic storage devices. The storage device 303 and the storage device 305 may be the same medium or different media. Further, the storage devices 303 and 305 may share a single storage device. The storage devices 303 and 305
Have the function of reading and writing at the same time, the codes 302 and 304 are bidirectional signals, and the switches 310 and 3
By setting 12 as a switch having a function of simultaneously transmitting signals in both directions, it is possible to simultaneously perform read conversion while recording codes. Further, regardless of the number of storage devices, reference numerals 302 and 304 and switches 310 and 312
11, 313 (see FIG. 9) and the like can also be physically time-division multiplexed on one signal line.

When the reproduced DCT code, which is the intra-frame signal 102, is input to the storage device 303, the reproduced DCT code may be variable-length coded to compress the amount of information, and may be recorded after video coding. A storage device having a small capacity can be applied by the information amount compression, and more images can be recorded. Note that the code configuration by the variable-length encoding at the time of recording is performed by the variable-length encoding circuit
The code configuration by encoding (see FIG. 7) may be different or the same. In the same case, most circuits and processes of the variable length code circuit 111 can be omitted,
Only the sign correction by the control information 114 is required. Furthermore,
By adding this code correction (time information of the frame to be coded) to the storage device 303, the variable length coding circuit 111 in the synthesizing circuit 104 can be entirely deleted.

The switches 310 and 312 may be connected to any two of the three contacts. That is, the conversion unit 301 includes the signal 102 and the code 10 in addition to the operation described above.
3 is provided so as to be directly supplied to the synthesis circuit 104. By doing so, the conversion unit 301
The same operation as the conversion device 100 of FIG. 1 can be performed. Further, in the above description, the switch 310 and the switch 312 always operate in cooperation with each other, but they may operate independently.

When the input video code 2 is stored in the storage device 305, the buffer 105 may be omitted. However, a function for associating each of the frames 302 and 304 is required.

In the above description, the intra-frame code
Both the 302 and the inter-frame code 304 are read out, and the
Although the selection / discarding is performed inside the storage device, the signal to be discarded may not be read from the storage devices 303 and 305 by applying the selection signal 106 to the control of the storage devices 303 and 305. With this configuration, the storage device 30
In the case where 3,305 is shared by one, the read / write speed of the storage device is slowed, and a medium with a low access speed can be used. This has the effect that codes with a high bit rate can be stored, or the structure of the storage device is simplified. Similarly, when the codes 302, 304, etc. are time-division multiplexed, the transmission speed of the transmission line or the bus width can be reduced by stopping the reading of the signal to be discarded in advance. As a result, the effect of reducing the circuit scale can be obtained.

<Embodiment 3> FIG. 11 shows an embodiment in which the conversion unit 301 in FIG. 9 has a resolution conversion function. In the figure, reference numeral 402 denotes a circuit for performing resolution conversion on a reproduced DCT signal which is an intra-frame signal, and reference numeral 401 denotes a resolution conversion circuit 402.
Is a video code conversion unit provided with. FIG. 12 shows the configuration of the resolution conversion circuit 402. The code 311 (reproduced DCT signal) which is the intra-frame code 302 from the switch 310 is
It becomes a reproduced DCT signal 403 after resolution conversion via 0. The control circuit 411 cuts off the DCT coefficient at a position not used for converting the resolution by opening the switch 410 from the matrix position of the DCT coefficient of the input reproduced DCT signal. Resolution conversion is performed by removing DCT coefficients at unused positions, and the signal after resolution conversion is reproduced DCT.
Obtained as signal 403.

FIG. 13 shows an example of the selection of the DCT coefficient. 8
The × 8 DCT coefficient can be represented as shown in the left end diagram of FIG. One small square in the figure is one DCT
Indicates a coefficient. When 64 coefficients are arranged as shown in the figure, the DCT coefficient at the upper left is a DC component, the right is a horizontal high frequency component, and the lower is a vertical high frequency component.

When an 8 × 8 DCT coefficient is transformed by an 8 × 8 inverse DCT, for example, an 8 × 8 reproduced image shown in the center left figure is obtained. By extracting only 4 × 4 on the low frequency side (upper left of the same figure on the left side) of the 8 × 8 DCT coefficient, and performing 4 × 4 inverse DCT on this, it is reduced to 4 × 4 as shown on the right end figure. A reproduced image is obtained.

By selecting only the DCT coefficient on the low frequency side in this manner, N / 8 times (N = 1, 2,...)
The image can be reduced in (7). In the control circuit 411 of FIG. 12, among the 64 input DCT coefficients,
It operates so as to select only N × N DCT coefficients necessary for a desired resolution.

Assuming that N> 8, the input DCT coefficients are directly arranged in the low frequency portion 8 × 8 of the N × N DCT coefficients, and the DCT coefficients of the remaining portion (N × N−64) are set to 0. By doing so, resolution conversion for image enlargement can be performed. An enlarged image can be obtained by performing an inverse DCT transform on the N × N DCT coefficients generated in this manner. When N = 8, the switch
410 remains closed and no resolution conversion is performed.

FIG. 14 shows an example of the operation of the video code conversion unit 401. All the frames of the input inter-frame video code 2 are converted into intra-frame codes 302 (reproduced DCT signals). The converted reproduced DCT signal is stored as a signal of the original resolution, and is reduced or converted to the original size by the resolution conversion circuit 402 at the time of synthesis, and is subjected to variable-length encoding. In the example 1 of the video code 7 in FIG. 14, the reduced intra-frame code (1s) is inserted immediately after the intra-frame code (1i) of the original size, and thereafter, the inter-frame encoded frame follows. I have. With the code as in Example 1, the reduced image transmitted partially (for example, frame 1) can be recorded for the purpose of recording or searching while reproducing normally on the receiving side. When the stream is constantly transmitted in the form of a broadcast, the receiving terminal extracts only the reduced image, displays the reduced image on the screen, and informs the outline of the program, thereby improving the viewer's convenience. In particular, by transmitting the reduced image, the receiving terminal does not need to perform the image reduction processing, so that the circuit scale and operation speed of the receiving terminal can be reduced. In order to receive the code of Example 1 in FIG. 14 and reproduce it as a moving image,
It is necessary for the receiving terminal to have a function of removing the code of the reduced image portion. Obviously, such a receiving terminal is also included in the present invention.

The reduced image code and the moving image code having no reduced image code inserted therein can be multiplexed and transmitted in the system layer. ISO / IEC 11172-1 (MPEG1 system) as system layer, ISO / I
EC 13818-1 (MPEG2 system), ITU-T H.221 (I
SDN videophone multiplexing), ITU-T H.223 (videophone multiplexing for analog modems), ITU-T H.225 (LA
There are international standards such as multiplexing for videophones for N). For multiplex transmission at the system layer, IP (Intern
et Protocol) packets and ATM (Asynchronous Transf)
er Mode) Packet transmission of cells or the like can be applied.

At this time, the receiving terminal is provided with a separating circuit for separating a desired code from a corresponding system layer, so that a normal reproducing circuit (a reproducing circuit having no function of removing a reduced image inserted in a moving image) is provided. ) Can be used to play back moving images. Various devices related to the above,
That is, a multiplexing device, a conversion device, and a multiplexing transmission device that multiplex the reduced image code and the moving image code in the system layer, a receiving terminal that receives the multiplexed code, and an image that multiplexes the reduced image code and the moving image code in the system layer and transmits the multiplexed code. The transmission system and the image communication system are included in the present invention.

Example 2 of the video code 7 in FIG. 14 is an example in which each frame of the inter-frame code is converted into the intra-frame code of the reduced image. Generally, the intra-frame code is easier to reproduce than the inter-frame code, and in the case of Example 2, the image size is small, so that the amount of processing required for reproduction is further reduced. Accordingly, the apparatus for receiving and reproducing the code of Example 2 is much simpler than an ordinary reproducing apparatus. For example, software processing by a low-speed processor becomes possible, or the processor performs a plurality of processings simultaneously (by time division). In this case, there is an advantage that the reproduction can be performed after a sufficient processing amount is allocated to other processing.

In the example 3 of the output code 7 in FIG. 14, some frames of the code of the example 2 are thinned to further reduce the processing amount at the time of reproduction and the transmission code amount. Example 2,
The reference numeral of Example 3 can be used as a modification of the case of Example 1.

<Embodiment 4> FIG. 15 shows a modification of the video code conversion apparatus 300 having the conversion section 401 shown in FIG.
In the figure, reference numeral 551 denotes a recognition circuit that detects a scene change point of a video sequence from the intra-frame code 302 and outputs a selection signal 106. Reference numeral 550 denotes a video code conversion device obtained by adding the recognition circuit 551 to the video code conversion device 300. It is. In the conversion device 300 having the conversion unit 401 shown in FIG.
Although the frame selected by 106, that is, the frame specified by the user, is converted into an intra-frame code, the conversion device 550 of the present embodiment automatically determines a frame to be an intra-frame code in the conversion device and performs conversion. Perform Specifically, a scene change portion of the video sequence is detected, and the first frame of the new scene is converted into an intra-frame code.

The input video code 2 is converted into an intra-frame code (reproduced DCT signal) 302 by the conversion section 401 and stored in the storage device 303, as in the case of FIG. 11, but has a time delay. The original inter-frame code 304 is stored in the storage device 305. The reproduced DCT signal 302 is input to the recognition circuit 551 at the same time as being stored, and a scene change is detected. If it is determined that a scene change has occurred, the selection signal 106 selects an intra-frame code for the frame immediately after the scene change.

As described above, by encoding the first frame of each scene in a frame, each scene can be reproduced independently, which is convenient for applications such as random access and retrieval.

FIG. 16 is a detailed diagram of the recognition circuit 551.
The input reproduced DCT signal 302 is compared with the reproduced DCT signal 561 of the previous frame stored in the memory 560 and the comparison circuit 562.
And the comparison result is output as the selection signal 106. The reproduced DCT signal 302 to be compared is simultaneously stored in the memory 560, and is used as the reproduced DCT signal 561 in the next frame comparison.

As a measure of comparison, the magnitude of the difference between spatially corresponding signals in two temporally different frames is used. The magnitude of the difference is, specifically,
It is obtained by accumulating the absolute value or the square value of the difference between the DC components of the blocks at the same screen position. Other methods of calculating the magnitude of the difference include counting the number of blocks in which the difference is larger than a predetermined value, and examining the difference in the frequency distribution of the corresponding block (the range in which valid DCT coefficients are distributed). is there.

Although such a comparison can be made in the pixel area, a more accurate comparison can be made by performing the comparison in the DCT coefficient area, that is, the frequency domain as in the above-mentioned method.

FIG. 17 shows an example of code conversion based on the result of comparing scene changes. Example 1 is an example in which frames (5, 9) immediately after a scene change are converted into intra-frame codes, Example 2
Is an example in which a frame immediately after a scene change is converted into an intra-frame code, and the reduced image is inserted for recording and retrieval. In Example 3, only the reduced image is inserted without conversion into an intra-frame code. It is an example. Either case can be used as a modification to the example of FIG.

When a scene change occurs, the correlation between frames at that portion is reduced. Therefore, the amount of generated codes may be smaller when intra-frame encoding is performed than when inter-frame encoding is performed. For example, Example 1
May be smaller than the code amount of the original code 304 in some cases.

In FIG. 15, the reproduced DCT signal 302 and code 3
04 is processed after being stored in storage devices 303 and 305, respectively.
By using a buffer (memory) as the storage device, the conversion device 550 has a simpler configuration. The present invention also includes a method of storing the recognition result in another storage device, one of the storage device 303 and the storage device 305, reading the code from the storage device, and performing no recognition process when combining the codes.

The recognition circuit 551 is premised on detecting a scene change. Conversely, the recognition circuit 551 detects a place where there is no change in a scene (a still image), and converts an intra-frame code or a reduced-image intra-frame code into them. By multiplexing and inserting, the outline of the transmission sequence can be easily reproduced and searched.

<Embodiment 5> FIG. 1 shows an example of the configuration of a receiving apparatus for receiving the video code 7 output from the video code conversion unit 401 shown in FIGS. 11 and 15, that is, a moving image code including a reduced image.
FIG. The input video code 7 is converted to a code separation circuit 601.
, And are separated into a moving image code (a part which is not a reduced image) 602 and a reduced image code 612, and switches 603 and 61, respectively.
The data is stored in the storage devices 620 and 630 via 3. The recorded signal is read from each recording device, input to the decoding circuit 605 and the decoding circuit 615 via the switches 603 and 613, respectively, and reproduced.

The decoding circuit 605 has the same configuration as the decoding circuit 3 shown in FIG. 24, and decodes a general moving image code. The decoding circuit 615 decodes the reduced intra-frame code, and has the same variable length decoding circuit 20 and inverse quantization circuit 22 as the decoding circuit 3 of FIG. And a circuit for performing an inverse DCT transform of × N data.

The outputs of the decoding circuits 605 and 615 are a reproduced image 606 and a reduced reproduced image 616, respectively, and both are inputted to the selection display circuit 607. The reduced reproduction image 616 is simultaneously stored in a memory (not shown), and when displaying a plurality of reduced reproduction images, the signal stored in the memory is read. In the selection display circuit 607, one of the images is selected by an external selection signal 609, and becomes an image signal 608.
The image signal 608 is sent to a display device (not shown) and is displayed as an image. When the selection display circuit 607 performs selection on a screen-by-pixel basis, the following image display can be performed.

Example 1 Only a moving image is displayed. Example 2 A reduced image is displayed on a part of the screen with a moving image as a background. Example 3 One or more reduced images are displayed. Example 4 One or more reduced images are displayed and one of the images is displayed. Display of pseudo-moving image by updating part or all periodically Note that, when displaying a moving image in real time, the receiving device 600 can have a configuration in which the storage device 620 or the storage device 630 is omitted. . Further, the decoding circuits 605 and 615 may be integrated, and one decoding circuit may be shared by the moving image and the reduced image by time division.

<Embodiment 6> FIG. 19 shows an example in which the present invention is applied to an image transmission system. In FIG. 18, reference numeral 700 denotes a video code conversion device 300 having the conversion unit 401 of FIG.
An image transmission system using the receiving device 600 of FIG. The image to be transmitted is encoded by the transmission device 701 from the video signal into an inter-frame code. The configuration of the transmitting device 701 is shown in FIG.
5 is almost the same as the re-encoding circuit 6 shown in FIG. The video code 710 of the encoded image is transmitted to the receiving devices 704-1 to 704-N via the relay device 702.

The relay apparatus 702 includes a circuit of the video coding apparatus 300 for performing intra-frame intra-frame conversion. The video coding apparatus 7- according to the selection signals 106-1 to 106-N sent from each receiving apparatus. Outputs 1 to 7-N. The conversion device 703 in the relay device 702 is one of the inter-frame conversion circuit 101, the buffer 105, the switches 310 and 312, the resolution conversion circuit 402 shown in FIG. 11, and the storage devices 303 and 305 shown in FIG. And N synthesis circuits 104. The combining circuit 104 is provided for each receiving device, but the other circuits are used in common for N receiving devices. In the conventional relay device, each of the other circuits requires N units. Therefore, the present invention greatly reduces the circuit scale.

In the image transmission system 700 shown in FIG. 19, the viewer can reproduce from an arbitrary part of the code stored in the conversion device 703 in the relay device 702. Further, it is possible to select a code including a reduced image or the like and display the code in the receiving device 600 in a free screen arrangement.

In the above image transmission system, the video code 2 of the inter-frame code input to the relay device 702 is one type, but the system is configured to transmit a plurality of types (M types) of video codes. It is possible to To do so, M relay devices 702 are prepared, M kinds of video codes (programs) are input to each relay device, and each receiving device can select any of the M relay devices. What is necessary is just to provide each receiving device with a switching circuit.

The video codes 7-1 to 7-N may be transmitted to the respective receiving devices via independent transmission paths. It may be multiplexed and transmitted.

Embodiment 7 FIG. 20 shows an example in which the present invention is applied to multipoint image communication. Multipoint image communication system 800
Are terminals 802-1 to 80-8 having a transmitting device 802 in addition to the receiving device 600.
02-N, a multipoint communication control device 803 that controls intercommunication between terminals 810-1 to 810-N arranged at a plurality of points, and a terminal 810.
-1 to 810-N transmission devices 802-1 to 802-N output from inter-frame coded video codes 710-1 to 710-N and perform conversion from video conversion devices 804-1 to 804-N. Become.

The conversion devices 804-1 to 804-N are shown in FIGS.
Are devices that perform the same processing as the conversion devices 100 and 300 shown in FIG.
2-1 to 102-N and the reduced image frame codes 403-1 to 403-N are output. These video codes are transmitted to the multipoint communication controller 803.
Is input to

The multipoint communication control device 803 includes, among the video codes of the other party (eg, 810-2 to 810-N) communicating with one terminal (eg, 810-1), One of the inter-frame code, intra-frame code, and reduced image intra-frame code is selected according to the instruction of the communication party (selection signal 106-1), and transmitted to the communication equipment.

FIG. 21 shows an operation example of the multipoint image communication system 800 of FIG. 20 and a display screen during the operation. FIG.
The lower time chart shows a case where a multipoint videoconference is being held with a plurality of parties (seven points) and a plurality of video codes (moving image 3 and still image 4) are multiplexed and received as one video code. The code configuration is shown. Correspondents are A, B, C at the first time (left end of the time chart).
, And still images (quasi-moving images) are received from the remaining four points. The display screen in that case is shown in the upper left of FIG. Next, as shown in the time chart, the communication person changes the moving image at the point C to the moving image at the point D using the selection signal 106 during the communication, and changes the moving image at the point B to the moving image at the point E. . When a moving image is changed, the head of the code is an intra-frame coding from a new point. As a result, the reception screen is switched to the screen shown in the upper right part of FIG. 21 without the video being interrupted or greatly disturbed.

Note that the following modifications are also included in the present invention.
By displaying characters, symbols, symbols, or the like on the screen indicating that the screen is the screen of the selected partner, the selected party can be easily confirmed. When the selection destination of the moving image to be displayed is changed (for example, C → D), a special image, for example, a blue-only image is displayed in order to notify the screen switching.
To insert between the image of D and the image of D, or to display that the screen has been switched for a while after being switched to the image of D, for example, display a character, a symbol, or a sign indicating switching, or a screen frame portion By changing to a specific color or adding a luminance frame, it is possible to clearly notify that the content of the screen has been switched.

Although the configuration shown in FIG. 20 is a system for conducting a multipoint video conference, a multipoint monitoring system can be realized with the same configuration. For example, a system can be configured by using the terminal 810-1 as a monitoring center and the other terminals 810-2 to 810-N as monitoring cameras. In that case, the transmitting device 802-1 of the terminal 810-1 of the monitoring center and the other terminals 810-2 to 810-N
Of the receiving devices 600-2 to 600-N can be deleted.

[0109]

According to the present invention, the intra-frame conversion of the video code is performed in the DCT area, and when the conversion is not performed, the video code is output as it is. Circuit size can be remarkably reduced as compared with the related art in which encoding is performed again after the reproduced image is reproduced. In addition, since the inter-frame intra-frame conversion circuit can be shared by a plurality of receiving apparatuses, the effect of reducing the circuit scale can be further enhanced when a large number of receiving apparatuses are arranged. It should be noted that a resolution conversion circuit in the DCT region can be adopted as the inter-frame intra-frame conversion circuit, and a function of reducing and enlarging an image can be easily added.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a first embodiment of a video transcoder according to the present invention.

FIG. 2 is a block diagram for explaining an inter-frame intra-frame conversion circuit according to the first embodiment;

FIG. 3 is a diagram for explaining motion compensation in a DCT domain.

FIG. 4 is a view for explaining a procedure of a motion compensation conversion in a DCT domain.

FIG. 5 is a block diagram for explaining a DCT area motion compensation circuit used in the inter-frame intra-frame conversion circuit according to the first embodiment;

FIG. 6 is an exemplary view for explaining a processing procedure of the DCT area motion compensation circuit of FIG. 5;

FIG. 7 is a block diagram illustrating a synthesis circuit according to the first embodiment;

FIG. 8 is a block diagram for explaining a second embodiment of the present invention.

FIG. 9 is a block diagram illustrating a video code converter according to a second embodiment;

FIG. 10 is a diagram for explaining the operation of the video code converter according to the second embodiment.

FIG. 11 is a block diagram for explaining a third embodiment of the present invention.

FIG. 12 is a block diagram illustrating a resolution conversion circuit according to a third embodiment.

FIG. 13 is a view for explaining resolution conversion.

FIG. 14 is a diagram for explaining the operation of the resolution conversion circuit according to the third embodiment.

FIG. 15 is a block diagram for explaining a fourth embodiment of the present invention.

FIG. 16 is a block diagram illustrating a recognition circuit according to a fourth embodiment;

FIG. 17 is a diagram for explaining the operation of the fourth embodiment.

FIG. 18 is a block diagram for explaining a fifth embodiment of the present invention.

FIG. 19 is a block diagram for explaining a sixth embodiment of the present invention.

FIG. 20 is a block diagram for explaining a seventh embodiment of the present invention.

FIG. 21 is a diagram for explaining the operation of the seventh embodiment.

FIG. 22 is a diagram for explaining the concept of motion-compensated inter-frame prediction coding.

FIG. 23 is a block diagram for explaining a conventional video code conversion device.

FIG. 24 is a block diagram for explaining a decoding circuit of a conventional video code conversion device.

FIG. 25 is a block diagram for explaining a re-encoding circuit of a conventional video code conversion device.

[Explanation of symbols]

2, 7, 103: video code, 20: variable length decoding circuit, 22
... Inverse quantization circuit, 100 ... Video code converter, 101 ... Inter-frame intra-frame conversion circuit, 102 ... Intra-frame signal (reproduced DCT signal), 104 ... Synthesis circuit, 105 ... Buffer, 106 ...
Selection signal, 111 ... variable length coding circuit, 113 ... control circuit, 11
5: selection circuit, 201: DCT area motion compensation circuit, 203: addition circuit, 205: frame memory, 402: resolution conversion circuit.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Tetsu Date 1-280 Higashi Koigabo, Kokubunji-shi, Tokyo F-term in Central Research Laboratory, Hitachi, Ltd. 5C057 AA01 AA06 CC04 EA02 EA07 EB18 ED01 ED07 EJ02 EK02 EL01 EM02 EM04 EM07 EM14 GF07 GG01 GL00 5C059 KK38 LB05 MA05 MA23 MC00 MC34 PP05 PP06 SS02 SS07 SS13 TA19 TA47 TB04 TC01 UA34

Claims (3)

[Claims] 1. DCT (Discrete cosine transform)
A video code of a moving image composed of at least one frame that is intra-coded by transform and a plurality of frames that are inter-coded by a combination of DCT transform and motion compensation is input, and inter-frame coded. Converting a part of the plurality of frames into an intra-coded frame and outputting the converted frame, wherein the plurality of inter-coded frames are converted into an intra-coded frame in a DCT domain. And temporarily storing the video code, and selecting and outputting any one of the video code obtained by the inter-frame intra-frame code conversion process and the temporarily stored video code. Video code conversion method. 2. DCT (Discrete cosine transform)
A video code of a moving image composed of at least one frame that is intra-coded by transform and a plurality of frames that are inter-coded by a combination of DCT transform and motion compensation is input, and inter-frame coded. And converting a part of the plurality of frames into an intra-coded frame and outputting the frame, wherein the plurality of inter-coded frames are converted into an intra-coded frame in a DCT domain. Inter-frame intra-frame code conversion circuit, a buffer for temporarily holding the video code, and a synthesizing circuit for selecting and outputting one of the video code output from the inter-frame intra-frame code conversion circuit and the video code in the buffer And a video transcoder. 3. A resolution conversion circuit for changing a resolution of a video code output from the inter-frame intra-frame code conversion circuit is further provided between the inter-frame intra-frame code conversion circuit and the synthesizing circuit. The conversion circuit outputs a video code of an image whose size is arbitrarily reduced or enlarged by a change in resolution, and the video code output from the intra-frame intra-frame conversion circuit selected by the synthesis circuit is a video code passed through the resolution conversion circuit. The video transcoder according to claim 2, wherein: