JP2000181679A - Intra-chip communication data compression technique - Google Patents

Abstract

PROBLEM TO BE SOLVED: To parallel perform a collation operation in compression and expansion and to perform efficient communication based on data compression between modules in a processor. SOLUTION: Data is compressed in a data transfer mode by using a memory and computing element integrated type parallel processor architecture for compressing and expanding data. Transmitting data is compressed in a compression module 3 of a module A1 and is transferred to a module B2. An expansion module 4 of a module B2 expands received data. In such a case, 'instantaneously decodable' algorithm, that is, such algorithm as to start to expand just after a module B receives data is used as compression algorithm. Then, it is possible to overlap expansion time 8 and transfer time 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

According to the present invention, communication between modules in a processor can be performed at high speed with a small number of wires.

[0002]

2. Description of the Related Art In a conventional data transfer between modules in a processor, a method of increasing the number of wirings has been mainly used when high-speed data transfer is required.

Further, as a technique for performing high-speed data transfer with a small number of wires, in the field of computer networks, a technique of compressing data and then performing communication between computers has been proposed. In this case, data compression is performed by software using a general-purpose signal processor or the like.

[0004]

In communication within a processor, in order to perform high-speed data communication with a small number of wires, it is considered that data is compressed and then transferred between modules. Within the processor, faster communication is required as compared to computer networks. Therefore, high-speed data compression / decompression is required. However, in the compression of data, the amount of calculation of the matching operation for detecting data redundancy is large,
It has been difficult for conventional software methods to satisfy the demand for higher speed.

[0005]

In order to solve this problem, we propose a memory / operation unit integrated parallel processor architecture for data compression / decompression.

[0006]

[Operation] It is possible to perform collation operations in compression and decompression in parallel, and between modules in a processor,
Efficient communication based on data compression becomes possible.

Embodiments will be described with reference to the drawings.
In FIG. 1, module A (1) to module B
Consider performing data transfer to (2). FIG. 2 shows an example of a time chart at the time of data transfer. The transmission data is compressed in the compression module (3) of the module A (1) and transferred to the module B (2). The expansion module (4) of the module B (2) expands the received data. In FIG. 2, it is assumed that an algorithm that is “instantaneously decodable”, that is, an algorithm that can start decompression immediately after receiving data in module B, is used as the compression algorithm. It is possible to overlap time (8). In FIG. 2, Tenc (9), Tde
c (10) represents a delay for generating the first transfer data and a delay for expanding the last received data, respectively. It is assumed that the bit length of the data to be transmitted is W [bits], the capacity of the transfer path is C [bits / second], and the compression ratio is R = (bit length after compression) / (bit length before compression). .
The total transfer time T is given by the following equation.

FIG. 3 shows an embodiment based on the associative memory of the compression module. An input symbol (13), which is an element of data to be transferred, is input to the associative memory. Input symbol (13)
Is checked in parallel by the comparator (16) with the contents of the word (15) in the associative memory and the input symbol (13) in order to check whether there is a word that matches. If a matching word (15) exists, instead of transferring the word, data called reference number (18) is transferred. Reference numeral (18) represents an address, which can be shortened compared to the bit length of a normal input symbol, and as a result, compression becomes possible. If there is no matching word,
The input symbols are stored in an associative memory.

FIG. 4 shows an embodiment of the decompression module. The decompression module stores the received data at the address indicated by the reference number. Word (22) already stored
Is input, the content of the word (22) is read. This is the decompressed data.

[0009]

(Equation 1)

[0010]

The present invention is embodied in the form described above and has the following effects. For example, if the compression ratio is r = 0.1, the entire transfer time can be reduced to 1/10 as compared with the case where the transfer is performed without compression.

[Brief description of the drawings]

FIG. 1 is a model of data communication within a processor.

FIG. 2 is a time chart when communication is performed using the model of FIG. 1;

FIG. 3 is an embodiment of a compression module using an associative memory.

FIG. 4 is an embodiment of a decompression module.

[Description of sign]

1 Module A in Processor 2 Module B in Processor 3 Module for Data Compression 4 Module for Data Decompression 5 Data Transfer Path 6 Time to Compress Transmission Data 7 Time to Transfer Transmission Data after Compression 8 Receive Data Decompression time 9 Time to compress the first transmission data 10 Time to decompress the last reception data 11 Time from the start of compression of the first transmission data to the end of decompression of the last reception data 12 Address counter of compression module 13 Input symbol of transfer data 14 Address data coder of compression module 15 Memory word of compression module 16 Comparator of compression module 17 Address generation circuit of compression module 18 Reference number 20 Output of address counter of decompression module 21 Decompression module No Symbol corresponding to the memory word 24 reference numbers less decoder 22 extended symbol 23 extension modules

Claims (1)

[Claims] 1. A processor architecture integrated with a memory and an arithmetic unit for data compression and data decompression.